TLC2272CPS [TI]
TLC227x, TLC227xA: Advanced LinCMOS Rail-to-Rail Operational Amplifiers;
| 型号： | TLC2272CPS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLC227x, TLC227xA: Advanced LinCMOS Rail-to-Rail Operational Amplifiers |
| 文件： | 总55页 (文件大小：2479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
TLC227x, TLC227xA: Advanced LinCMOS Rail-to-Rail Operational Amplifiers
The TLC227x also make great upgrades to the
TLC27x in standard designs. They offer increased
output dynamic range, lower noise voltage, and lower
input offset voltage. This enhanced feature set allows
them to be used in a wider range of applications. For
applications that require higher output drive and wider
input voltage range, see the TLV2432 and TLV2442
devices.
1 Features
1
•
•
•
•
Output Swing Includes Both Supply Rails
Low Noise: 9 nV/√Hz Typical at f = 1 kHz
Low-Input Bias Current: 1-pA Typical
Fully-Specified for Both Single-Supply and Split-
Supply Operation
•
Common-Mode Input Voltage Range Includes
Negative Rail
If the design requires single amplifiers, see the
TLV2211, TLV2221 and TLV2231 family. These
devices are single rail-to-rail operational amplifiers in
the SOT-23 package. Their small size and low power
consumption make them ideal for high density,
battery-powered equipment.
•
•
•
High-Gain Bandwidth: 2.2-MHz Typical
High Slew Rate: 3.6-V/μs Typical
Low Input Offset Voltage: 950 μV Maximum at
TA = 25°C
•
•
Macromodel Included
Device Information(1)
Performance Upgrades for the TLC272 and
TLC274
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.40 mm × 3.00 mm
3.91 mm × 4.90 mm
5.30 mm × 6.20 mm
6.35 mm × 9.81 mm
4.40 mm × 5.00 mm
3.91 mm × 8.65 mm
TSSOP (8)
•
Available in Q-Temp Automotive
SOIC (8)
SO (8)
TLC2272
2 Applications
PDIP (8)
TSSOP (14)
SOIC (14)
•
•
•
•
•
White Goods (Refrigerators, Washing Machines)
Hand-held Monitoring Systems
Configuration Control and Print Support
Transducer Interfaces
5.30 mm × 10.30
mm
TLC2274
SO (14)
6.35 mm × 19.30
mm
PDIP (14)
Battery-Powered Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The TLC2272 and TLC2274 are dual and quadruple
operational amplifiers from Texas Instruments. Both
devices exhibit rail-to-rail output performance for
increased dynamic range in single- or split-supply
applications. The TLC227x family offers 2 MHz of
bandwidth and 3 V/μs of slew rate for higher-speed
applications. These devices offer comparable AC
performance while having better noise, input offset
voltage, and power dissipation than existing CMOS
operational amplifiers. The TLC227x has a noise
voltage of 9 nV/√Hz, two times lower than competitive
solutions.
Maximum Peak-to-Peak Output Voltage vs
Supply Voltage
16
T
A
= 25°C
14
12
10
8
I
O
=
50 µA
The TLC227x family of devices, exhibiting high input
impedance and low noise, is excellent for small-signal
conditioning for high-impedance sources such as
piezoelectric transducers. Because of the micropower
dissipation levels, these devices work well in hand-
held monitoring and remote-sensing applications. In
addition, the rail-to-rail output feature, with single- or
split-supplies, makes this family a great choice when
interfacing with analog-to-digital converters (ADCs).
For precision applications, the TLC227xA family is
available with a maximum input offset voltage of
950 μV. This family is fully characterized at 5 V and
I
O
=
500 µA
6
4
4
6
8
10
12
14
16
|V
DD
| − Supply Voltage − V
±5 V.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
www.ti.com
Table of Contents
7.1 Overview ................................................................. 24
7.2 Functional Block Diagram ....................................... 24
7.3 Feature Description................................................. 24
7.4 Device Functional Modes........................................ 24
Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 26
Power Supply Recommendations...................... 28
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
8
9
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1 Related Links ........................................................ 30
11.2 Community Resources.......................................... 30
11.3 Trademarks........................................................... 30
11.4 Electrostatic Discharge Caution............................ 30
11.5 Glossary................................................................ 30
6.5 TLC2272 and TLC2272A Electrical Characteristics
VDD = 5 V ................................................................... 6
6.6 TLC2272 and TLC2272A Electrical Characteristics
VDD± = ±5 V................................................................ 8
6.7 TLC2274 and TLC2274A Electrical Characteristics
VDD = 5 V ................................................................... 9
6.8 TLC2274 and TLC2274A Electrical Characteristics
VDD± = ±5 V.............................................................. 11
12 Mechanical, Packaging, and Orderable
6.9 Typical Characteristics............................................ 13
Information ........................................................... 30
7
Detailed Description ............................................ 24
4 Revision History
Changes from Revision G (May 2004) to Revision H
Page
•
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Supportsection, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
Added ESD Rating table for the D and PW package devices. .............................................................................................. 5
2
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
5 Pin Configuration and Functions
TLC2272
D, JG, P, or PW Package
8-Pin SOIC, CDIP, PDIP, or TSSOP
Top View
TLC2274
D, J, N, PW, or W Package
14-Pin SOIC, CDIP, PDIP, TSSOP, or CFP
Top View
1OUT
1IN−
1IN+
/GND
V
DD+
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
1
2
3
4
5
6
7
14
13
12
11
10
9
2OUT
2IN−
2IN+
V
DD−
V
V
DD+
DD−
2IN+
2IN−
3IN+
3IN−
3OUT
TLC2272
2OUT
8
FK Package
20-Pin LCCC
Top View
TLC2274
FK Package
20-Pin LCCC
Top View
3
2 1 20 19
NC
NC
1 IN−
NC
18
17
16
15
14
4
5
6
7
8
2 OUT
NC
3
2 1 20 19
2 IN−
NC
1 IN+
NC
4IN+
1IN+
18
17
16
15
14
4
5
6
7
8
NC
V
NC
9 10 11 12 13
V
DD−
DD+
NC
NC
3IN+
2IN+
9 10 11 12 13
TLC2272
U Package
10-Pin CFP
Top View
NC
NC
1
2
3
4
5
10
9
1 OUT
1 IN−
1 IN+
/GND
V
DD+
8
2 OUT
2 IN−
2 IN+
7
6
V
DD−
Copyright © 1997–2016, Texas Instruments Incorporated
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TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
www.ti.com
Pin Functions
PIN
NO.
I/O
DESCRIPTION
TLC2272
NAME
TLC2274
FK
D, JG, P,
or PW
D, J, N,
PW, or W
FK
U
1IN+
3
2
7
4
3
3
2
4
3
I
I
Non-inverting input, Channel 1
Inverting input, Channel 1
Output, Channel 1
1IN-
5
1OUT
2IN+
1
2
2
1
2
O
I
5
12
15
17
—
—
—
—
—
—
20
—
10
6
5
8
Non-inverting input, Channel 2
Inverting input, Channel 2
Output, Channel 2
2IN-
6
7
6
9
I
2OUT
3IN+
7
8
7
10
14
13
12
18
19
20
6
O
I
—
—
—
—
—
—
8
—
—
—
—
—
—
9
10
9
Non-inverting input, Channel 3
Inverting input, Channel 3
Output, Channel 3
3IN-
I
3OUT
4IN+
8
O
I
12
13
14
4
Non-inverting input, Channel 4
Inverting input, Channel 4
Output, Channel 4
4IN-
I
4OUT
VDD+
VDD–
O
—
—
—
Positive (highest) supply
Negative (lowest) supply
Negative (lowest) supply
—
4
—
5
11
—
16
—
VDD–/GND
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
1, 5, 7, 11,
15, 17
NC
—
1, 10
—
—
No Connection
4
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–8
MAX
UNIT
V
(2)
Supply voltage, VDD
+
8
(2)
VDD
-
V
(3)
Differential input voltage, VID
±16
VDD+
±5
V
Input voltage, VI(any input)(2)
Input current, II (any input)
Output current, IO
VDD− − 0.3
V
mA
mA
mA
mA
±50
±50
±50
Total current into VDD+
Total current out of VDD–
Duration of short-circuit current at (or below) 25°C(4)
Unlimited
C level parts
0
70
Operating free-air temperature range, TA
I, Q level parts
M level parts
–40
–55
125
125
260
300
150
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds
Storage temperature, Tstg
D, N, P or PW package
J or U package
°C
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD
.
(3) Differential voltages are at IN+ with respect to IN–. Excessive current will flow if input is brought below VDD– − 0.3 V.
(4) The output may be shorted to either supply. Temperature or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q-grade and M-grade devices in D and
±2000
Q100-002(1)
PW packages
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per
AEC Q100-011
Q-grade and M-grade devices in D and
PW packages
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
±2.2
±2.2
±2.2
±2.2
VDD−
VDD−
VDD−
VDD−
VDD−
VDD−
VDD−
VDD−
MAX
UNIT
C LEVEL PARTS
I LEVEL PARTS
Q LEVEL PARTS
M LEVEL PARTS
C LEVEL PARTS
I LEVEL PARTS
Q LEVEL PARTS
M LEVEL PARTS
C LEVEL PARTS
I LEVEL PARTS
Q LEVEL PARTS
M LEVEL PARTS
±8
±8
VDD±
Supply voltage
V
V
V
±8
±8
V
V
V
V
V
V
V
V
DD+ −1.5
DD+ −1.5
DD+ −1.5
DD+ −1.5
DD+ −1.5
DD+ −1.5
DD+ −1.5
DD+ −1.5
VI
Input voltage
VIC
Common-mode input voltage
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
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Recommended Operating Conditions (continued)
MIN
0
MAX
70
UNIT
C LEVEL PARTS
I LEVEL PARTS
Q LEVEL PARTS
M LEVEL PARTS
–40
–40
–55
125
125
125
TA
Operating free-air temperature
°C
6.4 Thermal Information
THERMAL METRIC(1)
TLC2272
PW
TLC2274
PW
D
P
FK
(LCCC)
U
(CFP)
D
N
FK
J
UNIT
(SOIC)
(PDIP) (TSSOP)
(SOIC)
(PDIP) (TSSOP)
(LCCC) (CDIP)
8-PIN
8-PIN
8-PIN
20-PIN
10-PIN
14-PIN
14-PIN
14-PIN
20-PIN
14-PIN
Junction-to-ambient thermal
resistance
RθJA
115.6
58.5
175.8
—
—
83.8
—
111.6
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(2)(3)
Junction-to-case (top) thermal
RθJC(top)
61.8
55.9
14.3
55.4
—
48.3
35.6
25.9
35.5
—
58.8
104.3
5.9
18
—
—
—
—
121.3
—
43.2
38.4
9.4
34
—
—
—
—
41.2
54.7
3.9
16
—
—
—
—
16.2
—
(2)(3)
resistance
Junction-to-board thermal
resistance
RθJB
Junction-to-top
ψJT
—
—
characterization parameter
Junction-to-board
ψJB
102.6
—
—
38.1
—
53.9
—
—
characterization parameter
Junction-to-case (bottom)
RθJC(bot)
8.68
—
thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) − TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).
6.5 TLC2272 and TLC2272A Electrical Characteristics VDD = 5 V
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
300
300
MAX UNIT
TLC2272
2500
TA = 25°C
TLC2272A
950
µV
3000
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
VIO
Input offset voltage
TLC2272
Full Range(1)
TLC2272A
1500
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift(2)
αVIO
VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω
VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω
2
μV/°C
0.002
0.5
μV/mo
All level parts
C level part
I level part
TA = 25°C
60
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
IIO
Input offset current
150
800
800
60
pA
Q level part
M level part
All level parts
C level part
I level part
1
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
150
800
800
4
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
IIB
Input bias current
pA
V
Q level part
M level part
–0.3
0
2.5
2.5
VICR
Common-mode input voltage
RS = 50 Ω; |VIO | ≤ 5 mV
Full Range(1)
3.5
(1) TA = –55°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
TLC2272 and TLC2272A Electrical Characteristics VDD = 5 V (continued)
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
4.99
4.93
MAX UNIT
IOH = −20 μA
IOH = −200 μA
TA = 25°C
Full Range(1)
4.85
4.85
4.25
4.25
VOH
High-level output voltage
V
TA = 25°C
Full Range(1)
4.65
IOH = −1 mA
IOL = 50 μA
0.01
0.09
TA = 25°C
Full Range(1)
0.15
IOL = 500 μA
VOL
Low-level output voltage
VIC = 2.5 V
0.15
1.5
V
TA = 25°C
0.9
35
35
35
35
IOL = 5 mA
C level part
I level part
Q level part
M level part
Full Range(1)
TA = 25°C
1.5
15
15
15
15
10
10
10
10
TA = 0°C to 80°C
TA = 25°C
VIC = 2.5 V,
TA = –40°C to 85°C
TA = 25°C
VO = 1 V to 4 V;
Large-signal differential
voltage amplification
RL = 10 kΩ(3)
AVD
V/mV
TA = –40°C to 125°C
TA = 25°C
TA = –55°C to 125°C
VIC = 2.5 V, VO = 1 V to 4 V; RL = 1 MΩ(3)
175
1012
1012
8
rid
ri
Differential input resistance
Ω
Ω
Common-mode input resistance
Common-mode input capacitance
Closed-loop output impedance
ci
f = 10 kHz, P package
f = 1 MHz, AV = 10
pF
Ω
zo
140
75
TA = 25°C
Full Range(1)
70
70
80
80
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50 Ω
CMRR Common-mode rejection ratio
dB
dB
TA = 25°C
95
2.2
3.6
Supply-voltage rejection ratio
kSVR
VDD = 4.4 V to 16 V,
VIC = VDD / 2, no load
Full Range(1)
TA = 25°C
Full Range(1)
(ΔVDD / ΔVIO
)
3
3
IDD
SR
Vn
Supply currrent
VO = 2.5 V, no load
mA
TA = 25°C
Full Range(1)
2.3
1.7
VO = 0.5 V to 2.5 V,
Slew rate at unity gain
Equivalent input noise voltage
V/µs
nV/√Hz
RL = 10 kΩ(3), CL = 100 pF(3)
f = 10 Hz
50
9
f = 1 kHz
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
1
Peak-to-peak equivalent
input noise voltage
VNPP
In
µV
1.4
Equivalent input noise current
0.6
fA/√Hz
AV = 1
0.0013%
0.004%
0.03%
2.18
1
VO = 0.5 V to 2.5 V,
THD+N Total harmonic distortion + noise
AV = 10
AV = 100
f = 20 kHz, RL = 10 kΩ(3)
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ(3), CL = 100 pF(3)
MHz
MHz
BOM
ts
Maximum output-swing bandwidth
Settling time
VO(PP) = 2 V, AV = 1, RL = 10 kΩ(3), CL = 100 pF(3)
AV = –1, RL = 10 kΩ(3)
,
To 0.1%
1.5
µs
Step = 0.5 V to 2.5 V, CL = 100 pF(3)
To 0.01%
2.6
φm
Phase margin at unity gain
Gain margin
RL = 10 kΩ(3), CL = 100 pF(3)
RL = 10 kΩ(3), CL = 100 pF(3)
50°
10
dB
(3) Referenced to 0 V.
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6.6 TLC2272 and TLC2272A Electrical Characteristics VDD± = ±5 V
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
300
300
MAX UNIT
TLC2272
2500
TA = 25°C
TLC2272A
950
µV
3000
VIC = 0 V, VO = 0 V,
RS = 50 Ω
VIO
Input offset voltage
TLC2272
Full Range(1)
TLC2272A
1500
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift(2)
αVIO
VIC = 0 V, VO = 0 V, RS = 50 Ω
VIC = 0 V, VO = 0 V, RS = 50 Ω
2
μV/°C
0.002
0.5
μV/mo
All level parts
TA = 25°C
60
C level part
I level part
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
VIC = 0 V, VO = 0 V,
RS = 50 Ω
IIO
Input offset current
150
800
800
60
pA
Q level part
M level part
All level parts
C level part
I level part
1
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
150
800
800
4
VIC = 0 V, VO = 0 V,
RS = 50 Ω
IIB
Input bias current
pA
V
Q level part
M level part
–5.3
–5
0
0
VICR
Common-mode input voltage
RS = 50 Ω; |VIO | ≤ 5 mV
IO = −20 μA
Full Range(1)
3.5
4.99
4.93
TA = 25°C
Full Range(1)
4.85
4.85
4.25
4.25
IO = −200 μA
Maximum positive peak
output voltage
VOM+
V
TA = 25°C
Full Range(1)
4.65
IO = −1 mA
IO = 50 μA
–4.99
–4.91
TA = 25°C
Full Range(1)
–4.85
–4.85
–3.5
–3.5
25
IO = 500 μA
Maximum negative
peak output voltage
VOM-
VIC = 0 V,
V
TA = 25°C
–4.1
50
IO = 5 mA
Full Range(1)
TA = 25°C
C level part
I level part
Q level part
M level part
TA = 0°C to 80°C
TA = 25°C
25
25
50
TA = –40°C to 85°C
TA = 25°C
25
VO = ±4 V; RL = 10 kΩ
Large-signal differential
voltage amplification
AVD
20
50
V/mV
TA = –40°C to 125°C
TA = 25°C
20
20
50
TA = –55°C to 125°C
20
VO = ±4 V; RL = 1 MΩ
300
1012
1012
8
rid
ri
Differential input resistance
Ω
Ω
Common-mode input resistance
Common-mode input capacitance
Closed-loop output impedance
ci
f = 10 kHz, P package
f = 1 MHz, AV = 10
pF
Ω
zo
130
80
TA = 25°C
Full Range(1)
75
75
80
80
VIC = –5 V to 2.7 V,
VO = 0 V, RS = 50 Ω
CMRR Common-mode rejection ratio
dB
dB
TA = 25°C
95
Supply-voltage rejection ratio
kSVR
VDD+ = 2.2 V to ±8 V,
VIC = 0 V, no load
Full Range(1)
TA = 25°C
Full Range(1)
(ΔVDD / ΔVIO
)
2.4
3
3
IDD
Supply currrent
VO = 0 V, no load
mA
(1) TA = –55°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
8
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TLC2272 and TLC2272A Electrical Characteristics VDD± = ±5 V (continued)
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
2.3
TYP
MAX UNIT
TA = 25°C
Full Range(1)
3.6
VO = ±2.3 V,
SR
Vn
Slew rate at unity gain
V/µs
RL = 10 kΩ, CL = 100 pF
1.7
f = 10 Hz
50
9
Equivalent input noise voltage
nV/√Hz
f = 1 kHz
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
1
Peak-to-peak equivalent
input noise voltage
VNPP
In
µV
1.4
Equivalent input noise current
0.6
fA/√Hz
AV = 1
0.0011%
0.004%
0.03%
2.25
0.54
1.5
VO = ±2.3,
f = 20 kHz, RL = 10 kΩ
THD+N Total harmonic distortion + noise
Gain-bandwidth product
AV = 10
AV = 100
f = 10 kHz, RL = 10 kΩ, CL = 100 pF
MHz
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 4.6 V, AV = 1, RL = 10 kΩ, CL = 100 pF
To 0.1%
To 0.01%
AV = –1, RL = 10 kΩ,
Step = –2.3 V to 2.3 V, CL = 100 pF
ts
Settling time
µs
3.2
φm
Phase margin at unity gain
Gain margin
RL = 10 kΩ, CL = 100 pF
RL = 10 kΩ, CL = 100 pF
52°
10
dB
6.7 TLC2274 and TLC2274A Electrical Characteristics VDD = 5 V
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
300
300
MAX UNIT
TLC2274
2500
TA = 25°C
TLC2274A
950
µV
3000
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
VIO
Input offset voltage
TLC2274
Full Range(1)
TLC2274A
1500
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift(2)
αVIO
VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω
VIC = 0 V, VDD± = ±2.5 V, VO = 0 V, RS = 50 Ω
2
μV/°C
0.002
0.5
μV/mo
All level parts
C level part
I level part
TA = 25°C
60
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
IIO
Input offset current
150
800
800
60
pA
Q level part
M level part
All level parts
C level part
I level part
1
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
150
800
800
4
VIC = 0 V, VDD± = ±2.5 V,
VO = 0 V, RS = 50 Ω
IIB
Input bias current
pA
V
Q level part
M level part
–0.3
0
2.5
2.5
VICR
Common-mode input voltage
High-level output voltage
RS = 50 Ω; |VIO | ≤ 5 mV
IOH = −20 μA
Full Range(1)
3.5
4.99
4.93
TA = 25°C
Full Range(1)
4.85
4.85
4.25
4.25
IOH = −200 μA
VOH
V
TA = 25°C
Full Range(1)
4.65
IOH = −1 mA
(1) TA = –55°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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TLC2274 and TLC2274A Electrical Characteristics VDD = 5 V (continued)
at specified free-air temperature, VDD = 5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.01
0.09
MAX UNIT
IOL = 50 μA
TA = 25°C
0.15
IOL = 500 μA
IOL = 5 mA
C level part
I level part
Q level part
M level part
VOL
Low-level output voltage
VIC = 2.5 V
Full Range(1)
0.15
1.5
V
TA = 25°C
0.9
35
35
35
35
Full Range(1)
TA = 25°C
1.5
15
15
15
15
10
10
10
10
TA = 0°C to 80°C
TA = 25°C
VIC = 2.5 V, VO = 1 V to
4 V;
TA = –40°C to 85°C
TA = 25°C
Large-signal differential
voltage amplification
RL = 10 kΩ(3)
AVD
V/mV
TA = –40°C to 125°C
TA = 25°C
TA = –55°C to 125°C
VIC = 2.5 V, VO = 1 V to 4 V; RL = 1 MΩ(3)
175
1012
1012
8
rid
ri
Differential input resistance
Ω
Ω
Common-mode input resistance
Common-mode input capacitance
Closed-loop output impedance
ci
f = 10 kHz, P package
f = 1 MHz, AV = 10
pF
Ω
zo
140
75
TA = 25°C
Full Range(1)
70
70
80
80
VIC = 0 V to 2.7 V,
VO = 2.5 V, RS = 50 Ω
CMRR Common-mode rejection ratio
dB
dB
TA = 25°C
95
4.4
3.6
Supply-voltage rejection ratio
kSVR
VDD = 4.4 V to 16 V,
VIC = VDD / 2, no load
Full Range(1)
TA = 25°C
Full Range(1)
(ΔVDD / ΔVIO
)
6
6
IDD
SR
Vn
Supply currrent
VO = 2.5 V, no load
mA
TA = 25°C
Full Range(1)
2.3
1.7
VO = 0.5 V to 2.5 V,
Slew rate at unity gain
Equivalent input noise voltage
V/µs
nV/√Hz
RL = 10 kΩ(3), CL = 100 pF(3)
f = 10 Hz
50
9
f = 1 kHz
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
1
Peak-to-peak equivalent
input noise voltage
VNPP
In
µV
1.4
Equivalent input noise current
0.6
fA/√Hz
AV = 1
0.0013%
0.004%
0.03%
2.18
1
VO = 0.5 V to 2.5 V,
THD+N Total harmonic distortion + noise
AV = 10
AV = 100
f = 20 kHz, RL = 10 kΩ(3)
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ(3), CL = 100 pF(3)
MHz
MHz
BOM
ts
Maximum output-swing bandwidth
Settling time
VO(PP) = 2 V, AV = 1, RL = 10 kΩ(3), CL = 100 pF(3)
AV = –1, RL = 10 kΩ(3)
,
To 0.1%
1.5
µs
Step = 0.5 V to 2.5 V, CL = 100 pF(3)
To 0.01%
2.6
φm
Phase margin at unity gain
Gain margin
RL = 10 kΩ(3), CL = 100 pF(3)
RL = 10 kΩ(3), CL = 100 pF(3)
50°
10
dB
(3) Referenced to 0 V.
10
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
6.8 TLC2274 and TLC2274A Electrical Characteristics VDD± = ±5 V
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
300
300
MAX UNIT
TLC2274
2500
TA = 25°C
TLC2274A
950
µV
3000
VIC = 0 V, VO = 0 V,
RS = 50 Ω
VIO
Input offset voltage
TLC2274
Full Range(1)
TLC2274A
1500
Temperature coefficient of
input offset voltage
Input offset voltage long-term drift(2)
αVIO
VIC = 0 V, VO = 0 V, RS = 50 Ω
VIC = 0 V, VO = 0 V, RS = 50 Ω
2
μV/°C
0.002
0.5
μV/mo
All level parts
TA = 25°C
60
C level part
I level part
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
VIC = 0 V, VO = 0 V,
RS = 50 Ω
IIO
Input offset current
150
800
800
60
pA
Q level part
M level part
All level parts
C level part
I level part
1
TA = 0°C to 80°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –55°C to 125°C
TA = 25°C
100
150
800
800
4
VIC = 0 V, VO = 0 V,
RS = 50 Ω
IIB
Input bias current
pA
V
Q level part
M level part
–5.3
–5
0
0
VICR
Common-mode input voltage
RS = 50 Ω; |VIO | ≤ 5 mV
IO = −20 μA
Full Range(1)
3.5
4.99
4.93
TA = 25°C
Full Range(1)
4.85
4.85
4.25
4.25
IO = −200 μA
Maximum positive peak
output voltage
VOM+
V
TA = 25°C
Full Range(1)
4.65
IO = −1 mA
IO = 50 μA
–4.99
–4.91
TA = 25°C
Full Range(1)
–4.85
–4.85
–3.5
–3.5
25
IO = 500 μA
Maximum negative peak
output voltage
VOM-
VIC = 0 V
V
TA = 25°C
–4.1
50
IO = 5 mA
Full Range(1)
TA = 25°C
C level part
I level part
Q level part
M level part
TA = 0°C to 80°C
TA = 25°C
25
25
50
TA = –40°C to 85°C
TA = 25°C
25
VO = ±4 V; RL = 10 kΩ
Large-signal differential
voltage amplification
AVD
20
50
V/mV
TA = –40°C to 125°C
TA = 25°C
20
20
50
TA = –55°C to 125°C
20
VO = ±4 V; RL = 1 MΩ
300
1012
1012
8
rid
ri
Differential input resistance
Ω
Ω
Common-mode input resistance
Common-mode input capacitance
Closed-loop output impedance
ci
f = 10 kHz, P package
f = 1 MHz, AV = 10
pF
Ω
zo
130
80
TA = 25°C
Full Range(1)
75
75
80
80
VIC = –5 V to 2.7 V,
VO = 0 V, RS = 50 Ω
CMRR Common-mode rejection ratio
dB
dB
TA = 25°C
95
Supply-voltage rejection ratio
kSVR
VDD+ = 2.2 V to ±8 V,
VIC = 0 V, no load
Full Range(1)
TA = 25°C
Full Range(1)
(ΔVDD / ΔVIO
)
4.8
6
6
IDD
Supply currrent
VO = 0 V, no load
mA
(1) TA = –55°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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TLC2274 and TLC2274A Electrical Characteristics VDD± = ±5 V (continued)
at specified free-air temperature, VDD± = ±5 V; TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
2.3
TYP
MAX UNIT
TA = 25°C
Full Range(1)
3.6
VO = ±2.3 V,
SR
Vn
Slew rate at unity gain
V/µs
RL = 10 kΩ, CL = 100 pF
1.7
f = 10 Hz
50
9
Equivalent input noise voltage
nV/√Hz
f = 1 kHz
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
1
Peak-to-peak equivalent
input noise voltage
VNPP
In
µV
1.4
Equivalent input noise current
0.6
fA/√Hz
AV = 1
0.0011%
0.004%
0.03%
2.25
0.54
1.5
VO = ±2.3,
f = 20 kHz, RL = 10 kΩ
THD+N Total harmonic distortion + noise
Gain-bandwidth product
AV = 10
AV = 100
f = 10 kHz, RL = 10 kΩ, CL = 100 pF
MHz
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 4.6 V, AV = 1, RL = 10 kΩ, CL = 100 pF
To 0.1%
To 0.01%
AV = –1, RL = 10 kΩ,
Step = –2.3 V to 2.3 V, CL = 100 pF
ts
Settling time
µs
3.2
φm
Phase margin at unity gain
Gain margin
RL = 10 kΩ, CL = 100 pF
RL = 10 kΩ, CL = 100 pF
52°
10
dB
12
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
6.9 Typical Characteristics
Table 1. Table of Graphs
FIGURE(1)
1, 2, 3, 4
5, 6
7, 8, 9, 10(2)
11(2)
Distribution
VIO
Input offset voltage
vs Common-mode voltage
Distribution
αVIO
Input offset voltage temperature coefficient
Input bias and input offset current
IIB /IIO
vs Free-air temperature
vs Supply voltage
12
13(2)
14(2)
15, 16(2)
17(2)
VI
Input voltage
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Output current
VOH
High-level output voltage
VOL
Low-level output voltage
VOM+
VOM-
VO(PP)
Maximum positive peak output voltage
Maximum negative peak output voltage
Maximum peak-to-peak output voltage
vs Output current
18(2)
vs Frequency
19
vs Supply voltage
20
21(2)
IOS
VO
Short-circuit output current
vs Free-air temperature
vs Differential input voltage
vs Load resistance
vs Frequency
Output voltage
22, 23
24
Large-signal differential voltage amplification
Large-signal differential voltage amplification and phase margin
Large-signal differential voltage amplification
Output impedance
AVD
25, 26
27(2), 28(2)
29, 30
31
vs Free-air temperature
vs Frequency
z0
vs Frequency
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
Supply current
vs Free-air temperature
vs Frequency
32
33, 34
35(2)
36(2), 37(2)
38(2), 39(2)
40
kSVR
vs Free-air temperature
vs Supply voltage
IDD
vs Free-air temperature
vs Load Capacitance
vs Free-air temperature
SR
Slew rate
41(2)
Inverting large-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Voltage-follower small-signal pulse response
Equivalent input noise voltage
42, 43
44, 45
46, 47
48, 49
50, 51
52
VO
Vn
vs Frequency
Noise voltage over a 10-second period
Integrated noise voltage
vs Frequency
53
THD+N
Total harmonic distortion + noise
vs Frequency
54
vs Supply voltage
vs Free-air temperature
vs Load capacitance
vs Load capacitance
55
56(2)
Gain-bandwidth product
φm
Phase margin
Gain margin
57
58
(1) For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.
(2) Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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20
20
15
10
891 Amplifiers From
2 Wafer Lots
891 Amplifiers From
2 Wafer Lots
V
DD
=
2.5 V
V
=
5 V
= 25°C
DD
T
A
= 25°C
T
A
15
10
5
0
5
0
−1.6 −1.2 −0.8 −0.4
0
0.4
0.8
1.2
1.6
−1.6 −1.2 −0.8 −0.4
0
0.4
0.8
1.2
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 1. Distribution of TLC2272 Input Offset Voltage
Figure 2. Distribution of TLC2272 Input Offset Voltage
20
20
992 Amplifiers From
2 Wafer Lots
992 Amplifiers From
2 Wafer Lots
V
DD
= 5 V
V
DD
= 2.5 V
15
10
15
10
5
0
5
0
−1.6 −1.2 −0.8 −0.4
0
0.4
0.8
1.2
1.6
−1.6 −1.2 −0.8 −0.4
0
0.4
0.8
1.2
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 3. Distribution of TLC2274 Input Offset Voltage
Figure 4. Distribution of TLC2274 Input Offset Voltage
1
1
V
T
= 5 V
V
= 5 V
DD
= 25°C
= 50 Ω
S
DD
= 25°C
T
A
R
A
R
= 50 Ω
S
0.5
0.5
0
0
−0.5
−1
−0.5
−1
−1
0
1
2
3
4
5
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
V
IC
− Common-Mode Voltage − V
V
IC
− Common-Mode Voltage − V
Figure 5. Input Offset Voltage vs Common-Mode Voltage
Figure 6. Input Offset Voltage vs Common-Mode Voltage
14
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
25
20
15
10
5
25
128 Amplifiers From
128 Amplifiers From
2 Wafer Lots
2 Wafer Lots
V
= 5 V
V
= 2.5 V
DD
P Package
DD
P Package
20
15
10
5
25°C to 125°C
25°C to 125°C
0
0
−1
0
1
2
3
4
5
−1
0
1
2
3
4
5
−5 −4 −3 −2
−5 −4 −3 −2
αV − Temperature Coefficient − µV/°C
IO
αV − Temperature Coefficient − µV/°C
IO
Figure 7. Distribution of TLC2272 vs
Figure 8. Distribution of TLC2272 vs
Input Offset Voltage Temperature Coefficient
Input Offset Voltage Temperature Coefficient
25
25
128 Amplifiers From
2 Wafer Lots
128 Amplifiers From
2 Wafer Lots
V
=
2.5 V
N Package
= 25°C to 125°C
V
=
2.5 V
N Package
T = 25°C to 125°C
A
DD
DD
20
15
10
5
20
15
10
5
T
A
0
0
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
α
− Temperature Coefficient − µV/°C
α
− Temperature Coefficient − µV/°C
VIO
VIO
Figure 9. Distribution of TLC2274 vs
Figure 10. Distribution of TLC2274 vs
Input Offset Voltage Temperature Coefficient
Input Offset Voltage Temperature Coefficient
12
35
T
= 25°C
= 50 Ω
A
10
8
V
V
V
= 2.5 V
R
DD
S
= 0 V
IC
O
30
25
20
15
10
5
= 0 V
R
= 50 Ω
S
6
4
2
I
IB
|V | ≤ 5mV
IO
0
− 2
− 4
I
IO
− 6
− 8
− 10
0
2
3
4
5
6
7
8
25
45
65
85
105
125
|V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 12. Input Voltage vs Supply Voltage
Figure 11. Input Bias and Input Offset Current vs
Free-Air Temperature
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
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5
6
5
4
3
V
DD
= 5 V
V
DD
= 5 V
4
3
T
A
= 125°C
|V | ≤ 5mV
IO
2
T
A
= 25°C
1
2
T
A
= −55°C
0
1
0
−1
−75 − 50 − 25
0
25
50
75
100 125
0
1
2
3
4
T
A
− Free-Air Temperature − °C
I
− High-Level Output Current − mA
OH
Figure 13. Input Voltage vs Free-Air Temperature
Figure 14. High-Level Output Voltage vs
High-Level Output Current
1.4
1.2
1
1.2
V
= 5 V
DD
= 2.5 V
V
T
= 5 V
DD
= 25°C
V
IC
A
1
0.8
0.6
0.4
0.2
0
V
IC
= 0 V
T
A
= 125°C
= 25°C
V
IC
= 1.25 V
0.8
0.6
0.4
0.2
0
T
A
T
= −55°C
A
V
IC
= 2.5 V
0
1
2
3
4
5
0
1
2
3
4
5
6
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 15. Low-Level Output Voltage vs
Low-Level Output Current
Figure 16. Low-Level Output Voltage vs
Low-Level Output Current
5
−3.8
V
DD
=
5 V
V
V
=
5 V
DD
IC
= 0 V
−4
T
A
= 125°C
4
−4.2
−4.4
−4.6
T
= −55°C
= 25°C
A
T
= 25°C
A
T
A
3
2
T
A
= −55°C
T
A
= 125°C
−4.8
−5
1
0
1
2
3
4
5
6
0
1
2
3
4
5
I
O
− Output Current − mA
|I | − Output Current − mA
O
Figure 18. Maximum Positive Peak Output Voltage vs
Output Current
Figure 17. Maximum Positive Peak Output Voltage vs
Output Current
16
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
10
9
8
7
6
5
4
3
2
1
0
16
R
T
= 10 kΩ
= 25°C
L
V
= −100 mV
ID
A
12
8
V
DD
= 5 V
4
V
DD
= 5 V
0
V
= 100 mV
ID
−4
−8
V
T
= 0 V
O
= 25°C
A
2
3
4
5
6
7
8
10 k
100 k
1 M
10 M
f − Frequency − Hz
|V
DD
| − Supply Voltage − V
Figure 19. Maximum Peak-to-Peak Output Voltage vs
Figure 20. Short-Circuit Output Current vs Supply Voltage
Frequency
5
15
V
V
= 0 V
= 5 V
V
T
= 5 V
O
DD
DD
= 25°C
= 10 kΩ
= 2.5 V
A
V
ID
= −100 mV
R
V
L
11
7
4
3
2
1
IC
−3
−1
−5
V
ID
= 100 mV
0
−800
800
− Differential Input Voltage − µV
1200
−400
0
400
−75 −50 −25
0
25
50
75 100 125
V
ID
T
A
− Free-Air Temperature − °C
Figure 22. Output Voltage vs Differential Input Voltage
Figure 21. Short-Circuit Output Current vs
Free-Air Temperature
5
1000
V
T
= 5 V
DD
V
T
= 1 V
= 25°C
= 10 kΩ
= 0 V
O
A
= 25°C
R
V
A
L
3
1
IC
100
10
1
V
DD
= 5 V
V
DD
= 5 V
−1
−3
−5
0.1
0.1
1
10
100
0
− Differential Input Voltage − µV
250 500 750 1000
−1000 −750 −500 −250
V
R
L
− Load Resistance − kΩ
ID
Figure 24. Large-Signal Differential Voltage Amplification vs
Load Resistance
Figure 23. Output Voltage vs Differential Input Voltage
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
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180°
80
60
40
20
80
180°
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
V
= 5 V
DD
DD
R
C
T
R
C
T
= 10 kΩ
= 100 pF
= 25°C
L
L
L
L
135°
90°
45°
0°
135°
90°
45°
0°
60
40
A
A
20
0
0
−20
−40
−20
−45°
−90°
−45°
−90°
−40
1 k
10 k
100 k
1 M
10 M
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 26. Large-Signal Differential Voltage Amplification
and Phase Margin vs Frequency
Figure 25. Large-Signal Differential Voltage Amplification
and Phase Margin vs Frequency
1 k
1 k
V
V
V
=
5 V
V
V
V
= 5 V
DD
DD
= 0 V
= 2.5 V
IC
O
IC
O
=
4 V
= 1 V to 4 V
R
= 1 MΩ
L
R
= 1 MΩ
L
100
100
R
= 10 kΩ
L
R
= 10 kΩ
L
10
10
−75 −50 −25
−75 −50 −25
0
25
50
75 100 125
0
25
T − Free-Air Temperature − °C
A
50
75 100 125
T
A
− Free-Air Temperature − °C
Figure 27. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
Figure 28. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
1000
1000
V
T
= 5 V
V
T
= 5 V
DD
DD
= 25°C
= 25°C
A
A
100
10
100
10
A
V
= 100
A
V
= 100
A
= 10
= 1
V
A
= 10
= 1
V
1
1
A
V
A
V
0.1
0.1
100
1 k
10 k
100 k
1 M
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
f − Frequency − Hz
Figure 29. Output Impedance vs Frequency
Figure 30. Output Impedance vs Frequency
18
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
90
100
80
60
40
20
0
T
A
= 25°C
V
= 5 V
DD
86
82
V
= 5 V
DD
V
DD
= 5 V
V
IC
= −5 V to 2.7 V
78
74
70
V
DD
= 5 V
V
IC
= 0 V to 2.7 V
10
100
1 k
10 k
100 k
1 M
10 M
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 31. Common-Mode Rejection Ratio vs Frequency
Figure 32. Common-Mode Rejection Ratio vs
Free-Air Temperature
100
100
V
T
= 5 V
V
= 5 V
DD
= 25°C
DD
= 25°C
T
A
A
80
60
40
20
0
80
60
40
20
0
k
k
SVR+
SVR+
k
SVR−
k
SVR−
−20
−20
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
f − Frequency − Hz
Figure 33. Supply-Voltage Rejection Ratio vs Frequency
Figure 34. Supply-Voltage Rejection Ratio vs Frequency
110
3
V
V
=
2.2 V to 8 V
V
= 0 V
DD
= 0 V
O
No Load
O
105
100
95
2.4
1.8
1.2
0.6
0
T
= 25°C
A
T
A
= −55°C
T
A
= 125°C
90
85
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75 100 125
|V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 36. TLC2272 Supply Current vs Supply Voltage
Figure 35. Supply-Voltage Rejection Ratio vs
Free-Air Temperature
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
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6
3
2.4
1.8
1.2
0.6
0
V
= 0 V
O
No Load
V
V
=
5 V
DD
= 0 V
O
4.8
3.6
2.4
1.2
0
V
V
= 5 V
DD
= 2.5 V
O
T
= 25°C
A
T
A
= −55°C
T
A
= 125°C
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75 100 125
|V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 37. TLC2274 Supply Current vs Supply Voltage
Figure 38. TLC2272 Supply Current vs Free-Air Temperature
6
5
V
= 5 V
DD
= −1
V
V
=
5 V
DD
A
V
T
A
= 0 V
O
= 25°C
4
3
2
1
0
4.8
3.6
2.4
V
V
= 5 V
DD
= 2.5 V
SR −
O
SR +
1.2
0
−75 −50 −25
0
25
50
75 100 125
10
100
1 k
10 k
C
− Load Capacitance − pF
T
A
− Free-Air Temperature − °C
L
Figure 40. Slew Rate vs Load Capacitance
Figure 39. TLC2274 Supply Current vs Free-Air Temperature
5
5
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
= −1
DD
R
C
T
L
L
SR −
4
4
3
2
A
A
V
SR +
3
2
V
= 5 V
= 10 kΩ
= 100 pF
= 1
DD
1
1
0
R
C
A
L
L
V
0
−75 −50 −25
0
25
50
75 100 125
0
1
2
3
4
5
6
7
8
9
T
A
− Free-Air Temperature − °C
t − Time − µs
Figure 41. Slew Rate vs Free-Air Temperature
Figure 42. Inverting Large-Signal Pulse Response
20
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
5
5
4
V
= 5 V
DD
V
= 5 V
= 10 kΩ
= 100 pF
= 1
DD
R
C
T
= 10 kΩ
= 100 pF
= 25°C
= −1
L
L
R
C
A
L
L
3
4
3
2
1
0
A
V
A
V
T
A
= 25°C
2
1
0
− 1
− 2
− 3
− 4
− 5
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
t − Time − µs
t − Time − µs
Figure 43. Inverting Large-Signal Pulse Response
Figure 44. Voltage-Follower Large-Signal Pulse Response
5
2.65
V
DD
= 5 V
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
= −1
DD
R
C
T
= 10 kΩ
= 100 pF
= 25°C
= 1
4
3
L
L
R
C
T
L
L
2.6
2.55
2.5
A
A
A
V
A
V
2
1
0
−1
−2
−3
−4
2.45
2.4
−5
0
1
2
3
4
5
6
7
8
9
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5 5.5
t − Time − µs
t − Time − µs
Figure 45. Voltage-Follower Large-Signal Pulse Response
Figure 46. Inverting Small-Signal Pulse Response
100
2.65
V
DD
= 5 V
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
= 1
DD
R
C
T
= 10 kΩ
= 100 pF
= 25°C
= 1
R
C
T
L
L
L
L
2.6
2.55
2.5
A
A
A
V
50
A
V
0
−50
2.45
2.4
−100
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
t − Time − µs
t − Time − µs
Figure 47. Inverting Small-Signal Pulse Response
Figure 48. Voltage-Follower Small-Signal Pulse Response
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100
60
V
DD
= 5 V
V = 5 V
DD
R
C
T
= 10 kΩ
= 100 pF
= 25°C
= 1
L
L
T
= 25°C
A
R
= 20 Ω
S
A
A
V
50
0
40
30
20
10
0
−50
−100
10
100
1 k
10 k
0
0.5
1
1.5
f − Frequency − Hz
t − Time − µs
Figure 49. Voltage-Follower Small-Signal Pulse Response
Figure 50. Equivalent Input Noise Voltage vs Frequency
60
1000
V
= 5 V
DD
f = 0.1 Hz to 10 Hz
V
T
= 5 V
DD
= 25°C
750
500
250
0
A
T
A
= 25°C
R
= 20 Ω
S
40
30
20
10
0
−250
−500
−750
−1000
10
100
1 k
10 k
0
2
4
6
8
10
f − Frequency − Hz
t − Time − s
Figure 51. Equivalent Input Noise Voltage vs Frequency
Figure 52. Noise Voltage Over a 10 Second Period
100
1
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
V
T
= 5 V
DD
= 25°C
A
R
= 10 kΩ
L
T
= 25°C
A
0.1
0.01
10
A
V
= 100
A
= 10
= 1
V
1
A
V
0.001
0.1
0.0001
1
10
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f − Frequency − Hz
f − Frequency − Hz
Figure 53. Integrated Noise Voltage vs Frequency
Figure 54. Total Harmonic Distortion + Noise vs Frequency
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
2.5
2.4
2.3
2.2
2.1
2
3
V
= 5 V
f = 10 kHz
DD
f = 10 kHz
R
C
T
= 10 kΩ
= 100 pF
= 25°C
L
L
2.8
2.6
2.4
2.2
2
R
C
= 10 kΩ
L
L
= 100 pF
A
1.8
1.6
1.4
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
|V
DD
| − Supply Voltage − V
Figure 56. Gain-Bandwidth Product vs Free-Air Temperature
Figure 55. Gain-Bandwidth Product vs Supply Voltage
75°
15
V
T
=
5 V
V
= 5 V
DD
DD
= 1
= 25°C
A
V
A
R
= 100 Ω
= 50 Ω
null
R
T
= 10 kΩ
= 25°C
L
60°
12
9
A
R
null
45°
30°
R
= 20 Ω
null
6
10 kΩ
V
3
15°
0°
DD +
10 kΩ
R
null
R
= 0
null
V
I
C
L
R
= 10 Ω
null
V
DD −
0
10
100
1000
10000
10
100
C − Load Capacitance − pF
L
1000
10000
C
− Load Capacitance − pF
L
Figure 57. Phase Margin vs Load Capacitance
Figure 58. Gain Margin vs Load Capacitance
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
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7 Detailed Description
7.1 Overview
The TLC227x and TLC227xA families of devices are rail-to-rail output operational amplifiers. These devices
operate from 4.4-V to 16-V single supply and ±2.2-V ±8-V dual supply, are unity-gain stable, and are suitable for
a wide range of general-purpose applications.
7.2 Functional Block Diagram
V
DD+
Q3
Q6
Q9
Q12
Q14
Q16
IN+
IN−
OUT
C1
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
R3
Q5
R4
Q7
Q8
Q10
Q11
R1
R2
V
DD−
Table 2. Device Component Count(1)
Component
TLC2272
TLC2274
Transistors
Resistors
Diodes
38
26
9
76
52
18
6
Capacitors
3
(1) Includes both amplifiers and all ESD, bias, and trim circuitry.
7.3 Feature Description
The TLC227x and TLC227xA family of devices feature 2-MHz bandwidth and voltage noise of 9 nV/√Hz with
performance rated from 4.4 V to 16 V across an automotive temperature range (–40°C to 125°C). LinMOS suits
a wide range of audio, automotive, industrial, and instrumentation applications.
7.4 Device Functional Modes
The TLC227x and TLC227xA families of devices is powered on when the supply is connected. The devices may
operate with single or dual supply, depending on the application. The devices are in its full performance once the
supply is above the recommended value.
24
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
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SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Macromodel Information
Macromodel information provided was derived using MicroSim Parts™, the model generation software used with
(1)
MicroSim PSpice™. The Boyle macromodel
and subcircuit in Figure 59 were generated using the TLC227x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
•
•
•
•
•
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
99
DIN
3
EGND
+
−
V
CC+
92
9
FB
+
91
90
RSS
ISS
RO2
+
−
+
−
VB
DIP
RP
2
VIP
VIN
HLIM
−
+
−
10
−
+
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
DE
VAD
5
−
54
V
CC−
−
+
4
VE
OUT
.SUBCKT TLC227x 1 2 3 4 5
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC 3 53 DC .78
VE
VLIM
VLP
VLN
60
60
8
7
3
10
60
9
112.653E3
122.653E3
550
C1
C2
11
6
1214E−12
760.00E−12
53DX
5DX
91DX
90DX
3DX
0POLY (2) (3,0) (4,) 0 .5 .5
0POLY (5) VB VC VE VLP VLN 0
DC
DE
DLP
DLN
DP
5
9950
54
90
92
4
44.310E3
99925.9E3
4−.5
0DC 0
EGND
FB
99
99
54
7
91
0
4DC .78
8DC 0
0DC 1.9
92DC 9.4
+ 984.9E3 −1E6 1E6 1E6 −1E6
GA 011 12 377.0E−6
GCM 0 6 10 99 134E−9
6
ISS
HLIM
J1
J2
R2
3
10DC 216.OE−6
0VLIM 1K
210 JX
110 JX
9100.OE3
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=1.500E−12BETA=1.316E-3
+ VTO=−.270)
.ENDS
90
11
12
6
Figure 59. Boyle Macromodel and Subcircuit
(1) Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974).
Copyright © 1997–2016, Texas Instruments Incorporated
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TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
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8.2 Typical Application
8.2.1 High-Side Current Monitor
VBAT
ILOUD
V1
V2
RS
0.1 µF
R1
R
ILOAD
VOUT
+
_
R2
47 kΩ
Rg
Figure 60. Equivalent Schematic (Each Amplifier)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
PARAMETER
VALUE
VBAT
Battery Voltage
Sense Resistor
Load Current
12 V
RSENSE
ILOAD
0.1 Ω
0 A to 10 A
Operational Amplifier
Set in Differential configuration with Gain = 10
8.2.1.2 Detailed Design Procedure
This circuit is designed for measuring the high-side current in automotive body control modules with 12-V battery
or similar applications. The operational amplifier is set as differential with an external resistor network.
8.2.1.2.1 Differential Amplifier Equations
Equation 1 and Equation 2 are used to calculate VOUT
.
æ
ö
÷
÷
÷
÷
æ
ö
÷
÷
ø
R1
1
R
R1
R
ç
1+
+
2 R2 Rg
ç
-
ç
Rg ç Rg R2
V1 + V2
è
VOUT
=
´
+
(V - V )
1 2
ç
R1
R2
R1
R
2
ç
1+
1+
ç
÷
R2
ç
÷
è
ø
(1)
(2)
æ
ç
ö
÷
÷
÷
÷
æ
ö
÷
÷
ø
R1
1
R
R1
R
1+
+
2 R2 Rg
ç
-
ç
Rg ç Rg R2
è
VOUT
=
´ VBAT
+
´RS ´ILoad
ç
R1
R2
R1
R
ç
1+
1+
ç
÷
R2
ç
÷
è
ø
In an ideal case R1 = R and R2 = Rg, and VOUT can then be calculated using Equation 3:
Rg
VOUT
=
´RS ´ILoad
R
(3)
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TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
www.ti.com
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
However, as the resistors have tolerances, they cannot be perfectly matched.
R1 = R ± ΔR1
R2 = R2 ± ΔR2
R = R ± ΔR
Rg = Rg ± ΔRg
DR
Tol =
R
(4)
By developing the equations and neglecting the second order, the worst case is when the tolerances add up.
This is shown by Equation 5.
æ
ö
÷
÷
ø
æ
ö
÷
÷
ø
Rg
Rg
R
2R
ç
VOUT = ± (4 Tol)
´ VBAT + 1± 2 Tolç1+
´RS ´ILOAD
ç
ç
R + Rg
R + Rg
è
è
where
•
•
Tol = 0.01 for 1%
Tol = 0.001 for 0.1%
(5)
(6)
If the resistors are perfectly matched, then Tol = 0 and VOUT is calculated using Equation 6.
Rg
VOUT
=
´RS ´ILOAD
R
The highest error is from the Common mode, as shown in Equation 7.
Rg
4 (Tol)
´ VBAT
R + Rg
(7)
Gain of 10, Rg / R = 10, and Tol = 1%:
Common mode error = ((4 × 0.01) / 1.1) × 12 V = 0.436 V
Gain of 10 and Tol = 0.1%:
Common mode error = 43.6 mV
The resistors were chosen from 2% batches.
R1 and R 12 kΩ
R2 and Rg 120 kΩ
Ideal Gain = 120 / 12 = 10
The measured value of the resistors:
R1 = 11.835 kΩ
R = 11.85 kΩ
R2 = 117.92 kΩ
Rg = 118.07 kΩ
Copyright © 1997–2016, Texas Instruments Incorporated
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TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
www.ti.com
8.2.1.3 Application Curves
1.2
1
12
10
8
0.8
0.6
0.4
0.2
6
4
2
Measured
Measured
Ideal
Ideal
0
0
0
0.2
0.4
0.6
0.8
1
1.2
0
2
4
6
8
10
12
Load Current (A)
Load Current (A)
D001
D001
Figure 61. Output Voltage Measured vs Ideal
(0 to 1 A)
Figure 62. Output Voltage Measured vs Ideal
(0 to 10 A)
9 Power Supply Recommendations
Supply voltage for a single supply is from 4.4 V to 16 V, and from ±2.2 V to ±8 V for dual supply. In the high-side
sensing application, the supply is connected to a 12-V battery.
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TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
www.ti.com
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
10 Layout
10.1 Layout Guidelines
The TLC227x and TLC227xA families of devices are wideband amplifiers. To realize the full operational
performance of the devices, good high-frequency printed-circuit-board (PCB) layout practices are required. Low-
loss 0.1-μF bypass capacitors must be connected between each supply pin and ground as close to the device as
possible. The bypass capacitor traces should be designed for minimum inductance.
10.2 Layout Example
Figure 63. Layout Example
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TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H –FEBRUARY 1997–REVISED MARCH 2016
www.ti.com
11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER SAMPLE & BUY
TLC2272
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
TLC2272A
TLC2272M
TLC2272AM
TLC2274
TLC2274A
TLC2274M
TLC2274AM
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
MicroSim Parts, PSpice are trademarks of MicroSim.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC2272ACD
TLC2272ACDG4
TLC2272ACDR
TLC2272ACDRG4
TLC2272ACP
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2272AC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
2272AC
2272AC
2272AC
TLC2272AC
P2272A
P2272A
2272AI
D
2500
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Green (RoHS
& no Sb/Br)
TLC2272ACPW
TLC2272ACPWR
TLC2272AID
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PW
PW
D
150
2000
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLC2272AIDG4
TLC2272AIDR
TLC2272AIDRG4
TLC2272AIP
D
75
Green (RoHS
& no Sb/Br)
2272AI
D
2500
2500
50
Green (RoHS
& no Sb/Br)
2272AI
D
Green (RoHS
& no Sb/Br)
2272AI
P
Green (RoHS
& no Sb/Br)
TLC2272AI
2272AM
2272AM
2272AM
2272AM
TLC2272AMD
SOIC
SOIC
SOIC
SOIC
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
TLC2272AMDG4
TLC2272AMDR
TLC2272AMDRG4
D
75
Green (RoHS
& no Sb/Br)
D
2500
2500
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC2272AQD
TLC2272AQDG4
TLC2272AQDR
TLC2272AQDRG4
TLC2272CD
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 125
C2272A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
C2272A
C2272A
C2272A
2272C
D
2500
2500
75
Green (RoHS
& no Sb/Br)
-40 to 125
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TLC2272CDG4
TLC2272CDR
TLC2272CDRG4
TLC2272CP
D
75
Green (RoHS
& no Sb/Br)
2272C
D
2500
2500
50
Green (RoHS
& no Sb/Br)
2272C
D
Green (RoHS
& no Sb/Br)
2272C
P
Green (RoHS
& no Sb/Br)
TLC2272CP
P2272
TLC2272CPS
TLC2272CPSR
TLC2272CPW
TLC2272CPWR
TLC2272ID
PS
PS
PW
PW
D
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SO
2000
150
2000
75
Green (RoHS
& no Sb/Br)
P2272
TSSOP
TSSOP
SOIC
SOIC
PDIP
TSSOP
Green (RoHS
& no Sb/Br)
P2272
Green (RoHS
& no Sb/Br)
P2272
Green (RoHS
& no Sb/Br)
2272I
TLC2272IDR
D
2500
50
Green (RoHS
& no Sb/Br)
2272I
TLC2272IP
P
Green (RoHS
& no Sb/Br)
TLC2272IP
Y2272
TLC2272IPW
PW
150
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2000
2000
75
(1)
(2)
(3)
(4/5)
(6)
TLC2272IPWR
TLC2272IPWRG4
TLC2272MD
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
D
8
8
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Y2272
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Y2272
8
Green (RoHS
& no Sb/Br)
-55 to 125
-55 to 125
2272M
TLC2272MDG4
TLC2272MDR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
2272M
SOIC
D
8
2500
2500
75
Green (RoHS
& no Sb/Br)
2272M
TLC2272MDRG4
TLC2272QDG4
TLC2272QDR
SOIC
D
8
Green (RoHS
& no Sb/Br)
2272M
SOIC
D
8
Green (RoHS
& no Sb/Br)
C2272Q
C2272Q
T2272Q
2274AC
2274AC
2274AC
2274AC
TLC2274ACN
P2274A
P2274A
P2274A
SOIC
D
8
2500
2000
50
Green (RoHS
& no Sb/Br)
-40 to 125
TLC2272QPWRG4
TLC2274ACD
TSSOP
SOIC
PW
D
8
Green (RoHS
& no Sb/Br)
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TLC2274ACDG4
TLC2274ACDR
TLC2274ACDRG4
TLC2274ACN
SOIC
D
50
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
PDIP
N
Green (RoHS
& no Sb/Br)
TLC2274ACPW
TLC2274ACPWR
TLC2274ACPWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC2274AID
TLC2274AIDR
TLC2274AIN
ACTIVE
SOIC
SOIC
PDIP
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-55 to 125
2274AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2500
25
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
2274AI
N
Green (RoHS
& no Sb/Br)
TLC2274AIN
Y2274A
TLC2274AIPW
TLC2274AIPWR
TLC2274AIPWRG4
TLC2274AMD
TLC2274AMDG4
TLC2274AMDRG4
TLC2274AQD
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PW
PW
PW
D
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2000
2000
50
Green (RoHS
& no Sb/Br)
Y2274A
Green (RoHS
& no Sb/Br)
Y2274A
Green (RoHS
& no Sb/Br)
2274AM
D
50
Green (RoHS
& no Sb/Br)
2274AM
D
2500
50
Green (RoHS
& no Sb/Br)
2274AM
D
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
TLC2274A
PJ2274A
TLC2274A
PJ2274A
TLC2274C
TLC2274C
TLC2274C
TLC2274CN
TLC2274AQDG4
TLC2274AQDR
TLC2274AQDRG4
TLC2274CD
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
TLC2274CDG4
TLC2274CDR
D
50
Green (RoHS
& no Sb/Br)
D
2500
25
Green (RoHS
& no Sb/Br)
TLC2274CN
N
Green (RoHS
& no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC2274CNE4
TLC2274CNS
TLC2274CNSR
TLC2274CPW
TLC2274CPWR
TLC2274ID
ACTIVE
PDIP
SO
N
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
25
Green (RoHS
& no Sb/Br)
NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC2274CN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NS
NS
PW
PW
D
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TLC2274
TLC2274
P2274
SO
2000
90
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
2000
50
Green (RoHS
& no Sb/Br)
P2274
Green (RoHS
& no Sb/Br)
TLC2274I
TLC2274I
TLC2274I
TLC2274I
TLC2274IN
Y2274
TLC2274IDG4
TLC2274IDR
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
25
Green (RoHS
& no Sb/Br)
TLC2274IDRG4
TLC2274IN
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TLC2274IPW
TLC2274IPWR
TLC2274IPWRG4
TLC2274MD
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PW
PW
PW
D
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2000
2000
50
Green (RoHS
& no Sb/Br)
Y2274
Green (RoHS
& no Sb/Br)
Y2274
Green (RoHS
& no Sb/Br)
-55 to 125
-55 to 125
TLC2274M
PJ2274M
TLC2274M
PJ2274M
TLC2274MDG4
TLC2274MDR
TLC2274MDRG4
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC2274MN
TLC2274QD
ACTIVE
PDIP
SOIC
SOIC
SOIC
N
D
D
D
14
14
14
14
25
Pb-Free
(RoHS)
NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-40 to 125
TLC2274MN
ACTIVE
ACTIVE
ACTIVE
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
TLC2274
TLC2274
TLC2274
TLC2274QDG4
TLC2274QDRG4
50
Green (RoHS
& no Sb/Br)
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2272, TLC2272A, TLC2272AM, TLC2272M, TLC2274, TLC2274A, TLC2274AM, TLC2274M :
Catalog: TLC2272A, TLC2272, TLC2274A, TLC2274
•
Automotive: TLC2272-Q1, TLC2272A-Q1, TLC2272A-Q1, TLC2272-Q1, TLC2274-Q1, TLC2274A-Q1, TLC2274A-Q1, TLC2274-Q1
•
Enhanced Product: TLC2272A-EP, TLC2272A-EP, TLC2274-EP, TLC2274A-EP, TLC2274A-EP, TLC2274-EP
•
Military: TLC2272M, TLC2272AM, TLC2274M, TLC2274AM
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC2272ACDR
TLC2272ACPWR
TLC2272AIDR
TLC2272AMDR
TLC2272AMDRG4
TLC2272AQDR
TLC2272CDR
SOIC
TSSOP
SOIC
D
PW
D
8
8
2500
2000
2500
2500
2500
2500
2500
2000
2500
2000
2500
2500
2000
2500
2000
2500
2000
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.5
12.4
12.4
12.4
12.4
12.4
12.5
12.4
16.4
12.4
16.4
12.4
16.4
6.4
7.0
6.4
6.4
6.4
6.4
6.4
7.0
6.4
7.0
6.4
6.4
7.0
6.5
6.9
6.5
6.9
6.5
5.2
3.6
5.2
5.2
5.2
5.2
5.2
3.6
5.2
3.6
5.2
5.2
3.6
9.0
5.6
9.0
5.6
9.0
2.1
1.6
2.1
2.1
2.1
2.1
2.1
1.6
2.1
1.6
2.1
2.1
1.6
2.1
1.6
2.1
1.6
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
8
SOIC
D
8
SOIC
D
8
SOIC
D
8
SOIC
D
8
TLC2272CPWR
TLC2272IDR
TSSOP
SOIC
PW
D
8
8
TLC2272IPWR
TLC2272MDR
TSSOP
SOIC
PW
D
8
8
TLC2272QDR
SOIC
D
8
TLC2272QPWRG4
TLC2274ACDR
TLC2274ACPWR
TLC2274AIDR
TLC2274AIPWR
TLC2274AQDR
TSSOP
SOIC
PW
D
8
14
14
14
14
14
TSSOP
SOIC
PW
D
TSSOP
SOIC
PW
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC2274CDR
TLC2274CNSR
TLC2274CPWR
TLC2274IDR
SOIC
SO
D
NS
PW
D
14
14
14
14
14
14
14
14
2500
2000
2000
2500
2000
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
12.4
16.4
12.4
16.4
16.4
16.4
6.5
8.2
6.9
6.5
6.9
6.5
6.5
6.5
9.0
10.5
5.6
9.0
5.6
9.0
9.0
9.0
2.1
2.5
1.6
2.1
1.6
2.1
2.1
2.1
8.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
12.0
16.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
TSSOP
SOIC
TSSOP
SOIC
SOIC
SOIC
TLC2274IPWR
TLC2274MDR
TLC2274MDRG4
TLC2274QDRG4
PW
D
D
D
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC2272ACDR
TLC2272ACPWR
TLC2272AIDR
TLC2272AMDR
TLC2272AMDRG4
TLC2272AQDR
TLC2272CDR
SOIC
TSSOP
SOIC
D
PW
D
8
8
8
8
8
8
8
8
8
2500
2000
2500
2500
2500
2500
2500
2000
2500
340.5
367.0
340.5
350.0
350.0
340.5
340.5
367.0
340.5
338.1
367.0
338.1
350.0
350.0
338.1
338.1
367.0
338.1
20.6
35.0
20.6
43.0
43.0
20.6
20.6
35.0
20.6
SOIC
D
SOIC
D
SOIC
D
SOIC
D
TLC2272CPWR
TLC2272IDR
TSSOP
SOIC
PW
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-May-2019
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC2272IPWR
TLC2272MDR
TLC2272QDR
TSSOP
SOIC
PW
D
8
2000
2500
2500
2000
2500
2000
2500
2000
2500
2500
2000
2000
2500
2000
2500
2500
2500
367.0
350.0
340.5
367.0
333.2
367.0
333.2
367.0
350.0
333.2
367.0
367.0
333.2
367.0
350.0
350.0
350.0
367.0
350.0
338.1
367.0
345.9
367.0
345.9
367.0
350.0
345.9
367.0
367.0
345.9
367.0
350.0
350.0
350.0
35.0
43.0
20.6
35.0
28.6
35.0
28.6
35.0
43.0
28.6
38.0
35.0
28.6
35.0
43.0
43.0
43.0
8
SOIC
D
8
TLC2272QPWRG4
TLC2274ACDR
TLC2274ACPWR
TLC2274AIDR
TLC2274AIPWR
TLC2274AQDR
TLC2274CDR
TSSOP
SOIC
PW
D
8
14
14
14
14
14
14
14
14
14
14
14
14
14
TSSOP
SOIC
PW
D
TSSOP
SOIC
PW
D
SOIC
D
TLC2274CNSR
TLC2274CPWR
TLC2274IDR
SO
NS
PW
D
TSSOP
SOIC
TLC2274IPWR
TLC2274MDR
TLC2274MDRG4
TLC2274QDRG4
TSSOP
SOIC
PW
D
SOIC
D
SOIC
D
Pack Materials-Page 3
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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