TLC2274EPWRQ1 [TI]
TLC2274-HT Advanced LinCMOS Rail-to-Rail Operational Amplifier;
| 型号： | TLC2274EPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLC2274-HT Advanced LinCMOS Rail-to-Rail Operational Amplifier 放大器 光电二极管 |
| 文件： | 总29页 (文件大小：1159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC2274-HT
SGLS416 –JANUARY 2015
TLC2274-HT Advanced LinCMOS™ Rail-to-Rail Operational Amplifier
1 Features
3 Description
The TLC2274 is a quadruple operational amplifier
from Texas Instruments. The device exhibits rail-to-
rail output performance for increased dynamic range
in single- or split-supply applications. The TLC2274
offers 2 MHz of bandwidth and 3 V/μs of slew rate for
higher speed applications. These device offers
comparable ac performance while having better
noise, input offset voltage, and power dissipation than
existing CMOS operational amplifiers. The TLC2274
has a noise voltage of 9nV/√Hz, two times lower than
competitive solutions.
1
•
Qualified for Automotive Applications
Qualified in Accordance With AEC-Q100
Output Swing Includes Both Supply Rails
Low Noise: 9 nV/√Hz Typ at ƒ = 1 kHz
Low Input Bias Current: 1 pA Typical
•
•
•
•
•
Fully Specified for Both Single-Supply and Split-
Supply Operation
•
Common-Mode Input Voltage Range Includes
Negative Rail
•
•
•
High-Gain Bandwidth: 2.2 MHz Typical
The TLC2274, exhibiting high input impedance and
low noise, is excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric
transducers. Because of the micropower dissipation
levels, this device works well in hand-held monitoring
and remote-sensing applications. In addition, the rail-
to-rail output feature, with single- or split-supplies,
makes this device a great choice when interfacing
with analog-to-digital converters (ADCs). This family
is fully characterized at 5 V and ±5 V.
High Slew Rate: 3.6 V/μs Typical
Low Input Offset Voltage 2500-μV Max at TA =
25°C
•
Macromodel Included
2 Applications
•
Supports Extreme Temperature Applications:
–
–
–
–
Controlled Baseline
It offers increased output dynamic range, lower noise
voltage, and lower input offset voltage. This
enhanced feature set allows the device to be used in
a wider range of applications.
One Assembly and Test Site
One Fabrication Site
Available in Extreme (–40°C to 150°C)
Temperature Range
(1)
Device Information(1)
–
–
–
–
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLC2274-HT
TSSOP (14)
6.60 mm × 5.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Texas Instruments' high temperature products
use highly-optimized silicon (die) solutions with
design and process enhancements to
Maximum Peak-to-Peak Output Voltage
vs Supply Voltage
16
maximize performance over extended
temperatures. All devices are characterized
and qualified for 1000 hours continuous
operating life at maximum rated temperature.
T
A
= 25°C
14
12
10
8
I
= 50 µA
O
I
O
= 500 µA
6
4
10
| − Supply Voltage (V)
DD
12
14
16
6
8
4
|V
(1) Custom temperature ranges available
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC2274-HT
SGLS416 –JANUARY 2015
www.ti.com
Table of Contents
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application ................................................. 19
Power Supply Recommendations...................... 22
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics, VDD = 5 V......................... 5
6.6 Operating Characteristics, VDD = 5 V ....................... 6
6.7 Electrical Characteristics, VDD± = ±5 V ..................... 7
6.8 Operating Characteristics, VDD± = ±5 V.................... 8
6.9 Typical Characteristics............................................ 10
Detailed Description ............................................ 17
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Trademarks........................................................... 23
11.2 Electrostatic Discharge Caution............................ 23
11.3 Glossary................................................................ 23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
7
4 Revision History
DATE
REVISION
NOTES
January 2015
*
Initial release.
2
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5 Pin Configuration and Functions
V
DD+
Q3
Q6
Q9
Q12
Q14
Q16
IN+
IN−
OUT
C1
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
R3
Q5
R4
Q7
Q8
Q10
Q11
R1
R2
V
DD−
Figure 1. Equivalent Schematic (Each Amplifier)
Table 1. Actual Device Component Count(1)
COMPONENT
Transistors
Resistors
TLC2274
76
52
18
6
Diodes
Capacitors
(1) Includes both amplifiers and all ESD, bias, and trim circuitry
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6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
8
UNIT
V
VDD+
VDD–
VID
VI
Supply voltage(2)
Supply voltage(2)
Differential input voltage(3)
Input voltage(2)
–8
V
–16
VDD– – 0.3
–5
16
V
Any input
Any input
VDD+
5
V
II
Input current
mA
mA
mA
mA
IO
Output current
–50
50
Total current into VDD+
Total current out of VDD−
Duration of short-circuit current at (or below) 25°C(4)
Operating free-air temperature
–50
50
–50
50
Unlimited
TA
–40
–65
150
260
150
°C
°C
°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 s
Storage temperature
Tstg
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD–
.
(3) Differential voltages are at IN+ with respect to IN–. Excessive current will flow if input is brought below VDD– – 0.3 V.
(4) The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
6.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
All pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
±2.2
VDD−
VDD−
−40
MAX
UNIT
VDD±
VI
Supply voltage
±8
DD+ −1.5
DD+ −1.5
150
V
V
Input voltage
V
V
VIC
TA
Common-mode input voltage
Operating free-air temperature
V
°C
6.4 Thermal Information
TLC2274
PW
THERMAL METRIC(1)
UNIT
14 PINS
106.0
35.5
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47.6
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.4
ψJB
47.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics, VDD = 5 V
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
2500
3000
UNIT
25°C
300
VIO
Input offset voltage
μV
Full range
Temperature coefficient of
input offset voltage
αVIO
25°C to 125°C
25°C
2
μV/°C
Input offset voltage long-term
drift(2)
VIC = 0 V,
VO = 0 V,
VDD± = ±2.5 V,
RS = 50 Ω
0.002
0.5
μV/mo
25°C
Full range
25°C
60
IIO
Input offset current
Input bias current
pA
pA
V
7000
1
IIB
Full range
25°C
0 to 4
−0.3 to 4.2
Common-mode input voltage
range
VICR
RS = 50 Ω
|VIO| ≤ 5 mV
Full range
25°C
0 to 3.5
IOH = −20 μA
IOH = −200 μA
4.99
4.93
25°C
4.85
4.84
4.25
4.20
VOH
High-level output voltage
Low-level output voltage
Full range
25°C
V
4.65
IOH = −1 mA
VIC = 2.5 V,
VIC = 2.5 V,
Full range
25°C
IOL = 50 μA
0.01
0.09
25°C
0.15
0.16
1.5
IOL = 500 μA
VOL
Full range
25°C
V
0.9
35
VIC = 2.5 V,
IOL = 5 mA
Full range
25°C
1.6
10
8
RL = 10 kΩ(3)
RL = 1 MΩ(3)
Large-signal differential voltage VIC = 2.5 V,
amplification
AVD
Full range
25°C
V/mV
VO = 1 V to 4 V,
175
1012
Differential input resistance
rid
ri
25°C
Ω
Ω
Common-mode input
resistance
1012
8
25°C
25°C
Common-mode input
capacitance
f = 10 kHz,
N package
ci
pF
zo
Closed-loop output impedance f = 1 MHz,
AV = 10
25°C
25°C
140
75
Ω
VIC = 0 V to 2.7 V,
VO = 2.5 V,
RS = 50 Ω
70
69
80
80
CMRR Common-mode rejection ratio
dB
dB
Full range
25°C
VDD = 4.4 V to 16 V,
VIC = VDD/2,
95
Supply voltage rejection ratio
kSVR
(ΔVDD/ΔVIO
)
No load
No load
Full range
25°C
4.4
6
6
IDD
Supply current
VO = 2.5 V,
mA
Full range
(1) Full range is −40°C to 150°C for thisl part.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(3) Referenced to 2.5 V
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6.6 Operating Characteristics, VDD = 5 V
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
2.3
TYP
MAX
UNIT
VO = 0.5 V to 2.5 V,
RL = 10 kΩ(2)
25°C
Full range
25°C
3.6
CL = 100 pF(2)
SR
Vn
Slew rate at unity gain
V/μs
1.2
f = 10 Hz
50
9
Equivalent input noise voltage
nV/√Hz
f = 1 kHz
25°C
f = 0.1 to 1 Hz
f = 0.1 to 10 Hz
25°C
1
Peak-to-peak equivalent input
noise voltage
VN(pp)
In
μV
25°C
1.4
Equivalent input noise current
25°C
0.6
fA/√Hz
VO = 0.5V to 2.5V,
AV = 1
0.0013%
0.004%
0.03%
RL = 10 kΩ,
THD + Total harmonic distortion plus
AV = 10
25°C
(2)
f = 20 kHz
N
noise
AV = 100
RL = 10 kΩ(2)
Gain-bandwidth product
f = 10 kHz,
25°C
25°C
2.18
MHz
MHz
CL = 100 pF(2)
BOM
Maximum output-swing
bandwidth
VO(PP) = 2V,
AV = 1,
1
RL = 10 kΩ(2)
CL = 100 pF(2)
AV = -1,
To 0.1%
1.5
Step = 0.5V to 2.5V,
RL = 10 kΩ(2)
CL = 100 pF(2)
ts
Settling time
25°C
μs
To 0.01%
2.6
φm
Phase margin at unity gain
Gain margin
25°C
25°C
50°
10
RL = 10 kΩ
CL = 100 pF(2)
dB
(1) Full range is −40°C to 150°C for this part.
(2) Referenced to 2.5 V
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6.7 Electrical Characteristics, VDD± = ±5 V
at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
2500
3000
UNIT
25°C
300
VIO
Input offset voltage
μV
Full range
Temperature coefficient of
input offset voltage
αVIO
25°C to 125°C
25°C
2
μV/°C
Input offset voltage long-
term drift(2)
VIC = 0 V,
RS = 50 Ω
0.002
0.5
μV/mo
VO = 0 V
25°C
Full range
25°C
60
7000
60
IIO
Input offset current
Input bias current
pA
pA
V
1
IIB
Full range
25°C
7000
−5 to 4
−5.3 to 4.2
Common-mode input
voltage range
VICR
RS = 50 Ω
|VIO| ≤ 5 mV
Full range
25°C
−5 to 3.5
IO = −20 μA
4.99
4.93
25°C
4.85
4.84
4.25
4.20
IO = −200 μA
Maximum positive peak
output voltage
VOM+
Full range
25°C
V
4.65
IO = −1 mA
VIC = 0 V,
VIC = 0 V,
Full range
25°C
IO = 50 μA
−4.99
−4.91
25°C
−4.85
−4.85
−3.5
−3.45
20
IO = 500 μA
Maximum negative peak
output voltage
VOM-
Full range
25°C
V
−4.1
VIC = 0 V,
VO = ±4 V,
IO = 5 mA
Full range
25°C
50
RL = 10 kΩ
RL = 1 MΩ
Large-signal differential
voltage amplification
AVD
Full range
25°C
16
V/mV
300
Differential input
resistance
1012
rid
ri
25°C
25°C
25°C
25°C
Ω
Ω
Common-mode input
resistance
1012
8
Common-mode input
capacitance
f = 10 kHz,
f = 1 MHz,
N package
AV = 10
ci
pF
Ω
Closed-loop output
impedance
zo
130
80
VIC = -5 V to 2.7 V,
VO = 0 V,
RS = 50 Ω
25°C
Full range
25°C
75
73
80
80
Common-mode rejection
ratio
CMRR
kSVR
IDD
dB
dB
VDD = ±2.2 V to ±8 V,
VIC = 0V,
95
Supply voltage rejection
ratio (ΔVDD/ΔVIO
)
No load
No load
Full range
25°C
4.4
6
6
Supply current
VO = 0 V,
mA
Full range
(1) Full range is −40°C to 150°C for this part.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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6.8 Operating Characteristics, VDD± = ±5 V
at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
2.3
TYP
MAX
UNIT
VO = ±2.3 V,
RL = 10 kΩ
CL = 100 pF
25°C
Full range
25°C
3.6
SR
Vn
Slew rate at unity gain
V/μs
1.2
f = 10 Hz
50
9
Equivalent input noise
voltage
nV/√Hz
f = 1 kHz
25°C
f = 0.1 to 1 Hz
f = 0.1 to 10 Hz
25°C
1
Peak-to-peak equivalent
input noise voltage
VN(pp)
μV
25°C
1.4
Equivalent input noise
current
In
25°C
0.6
fA/√Hz
AV = 1
0.0011%
0.004%
0.03%
VO = ±2.3 V,
f = 20 kHz,
RL = 10 kΩ
Total harmonic distortion
plus noise
THD + N
AV = 10
25°C
AV = 100
RL = 10 kΩ
f = 10 kHz,
CL = 100 pF
Gain-bandwidth product
25°C
25°C
2.25
MHz
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 4.6 V,
RL = 10 kΩ
AV = 1,
CL = 100 pF
0.54
1.5
AV = -1,
To 0.1%
Step = -2.3 V to 2.3 V,
RL = 10 kΩ
CL = 100 pF
ts
Settling time
25°C
μs
To 0.01%
3.2
φm
Phase margin at unity gain
Gain margin
25°C
25°C
52°
10
RL = 10 kΩ,
CL = 100 pF
dB
(1) Full range is −40°C to 150°C for this part.
1000
500
Electromigration Fail Mode
300
200
100
50
30
20
10
5
3
2
1
110
120
130
140
150
160
170
180
D006
Continuous TJ (°C)
A. See data sheet for Absolute Maximum Ratings and minimum Recommended Operating Conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 2. TLC2274EPWRQ1 Operating Life Derating Chart
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R2 = 0.831049146721252
Continuous TJ (°C)
Figure 3. Estimated Wire Bond Life
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6.9 Typical Characteristics
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
1
0.5
0
20
15
10
V
= 5 V
992 Amplifiers From
2 Wafer Lots
DD
T
= 25°C
R = 50 Ω
S
A
V
DD
=
2.5 V
−0.5
−1
5
0
−1
0
1
2
3
4
5
−1.6 −1.2 −0.8 −0.4
0
0.4
0.8
1.2
1.6
V
IC
− Common-Mode Voltage − V
V
IO
− Input Offset V oltage − mV
Figure 5. Input Offset Voltage vs Common-Mode Voltage
Figure 4. Distribution of TLC2274 Input Offset Voltage
1
12
T
= 25°C
= 50 Ω
A
V
= 5 V
DD
10
8
R
S
T
A
= 25°C
= 50 Ω
R
S
0.5
6
4
2
0
|V | ≤ 5mV
IO
0
− 2
− 4
−0.5
−1
− 6
− 8
− 10
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
2
3
4
5
6
7
8
V
IC
− Common-Mode Voltage − V
|V
| − Supply Voltage − V
DD
Figure 6. Input Offset Voltage vs Common-Mode Voltage
Figure 7. Input Voltage vs Supply Voltage
6
5
V
DD
= 5 V
V
DD
= 5 V
4
3
5
4
3
|V | ≤ 5mV
IO
2
1
2
0
1
0
−1
−75 − 50 − 25
0
25
50
75
100 125
0
1
2
3
4
T
A
− Free-Air Temperature − °C
I
− High-Level Output Current − mA
OH
TA = 25°C
Figure 9. High-Level Output Voltage vs High-Level Output
Current
Figure 8. Input Voltage vs Free-Air Temperature
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
1.4
1.2
1
1.2
V
V
= 5 V
DD
V
= 5 V
DD
= 2.5 V
IC
T
A
= 25°C
1
V
IC
= 0 V
0.8
0.6
0.4
0.2
0
V
IC
= 1.25 V
0.8
0.6
0.4
0.2
0
V
IC
= 2.5 V
0
1
2
3
4
5
6
0
1
2
3
4
5
I
OL
− Low-Level Output Current − mA
I
OL
− Low-Level Output Current − mA
TA = 25°C
Figure 11. Low-Level Output Voltage vs Low-Level Output
Current
Figure 10. Low-Level Output Voltage vs Low-Level Output
Current
5
−3.8
V
DD
= 5 V
V
V
=
5 V
DD
= 0 V
IC
−4
4
−4.2
−4.4
−4.6
3
2
−4.8
−5
1
0
1
2
3
4
5
6
0
1
2
3
4
5
I
O
− Output Current − mA
|I | − Output Current − mA
O
TA = 25°C
TA = 25°C
Figure 13. Maximum Negative Peak Output Voltage vs
Output Current
Figure 12. Maximum Positive Peak Output Voltage vs
Output Current
16
10
R
= 10 kΩ
= 25°C
L
V
ID
= −100 mV
9
8
7
6
5
4
3
2
1
T
A
12
8
V
DD
= 5 V
4
V
DD
= 5 V
0
V
ID
= 100 mV
−4
−8
V
= 0 V
O
T
A
= 25°C
0
10 k
100 k
1 M
10 M
2
3
4
5
6
7
8
f − Frequency − Hz
|V
| − Supply Voltage − V
DD
Figure 14. Maximum Peak-to-Peak Output Voltage vs
Frequency
Figure 15. Short-Circuit Output Current vs Supply Voltage
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
5
4
3
2
5
V
DD
= 5 V
V
= 5 V
DD
T = 25°C
A
T
A
= 25°C
= 10 kΩ
= 2.5 V
R
L
= 10 kΩ
R
V
L
V
IC
= 0 V
3
IC
1
−1
1
−3
−5
0
−800
0
250 500 750 1000
−1000 −750 −500 −250
800
− Differential Input V oltage − µV
1200
−400
0
400
V
ID
− Differential Input V oltage − µV
V
ID
Figure 17. Output Voltage vs Differential Input Voltage
Figure 16. Output Voltage vs Differential Input Voltage
1000
80
180°
V
DD
= 5 V
V
=
1 V
O
R
C
= 10 kΩ
= 100 pF
= 25°C
L
T
A
= 25°C
L
135°
90°
45°
0°
60
40
T
A
100
10
1
V
DD
= 5 V
20
V
DD
= 5 V
0
−20
−40
−45°
−90°
0.1
0.1
1
10
100
1 k
10 k
100 k
1 M
10 M
R
L
− Load Resistance − k Ω
f − Frequency − Hz
Figure 18. Large-Signal Differential Voltage Amplification vs
Load Resistance
Figure 19. Large-Signal Differential Voltage Amplification
and Phase Margin vs Frequency
80
100
70
180°
V
= 5 V
DD
R
C
= 10 kΩ
= 100 pF
= 25°C
L
50
135°
90°
45°
0°
L
60
40
20
T
A
30
20
10
7
5
0
3
2
−20
−45°
−90°
1
−40
-50 -25
0
25
50
75 100 125 150 175 200
1 k
10 k
100 k
1 M
10 M
Free-Air Temperature, TA (°C)
f − Frequency − Hz
D003
VDD = 5 V
VIC = 2.5 V
VO = 1 to 4 V
RL = 10 kΩ
Figure 20. Large-Signal Differential Voltage Amplification
and Phase Margin vs Frequency
Figure 21. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
1000
100
V
= 5 V
DD
70
50
T
A
= 25°C
30
20
100
10
A
= 100
V
10
7
A
= 10
= 1
V
5
3
2
1
A
V
1
0.1
-50 -25
0
25
50
75 100 125 150 175 200
100
1 k
10 k 100 k
f − Frequency − Hz
1 M
Free-Air Temperature, TA (°C)
D004
VDD = ±5 V
VIC = 2.5 V
VO = ±4 V
RL = 10 kΩ
Figure 23. Output Impedance vs Frequency
Figure 22. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
1000
100
80
60
40
20
0
T
A
= 25°C
V
= 5 V
DD
T
A
= 25°C
V
= 5 V
DD
100
10
V
= 5 V
DD
A
V
= 100
A
A
= 10
= 1
V
1
V
0.1
10
100
1 k
10 k
100 k
1 M
10 M
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
f − Frequency − Hz
Figure 25. Common-Mode Rejection Ratio vs Frequency
Figure 24. Output Impedance vs Frequency
102
100
98
100
V
T
= 5 V
VDD = 5 V
VDD = ±5 V
DD
= 25°C
A
80
60
40
20
0
96
k
SVR+
94
92
k
SVR−
90
88
86
-50
−20
10
0
50
100
150
200
100
1 k
10 k
100 k
1 M
10 M
Free-Air Temperature, TA (°C)
D005
f − Frequency − Hz
Figure 26. Common-Mode Rejection Ratio vs Free-Air
Temperature
Figure 27. Supply-Voltage Rejection Ratio vs Frequency
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
100
80
60
40
20
0
110
105
100
95
V
=
5 V
DD
T
A
= 25°C
k
SVR+
k
SVR−
90
-50
−20
10
0
50
100
150
200
100
1 k
10 k
100 k
1 M
10 M
Free-Air Temperature, TA (°C)
D002
f − Frequency − Hz
VDD± = ±2.2 to ±8 V
VO = 0 V
Figure 29. Supply-Voltage Rejection Ratio vs Free-Air
Temperature
Figure 28. Supply-Voltage Rejection Ratio vs Frequency
5
5
4
3
2
1
0
V
A
= 5 V
DD
65±
SR+
= −1
V
T
A
= 25°C
4
3
2
SR −
SR +
1
0
-50
0
50
100
150
200
10
100
1 k
10 k
Free-Air Temperature, TA (°C)
C
L
− Load Capacitance − pF
D001
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
Figure 30. Slew Rate vs Load Capacitance
Figure 31. Slew Rate vs Free-Air Temperature
5
5
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
= −1
V
= 5 V
DD
DD
R
C
T
R
C
T
= 10 kΩ
= 100 pF
= 25°C
= −1
4
3
L
L
L
L
4
3
2
A
A
A
V
A
V
2
1
0
− 1
− 2
1
0
− 3
− 4
− 5
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
t − Time − µs
t − Time − µs
Figure 33. Inverting Large-Signal Pulse Response
Figure 32. Inverting Large-Signal Pulse Response
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
5
4
3
2
5
4
3
2
1
0
V
= 5 V
DD
V
= 5 V
= 10 kΩ
= 100 pF
= 1
DD
R
C
T
= 10 kΩ
= 100 pF
= 25°C
= 1
L
R
C
L
L
L
A
A
V
A
V
T
A
= 25°C
−1
−2
−3
−4
1
0
−5
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
t − Time − µs
t − Time − µs
Figure 35. Voltage-Follower Large-Signal Pulse Response
Figure 34. Voltage-Follower Large-Signal Pulse Response
100
2.65
V
= 5 V
DD
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
= −1
DD
R
C
= 10 kΩ
= 100 pF
= 25°C
= 1
L
R
C
L
L
L
2.6
2.55
2.5
T
A
T
A
A
V
50
A
V
0
−50
2.45
2.4
−100
0
0.5
1
1.5
2
2.5
3
3.5
4.5
5 5.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
t − Time − µs
t − Time − µs
Figure 36. Inverting Small-Signal Pulse Response
Figure 37. Inverting Small-Signal Pulse Response
100
2.65
V
DD
= 5 V
V
= 5 V
= 10 kΩ
= 100 pF
= 25°C
= 1
DD
R
C
= 10 kΩ
= 100 pF
= 25°C
= 1
R
C
T
L
L
L
L
T
A
2.6
2.55
2.5
A
A
V
50
0
A
V
−50
2.45
2.4
−100
0
0.5
t − Time − µs
1
1.5
0
0.5
1
1.5
t − Time − µs
Figure 39. Voltage-Follower Small-Signal Pulse Response
Figure 38. Voltage-Follower Small-Signal Pulse Response
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Typical Characteristics (continued)
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the devices.
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
= 5 V
DD
V
= 5 V
DD
T
A
= 25°C
= 20 Ω
T
A
= 25°C
= 20 Ω
R
S
R
S
10
100
1 k
10 k
10
100
1 k
10 k
f − Frequency − Hz
f − Frequency − Hz
Figure 40. Equivalent Input Noise Voltage vs Frequency
Figure 41. Equivalent Input Noise Voltage vs Frequency
1000
100
V
= 5 V
DD
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
f = 0.1 Hz to 10 Hz
= 25°C
750
500
250
0
T
A
T = 25°C
A
10
−250
−500
1
−750
0.1
−1000
1
10
100
1 k
10 k
100 k
0
2
4
6
8
10
f − Frequency − Hz
t − Time − s
Figure 42. Noise Voltage Over a 10-s Period
Figure 43. Integrated Noise Voltage vs Frequency
1
2.5
f = 10 kHz
V
T
= 5 V
DD
R
C
= 10 kΩ
= 100 pF
= 25°C
= 25°C
= 10 kΩ
L
A
R
L
L
2.4
2.3
2.2
T
A
0.1
0.01
A
= 100
V
A
= 10
= 1
V
A
V
0.001
2.1
2
0.0001
0
1
2
3
4
5
6
7
8
100
1 k
10 k
100 k
|V
| − Supply Voltage − V
DD
f − Frequency − Hz
Figure 45. Gain-Bandwidth Product vs Supply Voltage
Figure 44. Total Harmonic Distortion Plus Noise vs
Frequency
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7 Detailed Description
7.1 Overview
The TLC2274 device exhibits rail-to-rail output performance for increased dynamic range in single- or split -
supply applications. These device offers comparable ac performance while having better noise, input offset
voltage and power dissipation than existing CMOS operational amplifiers. The TLC2274 device, exhibiting high
input impedance and low noise, is excellent for small signal conditioning for high-impedance sources, such as
piezoelectric transducers. It offers increased output dynamic range, lower noise voltage, and lower input offset
voltage. This enhanced feature set allows the device to be used in a wider range of applications.
7.2 Functional Block Diagram
Vsupply+
Vin+
+
Vout
Vin±
±
Vsupply±
7.3 Feature Description
These devices use the Texas Instruments silicon gate LinCMOS™ process, giving them stable input offset
voltages, very high input impedances, and extremely low input offset and bias currents. In addition, the rail-to-rail
output feature with single- or split-supplies, makes this device a great choice when interfacing with analog-to-
digital converters (ADCs).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Macromodel Information
Macromodel information provided was derived using Microsim Parts, the model generation software used with
(1)
Microsim PSpice. The Boyle macromodel and subcircuit in Figure 46 are generated using the TLC227x typical
electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following
key parameters can be generated to a tolerance of 20% (in most cases):
•
•
•
•
•
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
(1) G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
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Application Information (continued)
99
DIN
3
EGND
+
−
V
CC+
92
9
FB
+
91
+
VIP
90
RSS
ISS
RO2
+
−
−
+
VB
DIP
RP
2
VIN
HLIM
−
+
−
10
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
DE
VAD
5
−
54
V
CC−
−
+
4
VE
OUT
.SUBCKT TLC227x 1 2 3 4 5
RD1
60
60
8
7
3
10
60
9
112.653E3
122.653E3
550
C1
C2
11
6
1214E−12
RD2
R01
R02
RP
RSS
VAD
VB
VC 3 53 DC .78
VE
VLIM
VLP
VLN
760.00E−12
53DX
5DX
91DX
90DX
3DX
0POLY (2) (3,0) (4,) 0 .5 .5
0POLY (5) VB VC VE VLP VLN 0
DC
DE
DLP
DLN
DP
5
9950
54
90
92
4
44.310E3
99925.9E3
4−.5
0DC 0
EGND
FB
99
99
54
7
91
0
4DC .78
8DC 0
0DC 1.9
92DC 9.4
+ 984.9E3 −1E6 1E6 1E6 −1E6
GA 011 12 377.0E−6
GCM 0 6 10 99 134E−9
6
ISS
HLIM
J1
J2
R2
3
10DC 216.OE−6
0VLIM 1K
210 JX
110 JX
9100.OE3
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=1.500E−12BETA=1.316E-3
+ VTO=−.270)
.ENDS
90
11
12
6
Figure 46. Boyle Macromodels and Subcircuit
8.2 Typical Application
The TLC2274 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 48 and
Figure 49 show its ability to drive loads up to 1000 pF while maintaining good gain and phase margins (Rnull =
0).
50 kΩ
V
DD+
50 kΩ
R
null
V
I
−
+
C
L
V
DD−/GND
Figure 47. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
As per Equation 1:
Table 2. Design Parameters
Improvement in Phase Margin
UGBW (kHz)
1000
R null (Ω)
CL (pF)
1000
0
0
7.15
17.43
32.12
1000
20
1000
1000
50
1000
1000
100
1000
8.2.2 Detailed Design Procedure
A smaller series resistor (Rnull) at the output of the device (see Figure 47) improves the gain and phase margins
when driving large capacitive loads. Figure 48 and Figure 49 show the effects of adding series resistances of 10
Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first is that it adds a
zero to the transfer function and the second is that it reduces the frequency of the pole associated with the
output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, Equation 1 can be used.
Δφm1 = tan–1 (2 × π × UGBW × Rnull × CL)
where
•
•
•
•
Δφm1 = Improvement in phase margin
UGBW = Unity-gain bandwidth frequency
Rnull = Output series resistance
CL = Load capacitance
(1)
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 47). To use
equation 1, UGBW must be approximated from Figure 47. Using Equation 1 alone overestimates the
improvement in phase margin, as illustrated in Figure 51. The overestimation is caused by the decrease in the
frequency of the pole associated with the load, thus providing additional phase shift and reducing the overall
improvement in phase margin. Using Figure 47, with Equation 1 enables the designer to choose the appropriate
output series resistance to optimize the design of circuits driving large capacitance loads.
8.2.3 Application Curves
TA = 25°C
75°
60°
15
12
9
V
=
5 V
DD
V
A
= 5 V
DD
T
A
= 25°C
= 1
= 10 kΩ
= 25°C
V
R
= 100 Ω
= 50 Ω
null
R
L
T
A
R
null
45°
30°
R
= 20 Ω
null
6
10 kΩ
V
15°
0°
3
DD +
10 kΩ
R
null
R
= 0
null
V
I
C
L
R
= 10 Ω
null
V
DD −
0
10
100
1000
10000
10
100 1000
− Load Capacitance − pF
10000
C
L
C
L
− Load Capacitance − pF
Figure 49. Gain Margin vs Load Capacitance
Figure 48. Phase Margin vs Load Capacitance
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TA = 25°C
25
20
15
200
175
150
R
= 500 Ω
null
125
100
R
= 100 Ω
null
10
5
R
= 200 Ω
null
75
50
R
= 50 Ω
= 10 Ω
null
R
null
25
0
0
10
1
2
3
4
5
10
1
2
3
4
5
10
10
10
10
10
10
10
10
C
− Load Capacitance (pF)
L
C
L
− Load Capacitance (pF)
Figure 51. Overestimation of Phase Margin vs Load
Capacitance
Figure 50. Unity-Gain Bandwidth vs Load Capacitance
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9 Power Supply Recommendations
TLC2274 operates from ±2.2- to ±8-V. In addition, key parameters are assured over the specified temperature
range, –55°C to 125°C. Parameters which vary significantly with operating voltage or temperature are shown in
the Typical Characteristics.
10 Layout
10.1 Layout Guidelines
The TLC2274 has very-low offset voltage and drift. To achieve highest performance, optimize circuit layout and
mechanical conditions. Offset voltage and drift can be degraded by small thermoelectric potentials at the
operational amplifier inputs. Connections of dissimilar metals generate thermal potential, which can degrade the
ultimate performance of the TLC2274. Cancel these thermal potentials by assuring that they are equal in both
input terminals.
•
•
•
Keep the thermal mass of the connections made to the two input terminals similar.
Locate heat sources as far as possible from the critical input circuitry.
Shield operational amplifier and input circuitry from air currents such as cooling fans.
10.2 Layout Example
Figure 52. Board Layout Example
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11 Device and Documentation Support
11.1 Trademarks
LinCMOS is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Jun-2015
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLC2274EPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
2274EQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
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of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2015
OTHER QUALIFIED VERSIONS OF TLC2274-HT :
Catalog: TLC2274
•
Automotive: TLC2274-Q1
•
Enhanced Product: TLC2274-EP
•
Military: TLC2274M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC2274EPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jan-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TLC2274EPWRQ1
2000
Pack Materials-Page 2
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