TLC2551CDGKR_技术文档

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

Maximum Throughput . . . 400 KSPS

INL/DNL: ±1 LSB Max, SINAD: 72 dB,

f = 20 kHz, SFDR: 85 dB, f = 20 kHz

– TLC2552 – Dual Channels With

Autosweep

– TLC2555 – Single Channel With

Pseudo-Differential Input

i

SPI/DSP-Compatible Serial Interfaces With

SCLK up to 20 MHz

Optimized DSP Mode – Requires FS Only

Low Power With Autopower Down

– Operating Current : 3.5 mA

Autopower Down: 8 µA

Single 5 V Supply

Rail-to-Rail Analog Input With 500 kHz BW

Three Options Available:

– TLC2551 – Single Channel Input

Small 8-Pin MSOP and SOIC Packages

PACKAGE TOP VIEW

TLC2551

TLC2552

TLC2555

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CS

SDO

FS

CS/FS

SDO

CS/FS

SDO

V

SCLK

V

SCLK

REF

GND

AIN

V

GND

AIN0

V

GND

V

DD

SCLK

AIN1

AIN(+)

AIN(–)

description

The TLC2551/2552/2555 are a family of high performance, 12-bit, low power, miniature 1.5 µs, CMOS

analog-to-digital converters (ADC). The TLC255x family uses a 5 V supply. Devices are available with single,

dual, or single pseudo-differential inputs. The TLC2551 has a 3-state output chip select (CS), serial output clock

(SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular

host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate

the start of a serial data frame. The TLV2552/55 have a shared CS/FS terminal.

TLC2551/2/5 are designed to operate with very low power consumption. The power saving feature is further

enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host

processors with SCLK up to 20 MHz. TLC255x family uses the SCLK as the conversion clock, thus providing

synchronous operation allowing a minimum conversion time of 1.5 µs using 20 MHz SCLK.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

8-MSOP

(DGK)

8-SOIC

(D)

TLC2551CDGK

TLC2552CDGK

TLC2555CDGK

TLC2551IDGK

TLC2552IDGK

TLC2555IDGK

0°C to 70°C

TLC2551ID

TLC2552ID

TLC2555ID

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

functional block diagram

TLC2551

TLC2552

V

DD

V

DD

REF

AIN

REF

AIN0

Mux

LOW POWER

12-BIT

AIN1

S/H

SDO

SAR ADC

LOW POWER

SAR ADC

S/H

SDO

Conversion

Clock

Conversion

Clock

SCLK

CS

CONTROL

LOGIC

CONTROL

LOGIC

SCLK

CS/FS

FS

GND

TLC2555

V

DD

REF

AIN (+)

AIN (–)

LOW POWER

12-BIT

SAR ADC

S/H

SDO

Conversion

Clock

CONTROL

LOGIC

SCLK

CS/FS

GND

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

Terminal Functions

TLC2551

TERMINAL

I/O

DESCRIPTION

NAME

AIN

NO.

4

I

Analog input channel

CS

1

Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.

CS can be used as the FS pin when a dedicated serial port is used. If TLC2551 is attached to a dedicated DSP serial

port, this terminal can be grounded.

FS

7

3

5

8

I

DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to V if not used.

DD

GND

SCLK

SDO

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

Output serial clock. This terminal receives the serial SCLK from the host processor.

I

O

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge.

The output format is MSB first.

When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge

and output data is valid on the falling edge of SCLK.

When FS is used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the falling edge of

FS or the falling edge of CS (whichever happens first). Output data is valid on the falling edge of SCLK. (This is

typically used with an active FS from a DSP).

V

6

2

I

Positive supply voltage

External reference input

DD

REF

TLC2552/55

TERMINAL

I/O

DESCRIPTION

NAME

AIN0 /AIN(+)

AIN1/AIN (–)

CS/FS

NO.

4

5

1

I

Analog input channel 0. (positive input for TLV2555)

Analog input channel 1 (inverted input for TLV2555)

Chip select/frame sync. A high-to-low transition on the CS/FS removes SDO from 3-state within a maximum delay

time.

GND

SCLK

SDO

3

7

8

I

Groundreturn for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

Output serial clock. This terminal receives the serial SCLK from the host processor.

O

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS/FS is

high and presents output data after the CS/FS falling edge until the LSB is presented. The output format is MSB

th

first. SDO returns to the Hi-Z state after the 16 SCLK. Output data is valid on the falling SCLK edge.

V

6

2

I

Positive supply voltage

External reference input

DD

REF

detailed description

The TLC2551/2/5 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1

shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, theSARcontrollogicandchargeredistributionDACareusedtoaddandsubtractfixedamountsofcharge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

detailed description (continued)

Charge

Redistribution

DAC

_

AIN

Control

Logic

ADC Code

+

GND/AIN(–)

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB

LSB

D15–D4

Conversion result (OD11–OD0)

D3–D0

Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero scale code = 000h, Vcode = GND

Full scale code = FFFh, Vcode = VREFP – 1 LSB

pseudo-differential inputs

The TLC2555 operates in pseudo-differential mode. The inverted input is available on terminal 5. It can have

a maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

TLC2551

When FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Output

data changes on the rising edge of SCLK. This is typically used for a microcontroller with SPI interface,

although it can also be used for a DSP. The microcontroller SPI interface should be programmed for

CPOL=0 (serial clock reference to ground) and CPHA=1 (data is valid on the falling edge of serial clock).

When FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Output

data changes on the rising edge of SCLK. This is typically used for a TMS320 DSP. If the TLC2551 is

attached to a dedicated DSP serial port. CS terminal can be grounded.

TLC2552/5

The CS and FS inputs are accessed via the same pin (pin 1) on the TLC2552 and TLC2555. The cycle is started

by the falling edge transition provided by either a CS (interfacing with a SPI interface microcontroller) signal or

FS (interfacing with a TMS320 DSP) signal. Timing for the TLC2555 is much like the TLC2551, with the

exception of the CS/FS line.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

detailed description (continued)

TLC2552 channel MUX reset cycle

The TLC2552 uses CS/FS to reset the AIN multiplexer. A short active CS/FS cycle (4–7 SCLKs) resets the MUX

to AIN0. If the CS/FS cycle is sufficient to complete the conversion (16 SCLKs plus maximum conversion time),

the MUX toggles to the next channel (see Figure 4 for timing).

sampling

th

The converter sample time is 12 SCLKs beginning on the 5 SCLK received after the converter has received

an active CS or FS signal (CS/FS for the TLC2552/5).

conversion

The TLC2551 completes conversion in the following manner. The conversion is started after the 16th SCLK

edge. The conversion takes 1.4 µs using 20 MHz SCLK plus 0.1 µs overhead. Enough time (for conversion)

should be allowed before a rising CS/FS edge so that no conversion is terminated prematurely.

TLC2552 input channel selection is toggled on each rising CS /FS edge. The MUX channel can be reset to AIN0

via CS /FS as described in the earlier section and in Figure 5. The input is sampled for 12 SCLKs, converted,

and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time

between samples to avoid prematurely terminating the conversion, which occurs on a rising CS /FS transition

if the conversion is not complete.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

timing diagrams/conversion cycles

DSP Interface

1

2

3

4

5

6

12

13

14

15

16

1

SCLK

CS

FS

t

(sample)

(powerdown)

t

c

OD11

OD10 OD9

OD8

OD7

OD6

OD0

SDO

Figure 2. TLC2551 DSP Mode/FS Active

µP Interface

1

2

3

4

5

6

7

12

13

14

15

16

1

SCLK

CS

FS

t

(powerdown)

(sample)

t

c

OD11 OD10 OD9

OD8

OD7

OD6

OD5

OD0

SDO

Figure 3. TLC2551 Microcontroller Mode/(SPI, CPOL = 0, CPHA = 1)

1

2

3

4

5

1

4

12

16

1

4

12

16

SCLK

CS/FS

>8 SCLKs, MUX Toggles to AIN1

<8 SCLKs, MUX

Resets to AIN0

t

(powerdown)

t

(sample)

t

c

AIN0 Result

OD11

OD0

SDO

Figure 4. TLC2552 Timing

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

timing diagrams/conversion cycles (continued)

1

2

3

4

5

6

7

12

13

14

15

16

1

SCLK

CS/FS

t

(powerdown)

(sample)

t

c

OD11

OD10

OD9

OD8

OD7

OD6

OD5

OD0

OD10

OD9

OD11

SDO

Figure 5. TLC2555 Timing

use CS as FS input

When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the

CS input if this is the only device on the serial port. This will save one output terminal from the DSP. (Output data

changes on the falling edge of SCLK. Default for TLC2552 and TLC2555).

SCLK and conversion speed

It takes 14 conversion clocks to complete the conversion. The conversion clock for the TLC2551/2/5 is equal

to SCLK/2. This yields a minimum conversion time of 1.4 µs plus 0.1 µs overhead. These devices can operate

with an SCLK up to 20 MHz for the supply voltage range specified. The total conversion time is 14× (1/10M)

+16× (1/20M)+ 0.1 µs} = 2.3 µs for a 20 MHz SCLK. This is the minimum cycle time for an active CS or CS/FS

signal. If violated, the conversion will terminate, invalidating the next data output cycle.

reference voltage

An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of

the analog inputs to produce a full-scale reading. The value of V

the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital

and the analog input should not exceed

REF

output is at full scale when the input signal is equal to or higher than V

is equal to or lower than GND.

and at zero when the input signal

REF

powerdown and powerup initialization

Autopower down is built in to the devices in order to reduce power consumption. The wake-up time is fast

enough to provide power down between each cycle. The power-down state is initiated at the end of conversion

and wakes up upon a falling edge on CS or FS.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, GND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V

DD

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V

+ 0.3 V

DD

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C

J

Operating free-air temperature range, T : C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

DD

Positive external reference voltage input, V

2.7

2

3.3

5.5

V

(see Note 1)

V

REFP

DD

Analog input voltage (see Note 1)

0

High level control input voltage, V

2.1

IH

IL

Low-level control input voltage, V

0.6

Setup time, CS falling edge (for 2551) or CS/FS falling edge (for

2552/55) before first SCLK falling edge, t

V

= REF = 5.5 V

40

ns

DD

su(CSL-SCLKL)

Hold time, CS rising edge after SCLK falling edge, t

5

0.5

ns

h(SCLKL-CSH)

Delay time, delay from CS falling edge to FS rising edge (t

7

SCLKs

ns

d(CSL-FSH)

Setup time, FS rising edge before SCLK falling edge, t

0.35

su(FSH-SCLKL)

Hold time, FS hold high after SCLK falling edge, t

h(SCLKL-FSL)

0.65

Pulse width CS high time, t

100

0.75

50

wH(CS)

wH(FS)

Pulse width FS high time, t

SCLKs

ns

SCLK cycle time, V

= 5.5–4.5 V, t

10000

0.6

DD

Pulse width low time, t

Pulse width high time, t

c(SCLK)

0.4

SCLKs

wL(SCLK)

0.4

0.6

wH(SCLK)

Hold time, hold from end of conversion to CS high, t

(EOC is internal, indicates end of

h(EOC-CSH)

0.1

µs

SCLKs

°C

conversion time, t )

c

Active CS/FS cycle time to reset internal MUX to AIN0, reset cycle TLC2552 only

4

0

7

70

85

TLC2551/2/5C

Operating free-air temperature, T

A

TLC2551/2/5I

–40

NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that

applied to GND convert as all zeros(000000000000).

2. This is the time required for the clock input signal to fall from V max or to rise from V max to V min. In the vicinity of normal room

IH

IL

IH

temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where the

sensor and A/D converter are placed several feet away from the controlling microprocessor.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

electrical characteristics over recommended operating free-air temperature range,

= V = 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)

V

DD

REF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level output voltage

Low-level output voltage

V

= 5.5 V, I

= –0.2 mA at 30 pF load

= 0.8 mA at 30 pF load

2.4

OH

DD

O

OH

OL

V

0.4

2.5

V

OL

= V

1

–1

Off-state output current

(high-impedance-state)

DD

CS = V

DD

I

µA

OZ

= 0

–2.5

2.5

O

I

High-level input current

Low-level input current

Operating supply current

V = V

DD

0.005

–0.005

3

µA

IH

I

V = 0 V

I

2.5

IL

CS at 0 V,

V

= 4.5 V ~ 5.5 V

3.5

mA

CC

DD

For all digital inputs,

Autopower-down current (0.5 µs inactive)

Autopower-down current (5 µs inactive)

8

1

0≤ V ≤ 0.3 V or V ≥ V – 0.3 V,

I

µA

I

DD

CC(AUTOPWDN)

SCLK = 0,

V

= 4.5 V to 5.5 V, Ext ref

DD

Selected channel at V

1

–1

Selected analog input channel leakage

current

DD

µA

Selected channel at 0 V

Analog inputs

20

45

5

50

C

Input capacitance

pF

i

Control Inputs

25

Input on resistance

V

= 5.5 V

500

Ω

DD

Delay time, delay from CS falling edge to

V

= REF = 5.5 V, 30 pF

40

1

ns

SDO valid, t

d(CSL-SDOV)

Delay time, delay from FS falling edge to

SDO valid, t

V

= REF = 5.5 V, 30 pF

ns

DD

d(FSL-SDOV)

Delay time, delay from SCLK rising edge

to SDO valid, t

11

30

d(SCLKH-SDOV)

th

Delay time, delay from 17 SCLK rising

edge to SDO 3-state, t

Conversion time

Sampling time

Action time

d(SCLK17H-SDOZ)

t

Conversion clock = internal oscillator

See Note 3

28

SCLK

ns

c

300

(sample)

I

start to decrease

0.5

1

SCLK

ms

CC

Autopower down

Wakeup time

I

down to MIN [I (AUTOPWDN)]

CC

2

Autopower down

0.5

SCLK

†

All typical values are at V

DD

= 5 V, T = 25°C.

A

NOTE 3: Minimal t

is given by 0.9 × 50 pF × (R + 0.5 kΩ), where R is the source output impedance.

(sample)

S S

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

ac specifications (f = 20 kHz)

i

PARAMETER

TEST CONDITIONS

MIN

TYP

72

MAX

–80

UNIT

dB

SINAD

THD

Signal-to-noise ratio + distortion

Total harmonic distortion

400 KSPS, V

= V

= 5 V

70

DD

REF

–84

11.8

–84

dB

ENOB

SFDR

Effective number of bits

Bits

dB

Spurious free dynamic range

–80

Analog Input

Full power bandwidth, –3 dB

1

MHz

kHz

Full-power bandwidth, –1 dB

500

external reference specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Reference input voltage

V

DD

V

DD

V

DD

V

DD

V

DD

= =4.5 V ~ 5.5 V

V

DD

CS = 1, SCLK = 0

100

20

MΩ

kΩ

Reference input impedance

Reference current

= 5.5 V

CS = 0, SCLK = 20 MHz

25

= V

= 5.5 V

100

400

15

µA

REF

CS = 1, SCLK = 0

5

Reference input capacitance

pF

V

CS = 0, SCLK = 20 MHz

20

45

50

V

REF

Reference voltage

= =4.5 V – 5.5 V

V

DD

dc specification, V

= V

= 4.5 V to 5.5 V, SCLK frequency = 20 MHz (unless otherwise noted)

REF

DD

PARAMETER

TEST CONDITIONS

MIN NOM

±0.6

MAX

±1

UNIT

LSB

INL

Integral linearity error (see Note 5)

Differential linearity error

DNL

See Note 4

±0.5

±1

TLC2551/52

TLC2555

±1.5

±2.5

±2

E

O

E

G

E

t

Offset error (see Note 6)

See Note 4

LSB

TLC2551/52

TLC2555

Gain error (see Note 6)

±5

TLC2551/52

TLC2555

±2

Total unadjusted error (see Note 7)

±5

NOTES: 4. Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that

applied to REFM convert as all zeros (0000000000).

5. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

7. Total unadjusted error comprises linearity, zero, and full-scale errors.

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

PARAMETER MEASUREMENT INFORMATION

t

(sample)

t

c

wH(SCLK)

V

1

2

4

12

16

IH

SCLK

V

IL

t

wL(SCLK)

t

su(CSL-SCLKL)

(powerdown)

CS

t

h(SCLKL-FSL)

WH(CS)

t

su(FSH-SCLKL)

t

h(EOC-CSH)

t

d(CSL-FSH)

t

d(SCLKH-SDOV)

FS

t

d(SCLK17H-SDOZ)

wh(FS)

OD11

OD8

OD0

SDO

t

d(CSL-SDOV)

Figure 6. Critical Timing TLC2551 (FS is active)

t

(sample)

t

su(CSL–SCLKL)

t

c

1

2

4

12

16

SCLK

t

(powerdown)

CS

t

d(SCLK17H-SDOZ)

d(SCLKH-SDOV)

OD11

OD10

OD9

OD0

SDO

t

h(EOC–CSH)

t

d(CSL-SDOV)

Figure 7. Critical Timing TLC2551 (FS = 1)

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5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

PARAMETER MEASUREMENT INFORMATION

t

(sample)

t

c

1

4

12

16

SCLK

CS/FS

t

(Reset Cycle)

MUX = AIN0

t

h(EOC-CSH)

t

d(CSLKH-SDOV)

t

d(CSL-SDOV)

OD11

OD0

OD11

SDO

t

d(SCLK17H-SDOZ)

d(CSL-SDOV)

Figure 8. Critical Timing TLC2552 Reset Cycle

t

c

t

(sample)

wH(SCLK)

V

1

2

4

12

16

IH

SCLK

V

IL

t

wL(SCLK)

t

h(SCLKL-FSL)

t

su(FSH-SCLKL)

(powerdown)

CS/FS

t

h(EOC-CSH)

d(SCLKH-SDOV)

t

wh(FS)

t

d(SCLK17H-SDOZ)

OD11

OD8

OD0

SDO

t

d(CSL-SDOV)

Figure 9. Critical Timing TLC2555 Power-Down Cycle

12

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TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

DIFFERENTIAL NONLINEARITY

vs

TEMPERATURE

0.7

0.65

0.6

0.4

0.35

0.3

V

= REF = 5.5 V

DD

400 KSPS

V

DD

= REF = 5.5 V

400 KSPS

–40

25

90

–40

25

90

°

t – Temperature –

C

°

t – Temperature –

C

Figure 10

Figure 11

OFFSET ERROR

vs

TEMPERATURE

GAIN ERROR

vs

TEMPERATURE

0.5

0.45

0.4

0.9

0.85

0.8

V

= REF = 5.5 V

DD

400 KSPS

V

DD

= REF = 5.5 V

400 KSPS

0.75

0.7

–40

25

90

25

90

°

t – Temperature –

C

°

t – Temperature –

C

Figure 12

Figure 13

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TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

TEMPERATURE

3.1

V = REF = 5.5 V

DD

400 KSPS

3.05

3

–40

25

90

°

t – Temperature –

C

Figure 14

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODES

1

V = REF = 5 V

DD

400 KSPS

0.5

0

–0.5

–1

1

4094

Digital Output Codes

Figure 15

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TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODES

1

V = REF = 5 V

DD

400 KSPS

0.5

0

–0.5

–1

1

4094

Digital Output Codes

Figure 16

2048 POINTS FAST FOURIER TRANSFORM (FFT)

0

V

DD

= REF = 5.5 V

400 KSPS

–20

f = 20 kHz

i

–40

–60

–80

–100

–120

–140

–160

0

20

40

60

80

100

120

140

160

180

200

f – Input Frequency – KHz

Figure 17

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5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

TYPICAL CHARACTERISTICS

ENOB

vs

FREQUENCY

SINAD

vs

FREQUENCY

12

75

73

71

69

V = REF = 5.5 V

DD

400 KSPS

V = REF = 5.5 V

DD

400 KSPS

11.5

11

10.5

10

67

65

0

20 40 60 80 100 120 140 160 180 200

f – Input Frequency – KHz

0

20 40 60 80 100 120 140 160 180 200

f – Input Frequency – KHz

Figure 18

Figure 19

THD

vs

FREQUENCY

–65

–70

V = REF = 5.5 V

DD

400 KSPS

–75

–80

–85

–90

0

20 40 60 80 100 120 140 160 180 200

f – Input Frequency – KHz

Figure 20

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TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

TYPICAL CHARACTERISTICS

4095

111111111111

111111111110

111111111101

V

FS

See Notes A and B

4094

4093

V

FS Nom

V

FT

= V

– 1/2 LSB

FS

2049

2048

100000000001

100000000000

V

ZT

=V

+ 1/2 LSB

ZS

2047

011111111111

V

ZS

2

1

0

000000000010

000000000001

000000000000

0

0.0012 0.0024

2.4564 2.4576 2.4588

V – Analog Input Voltage – V

4.9128

4.9140 4.9152

I

NOTES: A. This curve is based on the assumption that V

and V have been adjusted so that the voltage at the transition from digital 0 to

ref–

ref+

1 (V ) is 0.0006 V, and the transition to full scale (V ) is 4.9134 V, 1 LSB = 1.2 mV.

ZT FT

B. The full scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is

FS

ZS

the step whose nominal midstep value equals zero.

Figure 21. Ideal 12-Bit ADC Conversion Characteristics

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SLAS276 –MARCH 2000

APPLICATION INFORMATION

V

DD

EXT

Reference

10 kΩ

V

DD

XF

RXD

SCLK

FS

SDO

SCLK

V

REF

TMS320 DSP

TLC2551

CS

GND

Ain

V

DD

EXT

Reference

10 kΩ

V

DD

XF

RXD

SCLK

CS/FSD

SDO

V

REF

TMS320 DSP

SCLK

TLC2552/55

GND

†

AIN 0/AIN (+)

†

AIN 1/AIN (–)

†

For TLC2555 only

Figure 22. Typical Interface to a TMS320 DSP

simplified analog input analysis

Using the equivalent circuit in Figure 23, the time required to charge the analog input capacitance from 0 to Vs

within 1/2 LSB can be derived as follows.

The capacitance charging voltage is given by:

–tch

Rt Ci

Vc

Vs 1–EXP

(1)

Where:

Rt = Rs + Zi

tch = Charge time

The input impedance Zi is 0.5 kΩ at 5 V, and is higher (~ 0.6 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

by:

Vs

8192

Vc (1 2 LSB)

Vs–

(2)

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SLAS276 –MARCH 2000

APPLICATION INFORMATION

simplified analog input analysis (continued)

Equating equation 1 to equation 2 and solving for cycle time t gives:

c

VS

8192

–tch

Rt Ci

Vs–

Vs 1–EXP

(3)

and time to change to 1/2 LSB (equal to minimum sampling time) is:

[ ]

Min t(sample)

tch (1 2 LSB)

Rt Ci In(8192)

Where:

In(8192) = 9.011

Therefore, with the values given, the time for the analog input signal to settle is:

(4)

(5)

(

)

tch (1 2 LSB)

Rs 0.5 k

Ci In(8192)

This time must be less than the converter sample time shown in the timing diagrams. This is 12× SCLKs.

1

2

t

12

Min t

tch

LSB

(sample)

f(SCLK)

Therefore the maximum SCLK frequency is:

12

(6)

max f

SCLK

[ (

In 8192

)

]

Rt Ci

tch 1 2 LSB

maximum conversion throughput

For a supply voltage of 5 V, if the source impedance is less than 1 kΩ, and the ADC analog input capacitance

1

2

Ci is less than 50 pF, this equates to a minimum sampling time tch

LSB of 0.676 µs ( 1 µs). Since the

1

2

sampling time requires 12 SCLKs, the fastest SCLK frequency is 12 tch

LSB = 12 MHz for R ≤ 1 kΩ.

s

The minimal total cycle time, t

, is given as:

(cycle)

16

Max f(SCLK)

14

t

0.1

s

3.77

s

c

(cycle)

(sample)

(overhead)

f[(SCLK)] 0.5

This is equivalent to a maximum throughput, max[fs] of 265 KSPS.

The throughput can be even higher with a smaller source impedance. When source impedance is 100 Ω, the

minimum sampling time becomes:

tch (1 2 LSB)

Rt Ci In(8192)

0.27

s

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SLAS276 –MARCH 2000

APPLICATION INFORMATION

maximum conversion throughput (continued)

1

2

The maximum SCLK frequency possible is 12/tch

LSB = 44 MHz. Then a 20 MHz clock (maximum SCLK

frequency allowed for the internal comparator can be used. The minimal total cycle time is then reduced to:

16

t

tc

t

0.1

s

2.3

s

(cycle)

(sample)

overhead

max f(SCLK)

max f(SCLK) 2

The maximum throughput, MAX[fs], is 1/2.3 µs = 134 KSPS for this case.

Driving Source Requirements:

Driving Source

Data Converter

r

V = Input Voltage at AIN

I

R

S

i

V

C

V

i

V = External Driving Source Voltage

S

+

_

V

S

R = Source Resistance

S

t

s AMP

r

C

V

= Input Resistance (Mux On Resistance)

= Input Capacitance

= Capacitance Charging Voltage

i

C

i

C

NOTE: Noise and distortion must for the source be equivalent to the resolution of the converter.

R must be real at the input frequency.

s

Figure 23. Equivalent Input Circuit Including the Driving Source

power down calculations

Total power consumption at different conversion rate f , (f ≤ MAX [f ]) can be calculated by:

s

V

× i(AVERAGE) = V

[(f /MAX [f ]) × i(ON) + (1–f /MAX [f ]) × i(OFF)]

DD S s s s

DD

If V

= 5 V for TLC2551, and the sampling rate f = 10 kHz, the maximum sampling rate f

= 200 kHz

SMAX

DD

s

then i(ON) = ~3.5 mA operating current

and i(OFF) = ~8 µA auto-powerdown current

so V

× i(AVERAGE) = 5 × (0.05 × 3500 µA + 0.95 × 8 µA)

DD

= (5 × 182.6) µW

= 0.9 mW

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SLAS276 –MARCH 2000

MECHANICAL DATA

DGK (R-PDSO-G8)

PLASTIC SMALL-OUTLINE PACKAGE

0,38

M

0,65

8

0,25

5

0,15 NOM

3,05

2,95

4,98

4,78

Gage Plane

0,25

0°–6°

1

4

0,69

0,41

3,05

2,95

Seating Plane

0,10

0,15

0,05

1,07 MAX

4073329/B 04/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-187

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SLAS276 –MARCH 2000

MECHANICAL DATA

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

M

14

8

0.008 (0,20) NOM

0.244 (6,20)

0.228 (5,80)

0.157 (4,00)

0.150 (3,81)

Gage Plane

0.010 (0,25)

1

7

0°–8°

0.044 (1,12)

0.016 (0,40)

A

Seating Plane

0.004 (0,10)

0.010 (0,25)

0.004 (0,10)

0.069 (1,75) MAX

PINS **

8

14

16

DIM

0.197

(5,00)

0.344

(8,75)

0.394

(10,00)

A MAX

0.189

(4,80)

0.337

(8,55)

0.386

(9,80)

A MIN

4040047/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

22

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TLC2551CDGKR
厂家：	TEXAS INSTRUMENTS
描述：	12 位 400kSPS ADC，串行输出、TMS320 兼容（最高 10MHz）和单通道 \| DGK \| 8 \| 0 to 70 光电二极管转换器模数转换器
文件：	总23页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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