TLC274_V01 [TI]
LinCMOS PRECISION QUAD OPERATIONAL AMPLIFIERS;
| 型号： | TLC274_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOS PRECISION QUAD OPERATIONAL AMPLIFIERS 放大器 |
| 文件： | 总49页 (文件大小：1496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢈ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢀꢁ ꢂꢃ ꢄꢊ
ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
D
Trimmed Offset Voltage:
TLC279 . . . 900 µV Max at 25°C,
= 5 V
D, J, N, OR PW PACKAGE
(TOP VIEW)
V
DD
D
D
Input Offset Voltage Drift . . . Typically
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
1OUT
1IN−
1IN+
4OUT
13 4IN−
1
2
3
4
5
6
7
14
12
11
10
9
4IN+
GND
3IN+
3IN−
3OUT
V
DD
2IN+
2IN−
8
2OUT
D
D
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix
and I-Suffix Versions)
FK PACKAGE
(TOP VIEW)
D
D
D
D
D
Low Noise . . . Typically 25 nV/√Hz
at f = 1 kHz
3
2
1
20 19
18
Output Voltage Range Includes Negative
Rail
4IN+
NC
1IN+
NC
4
5
6
7
8
17
16
15
14
12
High Input Impedance . . . 10 Ω Typ
GND
NC
V
DD
NC
ESD-Protection Circuitry
3IN+
2IN+
Small-Outline Package Option Also
Available in Tape and Reel
9 10 11 12 13
D
Designed-In Latch-Up Immunity
description
NC − No internal connection
The TLC274 and TLC279 quad operational
amplifiers combine a wide range of input offset
voltage grades with low offset voltage drift, high
input impedance, low noise, and speeds
approaching that of general-purpose BiFET
devices.
DISTRIBUTION OF TLC279
INPUT OFFSET VOLTAGE
30
25
20
15
10
5
290 Units Tested From 2 Wafer Lots
= 5 V
V
T
A
DD
= 25°C
These devices use Texas Instruments silicon-
gate LinCMOS technology, which provides
offset voltage stability far exceeding the stability
N Package
available
with
conventional
metal-gate
processes.
The extremely high input impedance, low bias
currents, and high slew rates make these
cost-effective devices ideal for applications which
have previously been reserved for BiFET and
NFET products. Four offset voltage grades are
available (C-suffix and I-suffix types), ranging
from the low-cost TLC274 (10 mV) to the high-
precision TLC279 (900 µV). These advantages, in
combination with good common-mode rejection
and supply voltage rejection, make these devices
a good choice for new state-of-the-art designs as
well as for upgrading existing designs.
0
−1200
−600
0
600
1200
V
IO
− Input Offset Voltage − µV
LinCMOS is a trademark of Texas Instruments.
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Copyright 2001, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
description (continued)
In general, many features associated with bipolar technology are available on LinCMOS operational
amplifiers, without the power penalties of bipolar technology. General applications such as transducer
interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the
TLC274 and TLC279. The devices also exhibit low voltage single-supply operation, making them ideally suited
for remote and inaccessible battery-powered applications. The common-mode input voltage range includes the
negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC274 and TLC279 incorporate internal ESD-protection circuits that prevent functional failures at voltages
up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling
these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
V
max
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
IO
T
A
FORM
(Y)
TSSOP
(PW)
AT 25°C
(J)
(N)
900 µV
2 mV
5 mV
TLC279CD
TLC274BCD
TLC274ACD
TLC274CD
—
—
—
—
—
—
—
—
TLC279CN
TLC274BCN
TLC274ACN
TLC274CN
—
—
—
—
—
—
0°C to 70°C
10 mV
TLC274CPW
TLC274Y
900 µV
2 mV
5 mV
TLC279ID
TLC274BID
TLC274AID
TLC274ID
—
—
—
—
—
—
—
—
TLC279IN
TLC274BIN
TLC274AIN
TLC274IN
—
—
—
—
—
—
—
—
−40°C to 85°C
−55°C to 125°C
10 mV
900 µV
10 mV
TLC279MD
TLC274MD
TLC279MFK
TLC274MFK
TLC279MJ
TLC274MJ
TLC279MN
TLC274MN
—
—
—
—
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC279CDR).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
equivalent schematic (each amplifier)
V
DD
P3
P4
R6
R1
R2
N5
C1
IN−
P5
P6
P2
P1
IN+
R5
OUT
N3
D2
N1
R3
N2
D1
N4
N6
R7
N7
R4
GND
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TLC274Y chip information
These chips, when properly assembled, display characteristics similar to the TLC274C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
V
DD
(4)
(14)
(11)
(8)
(13)
(12)
(10)
(9)
(3)
(2)
+
−
1IN+
1IN−
(1)
1OUT
(5)
(6)
+
2IN+
2IN−
(7)
2OUT
−
(10)
(9)
68
+
−
3IN+
3IN−
(8)
3OUT
(12)
(13)
+
−
4IN+
4IN−
(14)
4OUT
11
(2)
(3)
(6)
(1)
(5)
(4)
108
(7)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T max = 150°C
J
TOLERANCES ARE 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACK SIDE OF CHIP.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
V
ID
DD
DD
I
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, l (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
DD
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input with respect to the inverting input.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
494 mW
715 mW
715 mW
819 mW
—
POWER RATING
A
D
FK
J
950 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
12.6 mW/°C
5.6 mW/°C
608 mW
—
275 mW
275 mW
—
1375 mW
1375 mW
1575 mW
700 mW
880 mW
880 mW
N
1008 mW
448 mW
PW
—
recommended operating conditions
C SUFFIX
I SUFFIX
M SUFFIX
UNIT
MIN
3
MAX
MIN
4
MAX
MIN
4
MAX
16
Supply voltage, V
DD
16
3.5
8.5
70
16
3.5
8.5
85
V
V
V
= 5 V
−0.2
−0.2
0
−0.2
−0.2
−40
0
3.5
DD
Common-mode input voltage, V
IC
V
= 10 V
0
8.5
DD
Operating free-air temperature, T
−55
125
°C
A
5
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC274C, TLC274AC,
TLC274BC, TLC279C
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
L
TLC274C
TLC274AC
TLC274BC
TLC279C
12
mV
0.9
340
320
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
6.5
S
L
V
IO
Input offset voltage
2000
3000
900
1500
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
70°C
α
1.8
µV/°C
pA
VIO
25°C
70°C
25°C
70°C
0.1
7
60
300
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
O
= 2.5 V,
V
IC
= 2.5 V
0.6
40
I
IB
pA
600
−0.2
to
−0.3
to
4.2
25°C
V
V
4
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
3.5
25°C
0°C
3.2
3
3.8
3.8
3.8
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
R
= 10 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
70°C
25°C
0°C
3
50
50
50
0
= −100 mV,
= 0.25 V to 2 V,
I
OL
OL
70°C
25°C
0°C
0
5
4
23
27
20
80
84
85
95
94
96
2.7
3.1
2.3
Large-signal differential voltage
amplification
A
R
= 10 kΩ
VD
L
70°C
25°C
0°C
4
65
60
60
65
60
60
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
70°C
25°C
0°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
70°C
25°C
0°C
6.4
7.2
5.2
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (four amplifiers)
mA
DD
No load
70°C
†
Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢈ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢉꢆ ꢀꢁ ꢂꢃ ꢄꢊ
ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, V
= 10 V (unless otherwise noted)
DD
TLC274C, TLC274AC,
TLC274BC, TLC279C
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
L
TLC274C
TLC274AC
TLC274BC
TLC279C
12
mV
0.9
390
370
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
6.5
S
L
V
IO
Input offset voltage
2000
3000
1200
1900
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
S
L
Average temperature coefficient of
input offset voltage
25°C to
70°C
α
2
µV/°C
pA
VIO
25°C
70°C
25°C
70°C
0.1
7
60
300
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
O
=.5 V,
V
IC
= 5 V
0.7
50
I
IB
pA
600
−0.2
to
−0.3
to
9.2
25°C
V
V
9
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
8.5
25°C
0°C
8
7.8
7.8
8.5
8.5
8.4
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 10 kΩ
V
mV
V/mV
dB
OH
ID
ID
O
L
70°C
25°C
0°C
50
50
50
0
I
= 0
OL
OL
70°C
25°C
0°C
0
10
7.5
7.5
65
60
60
65
60
60
36
42
32
85
88
88
95
94
96
3.8
4.5
3.2
Large-signal differential voltage
amplification
A
R
= 10 kΩ
VD
L
70°C
25°C
0°C
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
70°C
25°C
0°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
70°C
25°C
0°C
8
8.8
6.8
= 5 V,
= 5 V,
O
IC
I
Supply current (four amplifiers)
mA
DD
No load
70°C
†
Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢉꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢊ
ꢎ
ꢁ
ꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢓ
ꢏꢓ
ꢎ
ꢔ
ꢕ
ꢖ
ꢇ
ꢗ
ꢎ
ꢐꢒ
ꢑ
ꢇꢀ
ꢓ
ꢔ
ꢇ
ꢁ
ꢇ
ꢍ
ꢐ
ꢁ
ꢓ
ꢘ
ꢓ
ꢒ
ꢑ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC274I, TLC274AI,
TLC274BI, TLC279I
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
L
TLC274I
TLC274AI
TLC274BI
TLC279I
13
mV
0.9
340
320
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
7
S
L
V
IO
Input offset voltage
2000
3500
900
2000
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
85°C
α
1.8
µV/°C
pA
VIO
25°C
85°C
25°C
85°C
0.1
24
60
1000
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
O
= 2.5 V,
V
IC
= 2.5 V
0.6
200
I
IB
pA
2000
−0.2
to
−0.3
to
4.2
25°C
V
4
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
3.5
Full range
V
V
25°C
−40°C
85°C
3.2
3
3.8
3.8
3.8
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
R
= 10 kΩ
= 0
OH
ID
ID
O
L
3
25°C
50
50
50
−40°C
85°C
0
= −100 mV,
= 0.25 V to 2 V,
I
mV
V/mV
dB
OL
OL
0
25°C
5
3.5
3.5
65
60
60
65
60
60
23
32
19
80
81
86
95
92
96
2.7
3.8
2.1
Large-signal differential voltage
amplification
−40°C
85°C
A
VD
R
= 10 kΩ
L
25°C
−40°C
85°C
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
25°C
−40°C
85°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
25°C
6.4
8.8
4.8
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (four amplifiers)
−40°C
85°C
mA
DD
No load
†
Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢈ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢉꢆ ꢀꢁ ꢂꢃ ꢄꢊ
ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, V
= 10 V (unless otherwise noted)
DD
TLC274I, TLC274AI,
TLC274BI, TLC279I
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
L
TLC274I
TLC274AI
TLC274BI
TLC279I
13
mV
0.9
390
370
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
7
S
L
V
IO
Input offset voltage
2000
3500
1200
2900
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
85°C
α
2
µV/°C
pA
VIO
25°C
85°C
25°C
85°C
0.1
26
60
1000
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
O
= 5 V,
V
IC
= 5 V
0.7
220
I
IB
pA
2000
−0.2
to
−0.3
to
9.2
25°C
V
V
9
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
8.5
25°C
−40°C
85°C
8
7.8
7.8
8.5
8.5
8.5
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 10 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
25°C
50
50
50
−40°C
85°C
0
I
OL
OL
0
25°C
10
7
36
47
31
85
87
88
95
92
96
3.8
5.5
2.9
Large-signal differential voltage
amplification
−40°C
85°C
A
R
= 10 kΩ
VD
L
7
25°C
65
60
60
65
60
60
−40°C
85°C
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
25°C
−40°C
85°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
25°C
8
10
= 5 V,
= 5 V,
O
IC
I
Supply current (four amplifiers)
−40°C
85°C
mA
DD
No load
6.4
†
Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢉꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢊ
ꢎ
ꢁ
ꢋ
ꢌ
ꢂ
ꢍꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢓ
ꢏꢓ
ꢎ
ꢔ
ꢕ
ꢖ
ꢇ
ꢗ
ꢎ
ꢐꢒ
ꢑ
ꢇꢀ
ꢓ
ꢔ
ꢇ
ꢁ
ꢇ
ꢍ
ꢐ
ꢁ
ꢓ
ꢘ
ꢓ
ꢒ
ꢑ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC274M, TLC279M
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
L
TLC274M
TLC279M
mV
12
V
IO
Input offset voltage
320
900
3750
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
L
µV
Full range
S
Average temperature coefficient of input
offset voltage
25°C to
125°C
α
VIO
2.1
µV/°C
25°C
125°C
25°C
0.1
1.4
0.6
9
60
15
60
35
pA
nA
pA
nA
I
Input offset current (see Note 4)
Input bias current (see Note 4)
IO
V
O
= 2.5 V,
V
IC
= 2.5 V
I
IB
125°C
0
to
4
−0.3
to
4.2
25°C
V
V
Common-mode input voltage range
(see Note 5)
V
ICR
0
to
3.5
Full range
25°C
−55°C
125°C
25°C
3.2
3
3.8
3.8
3.8
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
R
= 10 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
3
50
50
50
−55°C
125°C
25°C
0
= −100 mV,
= 0.25 V to 2 V,
I
OL
OL
0
5
3.5
3.5
65
60
60
65
60
60
23
35
16
80
81
84
95
90
97
2.7
4
Large-signal differential voltage
amplification
−55°C
125°C
25°C
A
VD
R
= 10 kΩ
L
−55°C
125°C
25°C
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
−55°C
125°C
25°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
6.4
10
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (four amplifiers)
−55°C
125°C
mA
DD
No load
1.9
4.4
†
Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢈ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢉꢆ ꢀꢁ ꢂꢃ ꢄꢊ
ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics at specified free-air temperature, V
= 10 V (unless) otherwise noted)
DD
TLC274M, TLC279M
†
T
A
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
L
TLC274M
TLC279M
mV
12
V
IO
Input offset voltage
370
1200
4300
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
IC
L
µV
Full range
S
Average temperature coefficient of input
offset voltage
25°C to
125°C
α
VIO
2.2
µV/°C
25°C
125°C
25°C
0.1
1.8
0.7
10
60
15
60
35
pA
nA
pA
nA
I
Input offset current (see Note 4)
Input bias current (see Note 4)
IO
V
O
= 5 V,
V
IC
= 5 V
I
IB
125°C
0
to
9
−0.3
to
9.2
25°C
V
V
Common-mode input voltage range
(see Note 5)
V
ICR
0
to
8.5
Full range
25°C
−55°C
125°C
25°C
8
7.8
7.8
8.5
8.5
8.4
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 10 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
50
50
50
−55°C
125°C
25°C
0
I
OL
OL
0
10
7
36
50
27
85
87
86
95
90
97
3.8
6.0
2.5
Large-signal differential voltage
amplification
−55°C
125°C
25°C
A
VD
R
= 10 kΩ
L
7
65
60
60
65
60
60
−55°C
125°C
25°C
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
−55°C
125°C
25°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
8
12
= 5 V,
= 5 V,
O
IC
I
Supply current (four amplifiers)
−55°C
125°C
mA
DD
No load
5.6
†
Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢈꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢉꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢊ
ꢎ
ꢁ
ꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢓ
ꢏꢓ
ꢎ
ꢔ
ꢕ
ꢖ
ꢇ
ꢗ
ꢎ
ꢐꢒ
ꢑ
ꢇ
ꢀ
ꢓ
ꢔ
ꢇ
ꢁ
ꢇ
ꢍ
ꢐ
ꢁ
ꢓ
ꢘ
ꢓ
ꢒ
ꢑ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC274C, TLC274AC,
TLC274AC,
TLC274BC, TLC279C
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
3.6
4
MAX
25°C
0°C
V
V
= 1 V
IPP
R
C
= 10 Ω,
L
L
70°C
25°C
0°C
3
= 20 F,
SR
Slew rate at unity gain
V/µs
P
2.9
3.1
2.5
See Figure 1
= 2.5 V
IPP
70°C
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
0°C
320
340
260
1.7
2
V
R
= V
OH
= 10 kΩ,
,
C
= 20 F,
P
O
L
B
B
Maximum output-swing bandwidth
kHz
OM
See Figure 1
70°C
25°C
0°C
V = 10 mV,
I
See Figure 3
C = 20 F,
L P
Unity-gain bandwidth
Phase margin
MHz
1
70°C
25°C
0°C
1.3
46°
47°
44°
V = 10 mV,
f = B ,
1
I
L
φ
m
C
= 20 F,
P
70°C
operating characteristics at specified free-air temperature, V
= 10 V
DD
TLC274C, TLC274AC,
TLC274AC,
TLC274BC, TLC279C
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
5.3
5.9
4.3
4.6
5.1
3.8
MAX
25°C
0°C
V
V
= 1 V
IPP
R
C
= 10 Ω,
L
L
70°C
25°C
0°C
= 20 F,
SR
Slew rate at unity gain
V/µs
P
See Figure 1
= 5.5 V
IPP
70°C
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
0°C
200
220
140
2.2
2.5
1.8
49°
50°
46°
V
R
= V
OH
= 10 kΩ,
,
C
= 20 F,
P
O
L
B
B
Maximum output-swing bandwidth
kHz
OM
See Figure 1
70°C
25°C
0°C
V = 10 mV,
I
See Figure 3
C = 20 F,
L P
Unity-gain bandwidth
Phase margin
MHz
1
70°C
25°C
0°C
V = 10 mV,
f = B ,
1
See Figure 3
I
L
φ
m
C
= 20 F,
P
70°C
12
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC274I, TLC274AI,
TLC274BI, TLC279I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
3.6
4.5
2.8
2.9
3.5
2.3
MAX
25°C
−40°C
85°C
V
= 1 V
IPP
IPP
R
C
= 10 kΩ,
L
L
= 20 F,
SR
Slew rate at unity gain
V/µs
P
25°C
See Figure 1
−40°C
85°C
V
= 2.5 V
R
= 20 Ω,
f = 1 kHz,
See Figure 2
S
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
−40°C
85°C
320
380
250
1.7
2.6
1.2
46°
49°
43°
V
R
= V
OH
,
C
= 20 F,
P
O
L
L
B
B
Maximum output-swing bandwidth
kHz
OM
= 10 kΩ,
See Figure 1
25°C
V = 10 mV,
I
See Figure 3
C = 20 F,
L P
−40°C
85°C
Unity-gain bandwidth
Phase margin
MHz
1
25°C
V
C
= 10 mV,
f = B ,
1
See Figure 3
I
φ
m
−40°C
85°C
= 20 F,
L
P
operating characteristics at specified free-air temperature, V
= 10 V
DD
TLC274I, TLC274AI,
TLC274BI, TLC279I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
5.3
6.7
4
MAX
25°C
−40°C
85°C
V
= 1 V
IPP
IPP
R
C
= 10 Ω,
L
L
= 20 F,
SR
Slew rate at unity gain
V/µs
P
25°C
4.6
5.8
3.5
See Figure 1
−40°C
85°C
V
= 5.5 V
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
−40°C
85°C
200
260
130
2.2
3.1
1.7
49°
52°
46°
V
R
= V
OH
,
C
= 20 F,
P
O
L
L
B
B
Maximum output-swing bandwidth
kHz
OM
= 10 kΩ,
See Figure 1
25°C
V = 10 mV,
I
See Figure 3
C = 20 F,
L P
−40°C
85°C
Unity-gain bandwidth
Phase margin
MHz
1
25°C
V
C
= 10 mV,
f = B ,
1
See Figure 3
I
φ
m
−40°C
85°C
= 20 F,
L
P
13
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ꢁ
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ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢓ
ꢏꢓ
ꢎ
ꢔ
ꢕ
ꢖ
ꢇ
ꢗ
ꢎ
ꢐꢒ
ꢑ
ꢇꢀ
ꢓ
ꢔ
ꢇ
ꢁ
ꢇ
ꢍ
ꢐ
ꢁ
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ꢓ
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ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC274M, TLC279M
PARAMETER
TEST CONDITIONS
T
UNIT
A
MIN
TYP
3.6
4.7
2.3
2.9
3.7
2
MAX
25°C
−55°C
125°C
25°C
V
= 1 V
IPP
IPP
R
C
= 10 kΩ,
L
L
= 20 F,
SR
Slew rate at unity gain
V/µs
P
See Figure 1
−55°C
125°C
V
= 2.5 V
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
−55°C
125°C
25°C
320
400
230
1.7
2.9
1.1
46°
49°
41°
V
R
= V
= 10 kΩ,
,
C
= 20 F,
P
O
L
OH
L
kHz
B
B
Maximum output-swing bandwidth
OM
See Figure 1
V
I
= 10 mV,
C = 20 F,
L P
−55°C
125°C
25°C
MHz
Unity-gain bandwidth
Phase margin
1
See Figure 3
V
C
= 10 mV,
= 20 F,
f = B ,
1
See Figure 3
I
φ
m
−55°C
125°C
L
P
operating characteristics at specified free-air temperature, V
= 10 V
DD
TLC274M, TLC279M
PARAMETER
TEST CONDITIONS
T
UNIT
A
MIN
TYP
5.3
7.1
3.1
4.6
6.1
2.7
MAX
25°C
−55°C
125°C
25°C
V
= 1 V
IPP
IPP
R
C
= 10 Ω ,
L
L
= 20 F,
SR
Slew rate at unity gain
V/µs
P
See Figure 1
−55°C
125°C
V
= 5.5 V
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
−55°C
125°C
25°C
200
280
110
2.2
3.4
1.6
49°
52°
44°
V
R
= V
= 10 kΩ,
,
C
= 20 F,
P
O
L
OH
L
B
B
Maximum output-swing bandwidth
kHz
OM
See Figure 1
V
I
= 10 mV,
C = 20 F,
L P
−55°C
125°C
25°C
Unity-gain bandwidth
Phase margin
MHz
1
See Figure 3
V
C
= 10 mV,
= 20 F,
f = B ,
1
See Figure 3
I
φ
m
−55°C
125°C
L
P
14
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
DD
A
TLC274Y
TYP
PARAMETER
Input offset voltage
TEST CONDITIONS
UNIT
MIN
MAX
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
V
IO
1.1
10
mV
L
I
I
Input offset current (see Note 4)
Input bias current (see Note 4)
0.1
0.6
pA
pA
IO
V
O
= 2.5 V,
V
IC
= 2.5 V
IB
−0.2
to
−0.3
to
4.2
V
ICR
Common-mode input voltage range (see Note 5)
V
4
V
V
High-level output voltage
V
V
V
V
V
V
= 100 mV,
R
= 10 kΩ
= 0
3.2
3.8
0
V
mV
V/mV
dB
OH
ID
ID
O
L
Low-level output voltage
= −100 mV,
= 0.25 V to 2 V,
I
50
OL
OL
A
VD
Large-signal differential voltage amplification
R
= 10 kΩ
5
65
65
23
80
95
L
CMRR Common-mode rejection ratio
= V
min
= 5 V to 10 V,
IC
DD
ICR
k
Supply-voltage rejection ratio (∆V
/∆V
IO
)
V
V
= 1.4 V
dB
SVR
DD
O
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (four amplifiers)
2.7
6.4
mA
DD
No load
electrical characteristics, V
= 10 V, T = 25°C (unless otherwise noted)
DD
A
TLC274Y
TYP
PARAMETER
Input offset voltage
TEST CONDITIONS
UNIT
MIN
MAX
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 10 kΩ
O
S
IC
V
IO
1.1
10
mV
L
I
I
Input offset current (see Note 4)
Input bias current (see Note 4)
0.1
0.7
pA
pA
IO
V
O
= 5 V,
V
IC
= 5 V
IB
−0.2
to
−0.3
to
9.2
V
ICR
Common-mode input voltage range (see Note 5)
V
9
V
V
High-level output voltage
V
V
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 10 kΩ
= 0
8
8.5
0
V
mV
V/mV
dB
OH
ID
ID
O
L
Low-level output voltage
I
50
OL
OL
A
VD
Large-signal differential voltage amplification
R
= 10 kΩ
10
65
65
36
85
95
L
CMRR Common-mode rejection ratio
= V
min
= 5 V to 10 V,
IC
DD
ICR
k
Supply-voltage rejection ratio (∆V
/∆V
IO
)
V
V
= 1.4 V
dB
SVR
DD
O
= 5 V,
= 5 V,
O
IC
I
Supply current (four amplifiers)
3.8
8
mA
DD
No load
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
15
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
operating characteristics, V
= 5 V, T = 25°C
A
DD
TLC274Y
TYP
3.6
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
V
V
= 1 V
R
= 10 kΩ,
C
= 20 F,
P
IPP
L
L
SR
Slew rate at unity gain
V/µs
nV/√Hz
kHz
See Figure 1
= 2.5 V
2.9
IPP
V
B
B
Equivalent input noise voltage
f = 1 kHz,
R
C
= 20 Ω,
See Figure 2
R = 10 kΩ,
L
25
n
S
L
V
O
= V
OH
,
= 20 F,
P
Maximum output-swing bandwidth
Unity-gain bandwidth
Phase margin
320
1.7
46°
OM
See Figure 1
V
V
= 10 mV,
= 10 mV,
C
= 20 F,
See Figure 3
MHz
1
I
L
P
f = B ,
C
= 20 F,
L P
I
1
φ
m
See Figure 3
operating characteristics, V
= 10 V, T = 25°C
A
DD
TLC274Y
TYP
5.3
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
V
V
= 1 V
R
= 10 kΩ,
C
= 20 F,
P
IPP
L
L
SR
Slew rate at unity gain
V/µs
nV/√Hz
kHz
See Figure 1
= 5.5 V
4.6
IPP
V
B
B
Equivalent input noise voltage
f = 1 kHz,
R
C
= 20 Ω,
See Figure 2
R = 10 kΩ,
L
25
n
S
L
V
O
= V
OH
,
= 20 F,
P
Maximum output-swing bandwidth
Unity-gain bandwidth
Phase margin
200
2.2
49°
OM
See Figure 1
V
V
= 10 mV,
= 10 mV,
C
= 20 F,
See Figure 3
C = 20 F,
L
MHz
1
I
L
P
f = B ,
I
1
P
φ
m
See Figure 3
16
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC274 and TLC279 are optimized for single-supply operation, circuit configurations used for the
various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.
V
DD
V
DD
+
−
−
V
O
V
O
+
+
V
I
V
I
C
R
C
R
L
L
L
L
V
DD
−
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
2 kΩ
2 kΩ
V
DD
+
V
DD
20 Ω
20 Ω
−
+
−
+
1/2 V
DD
V
O
V
O
20 Ω
20 Ω
V
DD
−
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 2. Noise-Test Circuit
10 kΩ
10 kΩ
V
V
+
DD
DD
100 Ω
100 Ω
−
−
V
I
V
I
V
O
V
O
+
+
1/2 V
DD
C
C
L
L
V
DD
−
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
17
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC274 and TLC279 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
7
1
V = V
IC
8
14
Figure 4. Isolation Metal Around Device Inputs (J and N packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
18
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz
(b) BOM > f > 1 kHz
(c) f = BOM
(d) f > BOM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
19
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
6, 7
V
IO
Input offset voltage
Distribution
α
VIO
Temperature coefficient of input offset voltage
Distribution
8, 9
vs High-level output current
vs Supply voltage
vs Free-air temperature
10, 11
12
13
V
V
High-level output voltage
OH
vs Common-mode input voltage
vs Differential input voltage
vs Free-air temperature
14, 15
16
17
Low-level output voltage
OL
vs Low-level output current
18, 19
vs Supply voltage
vs Free-air temperature
vs Frequency
20
21
32, 33
A
VD
Large-signal differential voltage amplification
I
I
Input bias current
vs Free-air temperature
vs Free-air temperature
vs Supply voltage
22
22
23
IB
Input offset current
IO
V
Common-mode input voltage
IC
vs Supply voltage
vs Free-air temperature
24
25
I
Supply current
Slew rate
DD
vs Supply voltage
vs Free-air temperature
26
27
SR
Normalized slew rate
vs Free-air temperature
vs Frequency
28
29
V
B
Maximum peak-to-peak output voltage
O(PP)
vs Free-air temperature
vs Supply voltage
30
31
Unity-gain bandwidth
Phase margin
1
vs Supply voltage
vs Free-air temperature
vs Load capacitance
34
35
36
φ
m
V
n
Equivalent input noise voltage
Phase shift
vs Frequency
vs Frequency
37
32, 33
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC274
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC274
INPUT OFFSET VOLTAGE
60
50
40
30
20
10
0
60
50
40
30
20
10
0
753 Amplifiers Tested From 6 Wafer Lots
DD
753 Amplifiers Tested From 6 Wafer Lots
V
= 5 V
V
T
A
= 10 V
DD
= 25°C
T = 25°C
A
N Package
N Package
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 6
Figure 7
DISTRIBUTION OF TLC274 AND TLC279
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC274 AND TLC279
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
TEMPERATURE COEFFICIENT
60
50
40
30
20
10
0
60
50
40
30
20
10
0
324 Amplifiers Tested From 8 Wafer Lots
324 Amplifiers Tested From 8 Wafer Lots
V
T
A
= 5 V
DD
= 25°C to 125°C
V
T
A
= 10 V
DD
= 25°C to 125°C
N Package
Outliers:
(1) 20.5 V/°C
N Package
Outliers:
(1) 21.2 V/C
−10 −8 −6 −4 −2
0
2
4
6
8
10
−10 −8 −6 −4 −2
0
2
4
6
8
10
α
VIO
− Temperature Coefficient − µV/°C
α
VIO
− Temperature Coefficient − µV/°C
Figure 8
Figure 9
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
Q
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5
4
3
2
1
0
16
14
12
10
8
V
= 100 mV
V
= 100 mV
ID
= 25°C
ID
T = 25°C
A
T
A
V
= 16 V
DD
V
= 5 V
DD
V
= 4 V
DD
V
= 10 V
DD
V
= 3 V
DD
6
4
2
0
0
−2
−4
−6
−8
−10
0
−5
I
−10 −15 −20 −25 −30 −35 −40
− High-Level Output Current − mA
I
− High-Level Output Current − mA
OH
OH
Figure 10
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
V
V
V
V
−1.6
−1.7
−1.8
−1.9
16
14
12
10
8
DD
DD
DD
I
= −5 mA
OH
V
= 100 mV
ID
V
= 100 mA
ID
R
T
A
= 10 kΩ
= 25°C
L
V
DD
= 5 V
DD
V
−2
DD
V
DD
= 10 V
V
DD
V
DD
V
DD
V
DD
−2.1
−2.2
−2.3
−2.4
6
4
2
0
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 12
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
700
650
500
450
400
350
300
250
V
= 5 V
DD
V
= 10 V
= 5 mA
DD
I
= 5 mA
OL
I
OL
T
A
= 25°C
T
A
= 25°C
600
550
V
= −100 mV
ID
V
V
V
= −100 mV
= −1 V
500
450
ID
ID
ID
= −2.5 V
400
350
V
ID
= −1 V
300
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 14
Figure 15
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
FREE-AIR TEMPERATURE
800
700
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
I
V
V
= 5 mA
= −1 V
= 0.5 V
I
V
T
= 5 mA
OL
ID
IC
OL
IC
A
= |V /2|
ID
= 25°C
V
= 5 V
DD
V
= 5 V
DD
V
DD
= 10 V
V
= 10 V
DD
−75 −50 −25
0
25
50
75
100 125
0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10
T
A
− Free-Air Temperature − °C
V
ID
− Differential Input Voltage − V
Figure 16
Figure 17
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
2.5
2
V
V
T
A
= −1 V
= 0.5 V
= 25°C
V
V
T
A
= −1 V
= 0.5 V
= 25°C
ID
IC
ID
IC
V
= 16 V
DD
V
= 5 V
DD
V
= 4 V
DD
V
= 10 V
DD
V
= 3 V
DD
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 18
Figure 19
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
T
= −55°C
A
R
= 10 kΩ
R
= 10 kΩ
L
L
T
A
= 0°C
V
= 10 V
DD
V
= 5 V
T
= 25°C
= 85°C
= 125°C
DD
A
T
A
T
A
5
0
0
2
4
6
8
10
12
14
16
−75 −50 −25
0
25
50
75
100 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 20
Figure 21
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
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ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
10000
1000
100
10
V
V
= 10 V
16
14
12
10
8
DD
= 5 V
IC
T
A
= 25°C
See Note A
I
IB
I
IO
6
1
4
2
0.1
25
45
65
85
105
125
0
T
− Free-Air Temperature − °C
0
2
4
V
6
8
10
12
14
16
A
− Supply Voltage − V
DD
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 22
Figure 23
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
10
8
7
6
5
4
3
2
1
0
V
= V /2
DD
V = V /2
O DD
9
8
O
No Load
No Load
T
= −55°C
= 0°C
A
7
6
5
4
3
T
A
T
A
= 25°C
V
DD
= 10 V
V
DD
= 5 V
2
1
0
T
A
= 70°C
T
= 125°C
A
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 24
Figure 25
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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ꢏ
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ꢍꢎ
ꢐ
ꢑ
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ꢏ
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ꢔ
ꢕ
ꢖ
ꢇ
ꢗ
ꢎ
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ꢘ
ꢓ
ꢒ
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ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
FREE-AIR TEMPERATURE
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
A
R
C
= 1
= 10 kΩ
= 20 pF
V
L
L
A
= 1
= 1 V
V
V
IPP
V
V
= 10 V
= 5.5 V
DD
IPP
R
C
= 10 kΩ
= 20 pF
= 25°C
L
L
See Figure 1
T
A
V
V
= 10 V
= 1 V
See Figure 1
DD
IPP
V
V
= 5 V
= 1 V
DD
IPP
2
1
V
V
= 5 V
DD
= 2.5 V
IPP
0
0
2
4
6
8
10
12
14
16
−75 −50 −25
0
25
50
75
100 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 26
Figure 27
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
1.5
1.4
1.3
1.2
1.1
1
10
9
8
7
6
5
4
3
2
1
0
A
= 1
V
V
= 10 V
DD
V
R
= 1 V
= 10 kΩ
= 20 pF
IPP
L
L
V
= 10 V
DD
C
T
T
A
T
A
= 125°C
= 25°C
= −55°C
A
V
DD
= 5 V
V
R
= 5 V
DD
0.9
0.8
0.7
0.6
0.5
= 10 kΩ
L
See Figure 1
10
100
1000
10000
−75 −50 −25
0
25
50
75
100 125
f − Frequency − kHz
T
A
− Free-Air Temperature − °C
Figure 28
Figure 29
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
26
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ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁ
ꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
UNITY-GAIN BANDWIDTH
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
3
2.5
2
2.5
V
= 5 V
V = 10 mV
I
DD
V = 10 mV
C
= 20 pF
I
C
L
T
A
= 25°C
= 20 pF
L
See Figure 3
See Figure 3
2
1.5
1.5
1
1
0
2
4
6
8
10
12
14
16
−75 −50 −25
0
25
50
75
100 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 30
Figure 31
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
10
V
= 5 V
= 10 kΩ
= 25°C
DD
106
R
L
T
A
5
10
0°
4
10
30°
60°
90°
A
VD
3
10
2
10
Phase Shift
10
1
120°
150°
180°
0.1
10
100
1 k
10 k 100 k
1 M
10 M
f − Frequency − Hz
Figure 32
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
27
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ꢏ
ꢁ
ꢋ
ꢌ
ꢂ
ꢍꢎ
ꢐꢑ ꢒ ꢂꢓ ꢏꢓ ꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒ ꢑꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐꢁ ꢓꢘ ꢓꢒ ꢑꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
†
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
6
5
4
3
2
10
10
10
10
10
10
V
R
= 10 V
= 10 kΩ
= 25°C
DD
L
T
A
0°
30°
60°
90°
120°
A
VD
Phase Shift
10
1
150°
180°
0.1
10
100
1 k
10 k 100 k
1 M
10 M
f − Frequency − Hz
Figure 33
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
53°
52°
50°
48°
46°
V
= 5 V
DD
V = 10 mV
I
C
= 20 pF
L
51°
50°
See Figure 3
49°
48°
47°
44°
42°
40°
V = 10 mV
I
C
= 20 pF
L
T
A
= 25°C
46°
45°
See Figure 3
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 34
Figure 35
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
28
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ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢈ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢉꢆ ꢀꢁ ꢂꢃ ꢄꢊ
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ꢁꢋ
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ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
400
300
200
100
0
50°
45°
40°
V
R
= 5 V
= 20 Ω
= 25°C
DD
S
V
= 5 V
DD
V = 10 mV
I
T
A
T
A
= 25°C
See Figure 2
See Figure 3
35°
30°
25°
10 20 30 40 50 60 70 80 90 100
0
1
10
100
1000
C
− Capacitive Load − pF
f − Frequency − Hz
L
Figure 36
Figure 37
29
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ꢏ
ꢁ
ꢋ
ꢌ
ꢂ
ꢍꢎ
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
single-supply operation
While the TLC274 and TLC279 perform well using dual power supplies (also called balanced or split supplies),
the design is optimized for single-supply operation. This design includes an input common-mode voltage range
that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage
range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for
TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC274 and TLC279 permits the use of very large resistive values to implement
the voltage divider, thus minimizing power consumption.
The TLC274 and TLC279 work well in conjunction with digital logic; however, when powering both linear devices
and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require R decoupling.
C
V
DD
R4
R1
R3
R1 + R3
V
= V
DD
REF
R2
R3
−
V
I
R4
R2
V
O
+ V
REF
+
V
O
= (V − V )
REF I
V
REF
C
0.01 µF
Figure 38. Inverting Amplifier With Voltage Reference
−
+
Power
Supply
Logic
Logic
Logic
V
O
(a) COMMON SUPPLY RAILS
−
+
Power
Supply
Logic
Logic
Logic
V
O
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common Versus Separate Supply Rails
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ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
input characteristics
The TLC274 and TLC279 are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially
in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at V
− 1 V at T = 25°C and at V
− 1.5 V at all other temperatures.
DD
A
DD
The use of the polysilicon-gate process and the careful input circuit design gives the TLC274 and TLC279 very
good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift
in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC274 and
TLC279 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC274 and TLC279 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
−
+
−
+
−
+
V
I
V
O
V
O
V
O
V
I
V
I
(a) NONINVERTING AMPLIFIER
(b) INVERTING AMPLIFIER
(c) UNITY-GAIN AMPLIFIER
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC274 and TLC279 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC274 and TLC279 were measured using a 20-pF load. The devices drive
higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at
lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many cases, adding
a small amount of resistance in series with the load capacitance alleviates the problem.
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ꢏ
ꢁ
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
output characteristics (continued)
(a) C = 20 pF, R = NO LOAD
(b) C = 130 pF, R = NO LOAD
L L
L
L
2.5 V
−
+
V
O
V
I
C
T = 25°C
A
L
f = 1 kHz
= 1 V
V
IPP
−2.5 V
(d) TEST CIRCUIT
(c) C = 150 pF, R = NO LOAD
L
L
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC274 and TLC279 possess excellent high-level output voltage and current capability, methods
for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor
(R ) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the
P
use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between
approximately 60 Ω and 180 Ω, depending on how hard the op amp input is driven. With very low values of R ,
P
a voltage offset from 0 V at the output occurs. Second, pullup resistor R acts as a drain load to N4 and the gain
P
of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current.
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ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁꢋ
ꢌ
ꢂ
ꢍ
ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
output characteristics (continued)
V
DD
C
R
V
I
P
+
I
I
P
−
V
O
−
F
V
O
+
R2
I
L
R
R1
L
V
− V
O
DD
+ I + I
P
Figure 43. Compensation for
Input Capacitance
Rp =
I
F
L
I
= Pullup current required
P
by the operational amplifier
(typically 500 µA)
Figure 42. Resistive Pullup to Increase V
OH
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic discharge protection
The TLC274 and TLC279 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents
functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be
exercised, however, when handling these devices as exposure to ESD may result in the degradation of the
device parametric performance. The protection circuit also causes the input bias currents to be
temperature-dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC274 and
TLC279 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
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ꢏ
ꢁ
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
10 kΩ
10 kΩ
0.016 µF
0.016 µF
10 kΩ
−
V
I
10 kΩ
−
1/4
TLC274
+
5 V
−
10 kΩ
1/4
TLC274
+
1/4
TLC274
+
Low Pass
HIgh Pass
Band Pass
5 kΩ
R = 5 kΩ (3/d−1)
(see Note A)
NOTE A: d = damping factor, 1/Q
Figure 44. State-Variable Filter
12 V
H.P.
5082-2835
V
I
+
1/4
+
TLC274
1/4
V
O
−
TLC274
0.5 µF
Mylar
−
N.O.
Reset
100 kΩ
Figure 45. Positive-Peak Detector
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ꢐꢑꢒ ꢂꢓꢏ ꢓꢎ ꢔ ꢕ ꢖꢇꢗ ꢎ ꢐꢒꢑ ꢇꢀ ꢓꢎ ꢔꢇꢁ ꢇꢍ ꢐ ꢁꢓ ꢘꢓ ꢒꢑ ꢏ
ꢁꢋ
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ꢎ
ꢏ
SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
V
I
(see Note A)
100 kΩ
0.47 µF
1.2 kΩ
20 kΩ
4.7 kΩ
0.1 µF
−
TL431
1/4
TLC274
+
1 kΩ
TIP31
15 Ω
TIS193
+
−
250 µF,
25 V
V
O
(see Note B)
10 kΩ
47 kΩ
0.01 µF
22 kΩ
110 Ω
NOTES: B. V = 3.5 V to 15 V
I
O
C.
V
= 2 V, 0 to 1 A
Figure 46. Logic-Array Power Supply
V
O
(see Note A)
9 V
0.1 µF
9 V
10 kΩ
10 kΩ
C
1/4
TLC274
100 kΩ
R2
−
1/4
TLC274
+
V
O
(see Note B)
100 kΩ
R1
1
R1
f
=
O
4C(R2) R2
47 kΩ
R3
NOTES: A.
B.
V
V
= 8 V
= 4 V
O(PP)
O(PP)
Figure 47. Single-Supply Function Generator
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ꢏ
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SLOS092D − SEPTEMBER 1987 − REVISED MARCH 2001
APPLICATION INFORMATION
5 V
V −
I
+
10 kΩ
100 kΩ
1/4
TLC279
−
−
1/4
TLC279
+
V
O
10 kΩ
−
R1, 10 kΩ
(see Note A)
10 kΩ
95 kΩ
1/4
TLC279
+
V +
I
−5 V
NOTE C: CMRR adjustment must be noninductive.
Figure 48. Low-Power Instrumentation Amplifier
5 V
−
1/4
TLC274
R
R
V
O
10 MΩ
10 MΩ
+
V
I
2C
540 pF
1
f
+
NOTCH
2pRC
R/2
5 MΩ
C
C
270 pF
270 pF
Figure 49. Single-Supply Twin-T Notch Filter
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC274ACD
TLC274ACDR
TLC274ACN
TLC274ACNE4
TLC274AID
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
N
N
D
D
N
D
D
D
N
N
NS
D
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
Call TI | NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
TLC274AC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2500
25
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
Call TI | NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TLC274AC
TLC274ACN
TLC274ACN
TLC274AI
Green (RoHS
& no Sb/Br)
0 to 70
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
0 to 70
TLC274AIDR
TLC274AIN
2500
25
Green (RoHS
& no Sb/Br)
TLC274AI
Green (RoHS
& no Sb/Br)
TLC274AIN
TLC274BC
TLC274BC
TLC274BC
TLC274BCN
TLC274BCN
TLC274B
TLC274BCD
TLC274BCDG4
TLC274BCDR
TLC274BCN
TLC274BCNE4
TLC274BCNS
TLC274BID
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
50
Green (RoHS
& no Sb/Br)
0 to 70
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
SOIC
SOIC
SOIC
50
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
TLC274BI
TLC274BIDG4
TLC274BIDR
50
Green (RoHS
& no Sb/Br)
TLC274BI
2500
Green (RoHS
& no Sb/Br)
TLC274BI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
25
(1)
(2)
(3)
(4/5)
(6)
TLC274BIDRG4
TLC274BIN
ACTIVE
SOIC
PDIP
SOIC
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
TLC274BI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TLC274BIN
TLC274C
P274
TLC274CD
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC274CDB
TLC274CDBG4
TLC274CDBR
TLC274CDG4
TLC274CDR
TLC274CDRG4
TLC274CN
DB
DB
DB
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
P274
2000
50
Green (RoHS
& no Sb/Br)
P274
Green (RoHS
& no Sb/Br)
TLC274C
TLC274C
TLC274C
TLC274CN
TLC274CN
TLC274
TLC274
P274
D
2500
2500
25
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TLC274CNE4
TLC274CNS
TLC274CNSR
TLC274CPW
TLC274CPWR
TLC274CPWRG4
TLC274ID
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
NS
NS
PW
PW
PW
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SO
2000
90
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
SOIC
Green (RoHS
& no Sb/Br)
2000
2000
50
Green (RoHS
& no Sb/Br)
P274
Green (RoHS
& no Sb/Br)
P274
Green (RoHS
& no Sb/Br)
TLC274I
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC274IDG4
TLC274IDR
TLC274IN
ACTIVE
SOIC
SOIC
PDIP
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
-55 to 125
0 to 70
TLC274I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2500
25
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TLC274I
TLC274IN
TLC274IN
P274
N
Green (RoHS
& no Sb/Br)
TLC274INE4
TLC274IPW
TLC274IPWR
TLC274IPWRG4
TLC274MD
PDIP
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PW
PW
PW
D
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2000
2000
50
Green (RoHS
& no Sb/Br)
Y274
Green (RoHS
& no Sb/Br)
Y274
Green (RoHS
& no Sb/Br)
TLC274M
TLC274M
TLC274M
TLC279C
TLC279C
TLC279C
TLC279CN
TLC279I
TLC279I
TLC279IN
TLC274MDG4
TLC274MDRG4
TLC279CD
D
50
Green (RoHS
& no Sb/Br)
D
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
TLC279CDG4
TLC279CDR
TLC279CN
D
50
Green (RoHS
& no Sb/Br)
0 to 70
D
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
N
Green (RoHS
& no Sb/Br)
0 to 70
TLC279ID
SOIC
SOIC
PDIP
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
TLC279IDR
TLC279IN
D
2500
25
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Apr-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC274ACDR
TLC274AIDR
TLC274CDBR
TLC274CDR
TLC274CDR
TLC274CNSR
TLC274CPWR
TLC274IPWR
TLC274MDRG4
TLC279CDR
TLC279IDR
SOIC
SOIC
SSOP
SOIC
SOIC
SO
D
D
14
14
14
14
14
14
14
14
14
14
14
2500
2500
2000
2500
2500
2000
2000
2000
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
12.4
12.4
16.4
16.4
16.4
6.5
6.5
8.35
6.5
6.5
8.2
6.9
6.9
6.5
6.5
6.5
9.0
9.0
6.6
9.0
9.0
10.5
5.6
5.6
9.0
9.0
9.0
2.1
2.1
2.5
2.1
2.1
2.5
1.6
1.6
2.1
2.1
2.1
8.0
8.0
12.0
8.0
8.0
12.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
DB
D
D
NS
PW
PW
D
TSSOP
TSSOP
SOIC
SOIC
SOIC
D
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Apr-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC274ACDR
TLC274AIDR
TLC274CDBR
TLC274CDR
TLC274CDR
TLC274CNSR
TLC274CPWR
TLC274IPWR
TLC274MDRG4
TLC279CDR
TLC279IDR
SOIC
SOIC
SSOP
SOIC
SOIC
SO
D
D
14
14
14
14
14
14
14
14
14
14
14
2500
2500
2000
2500
2500
2000
2000
2000
2500
2500
2500
350.0
350.0
367.0
350.0
333.2
367.0
367.0
367.0
350.0
350.0
350.0
350.0
350.0
367.0
350.0
345.9
367.0
367.0
367.0
350.0
350.0
350.0
43.0
43.0
38.0
43.0
28.6
38.0
35.0
35.0
43.0
43.0
43.0
DB
D
D
NS
PW
PW
D
TSSOP
TSSOP
SOIC
SOIC
SOIC
D
D
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2020, Texas Instruments Incorporated
相关型号：
TLC277CJG
DUAL OP-AMP, 1900uV OFFSET-MAX, 2.2MHz BAND WIDTH, CDIP8, 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-8
TI
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