TLC27M2BCDG4 [TI]

LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS; ?????????路LinCMOS精密双运算放大器


型号：	TLC27M2BCDG4
厂家：	TEXAS INSTRUMENTS
描述：	LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS ?????????路LinCMOS精密双运算放大器运算放大器
文件：	总50页 (文件大小：1503K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

Trimmed Offset Voltage:

TLC27M7 . . . 500 µV Max at 25°C,

= 5 V

Low Noise . . . Typically 32 nV/√Hz at

f = 1 kHz

Low Power . . . Typically 2.1 mW at 25°C,

Input Offset Voltage Drift . . . Typically

0.1 µV/Month, Including the First 30 Days

Wide Range of Supply Voltages Over

Specified Temperature Ranges:

0°C to 70°C . . . 3 V to 16 V

−40°C to 85°C . . . 4 V to 16 V

−55°C to 125°C . . . 4 V to 16 V

Single-Supply Operation

= 5 V

Output Voltage Range Includes Negative

Rail

High Input impedance . . . 10 Ω Typ

ESD-Protection Circuitry

Small-Outline Package Option Also

Available in Tape and Reel

Designed-In Latch-Up Immunity

Common-Mode Input Voltage Range

Extends Below the Negative Rail (C-Suffix,

I-Suffix Types)

DISTRIBUTION OF TLC27M7

INPUT OFFSET VOLTAGE

D, JG, P OR PW PACKAGE

(TOP VIEW)

FK PACKAGE

(TOP VIEW)

340 Units Tested From 2 Wafer Lots

1OUT

1IN −

1IN +

GND

= 5 V

= 25°C

2OUT

2IN −

2IN +

P Package

20 19

1IN −

2OUT

2IN −

1IN +

9 10 11 12 13

−800

−400

400

800

NC − No internal connection

− Input Offset Voltage − µV

AVAILABLE OPTIONS

PACKAGE

max

SMALL OUTLINE

CHIP CARRIER

(FK)

CERAMIC DIP

(JG)

PLASTIC DIP

(P)

TSSOP

(PW)

AT 25°C

(D)

500 µV

2 mV

TLC27M7CD

TLC27M2BCD

TLC27M2ACD

TLC27M2CD

TLC27M7ID

TLC27M2BID

TLC27M2AID

TLC27M2ID

TLC27M7MD

TLC27M2MD

—

TLC27M7CP

TLC27M2BCP

TLC27M2ACP

TLC27M2CP

TLC27M7IP

—

0°C to 70°C

5 mV

—

10 mV

500 µV

2 mV

—

TLC27M2CPW

—

TLC27M2BIP

TLC27M2AIP

TLC27M2IP

—

−40°C to 85°C

−55°C to 125°C

5 mV

—

10 mV

500 µV

10 mV

—

TLC27M2IPW

TLC27M7MFK

TLC27M2MFK

TLC27M7MJG

TLC27M2MJG

TLC27M7MP

TLC27M2MP

—

The D and PW package are available taped and reeled. Add R suffix to the device type (e.g.,TLC27M7CDR). For the most current package and

ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

LinCMOS is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

description

The TLC27M2 and TLC27M7 dual operational amplifiers combine a wide range of input offset voltage grades

with low offset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose

bipolar devices.These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset

voltage stability far exceeding the stability available with conventional metal-gate processes.

The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices

ideal for applications which have previously been reserved for general-purpose bipolar products, but with only

a fraction of the power consumption. Four offset voltage grades are available (C-suffix and I-suffix types),

ranging from the low-cost TLC27M2 (10 mV) to the high-precision TLC27M7 (500 µV). These advantages, in

combination with good common-mode rejection and supply voltage rejection, make these devices a good

choice for new state-of-the-art designs as well as for upgrading existing designs.

In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers,

without the power penalties of bipolar technology. General applications such as transducer interfacing, analog

calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M2 and

TLC27M7. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote

and inaccessible battery-powered applications. The common-mode input voltage range includes the negative

rail.

A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density

system applications.

The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.

The TLC27M2 and TLC27M7 incorporate internal ESD-protection circuits that prevent functional failures at

voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in

handling these devices as exposure to ESD may result in the degradation of the device parametric performance.

The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized

for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military

temperature range of −55°C to 125°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

equivalent schematic (each amplifier)

IN −

IN +

OUT

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V

Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Total current into V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA

Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA

Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited

Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.

2. Differential voltages are at IN+ with respect to IN−.

3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum

dissipation rating is not exceeded (see application section).

DISSIPATION RATING TABLE

≤ 25°C

DERATING FACTOR

= 70°C

= 85°C

T = 125°C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING POWER RATING

725 mW

5.8 mW/°C

11.0 mW/°C

8.4 mW/°C

8.0 mW/°C

464 mW

880 mW

672 mW

640 mW

377 mW

715 mW

546 mW

520 mW

1375 mW

275 mW

210 mW

1050 mW

1000 mW

recommended operating conditions

C SUFFIX

I SUFFIX

M SUFFIX

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Supply voltage, V

3.5

8.5

125

= 5 V

−0.2

3.5

8.5

−0.2

−40

3.5

8.5

Common-mode input voltage, V

= 10 V

Operating free-air temperature, T

−55

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

electrical characteristics at specified free-air temperature, V

= 5 V (unless otherwise noted)

TLC27M2C

TLC27M2AC

TLC27M2BC

TLC27M7C

PARAMETER

TEST CONDITIONS

UNIT

†

MIN

TYP

MAX

25°C

Full range

25°C

1.1

= 1.4 V,

= 50 Ω,

= 0,

R = 100 kΩ

TLC27M2C

TLC27M2AC

TLC27M2BC

TLC27M7C

0.9

220

185

= 1.4 V,

= 50 Ω,

= 0,

R = 100 kΩ

Full range

25°C

6.5

Input offset voltage

2000

3000

500

1500

= 1.4 V,

= 50 Ω,

= 0,

R = 100 kΩ

Full range

25°C

µV

= 1.4 V,

= 50 Ω,

= 0,

R = 100 kΩ

Full range

Average temperature coefficient of input

offset voltage

25°C to

70°C

1.7

µV/°C

VIO

25°C

70°C

25°C

70°C

0.1

300

Input offset current (see Note 4)

Input bias current (see Note 4)

= 2.5 V,

= 2.5 V

0.6

600

−0.2

−0.3

4.2

25°C

Common-mode input voltage range

(see Note 5)

ICR

−0.2

Full range

3.5

25°C

0°C

3.2

3.9

High-level output voltage

Low-level output voltage

= 100 mV,

= 100 kΩ

= 0

V/mV

70°C

25°C

0°C

= −100 mV,

= 0.25 V to 2 V,

70°C

25°C

0°C

170

200

140

210

250

170

Large-signal differential voltage

amplification

= 100 kΩ

70°C

25°C

0°C

CMRR

Common-mode rejection ratio

Supply-voltage rejection ratio

= V min

ICR

70°C

25°C

0°C

= 5 V to 10 V,

= 1.4 V

SVR

(∆V

/∆V )

70°C

25°C

0°C

560

640

440

= 2.5 V,

Supply current (two amplifiers)

µA

No load

70°C

†

Full range is 0°C to 70°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

electrical characteristics at specified free-air temperature, V

= 10 V (unless otherwise noted)

TLC27M2C

TLC27M2AC

†

TLC27M2BC

TLC27M7C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

25°C

Full range

25°C

1.1

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

TLC27M2C

TLC27M2AC

TLC27M2BC

TLC27M7C

0.9

224

190

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

25°C

6.5

Input offset voltage

2000

3000

800

1900

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

25°C

µV

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

Average temperature coefficient of input

offset voltage

25°C to

70°C

2.1

µV/°C

VIO

25°C

70°C

25°C

70°C

0.1

300

Input offset current (see Note 4)

Input bias current (see Note 4)

= 5 V,

= 5 V

0.7

600

−0.2

−0.3

9.2

25°C

Common-mode input voltage range

(see Note 5)

ICR

−0.2

Full range

8.5

25°C

0°C

7.8

8.7

High-level output voltage

Low-level output voltage

= 100 mV,

= −100 mV,

= 1 V to 6 V,

= 100 kΩ

= 0

V/mV

70°C

25°C

0°C

70°C

25°C

0°C

275

320

230

Large-signal differential voltage

amplification

= 100 kΩ

70°C

25°C

0°C

CMRR

Common-mode rejection ratio

Supply-voltage rejection ratio

= V min

ICR

70°C

25°C

0°C

= 5 V to 10 V,

= 1.4 V

SVR

(∆V

/∆V )

70°C

25°C

0°C

285

345

220

600

800

560

= 5 V,

Supply current (two amplifiers)

µA

No load

70°C

†

Full range is 0°C to 70°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

ꢁꢉ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

electrical characteristics at specified free-air temperature, V

= 5 V (unless otherwise noted)

TLC27M2I

TLC27M2AI

†

TLC27M2BI

TLC27M7I

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

25°C

Full range

25°C

1.1

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

TLC27M2I

TLC27M2AI

TLC27M2BI

TLC27M7I

0.9

220

185

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

25°C

Input offset voltage

2000

3500

500

2000

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

25°C

µV

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

Average temperature coefficient of input

offset voltage

25°C to

85°C

1.7

µV/°C

VIO

25°C

85°C

25°C

85°C

0.1

1000

Input offset current (see Note 4)

Input bias current (see Note 4)

= 2.5 V,

= 2.5 V

0.6

200

2000

−0.2

−0.3

4.2

25°C

Common-mode input voltage range

(see Note 5)

ICR

−0.2

Full range

3.5

25°C

−40°C

85°C

3.2

3.9

High-level output voltage

Low-level output voltage

= 100 mV,

= 100 kΩ

= 0

V/mV

25°C

−40°C

85°C

= −100 mV,

= 0.25 V to 2 V,

25°C

170

270

130

210

315

160

Large-signal differential voltage

amplification

−40°C

85°C

= 100 kΩ

25°C

−40°C

85°C

CMRR

Common-mode rejection ratio

Supply-voltage rejection ratio

= V min

ICR

25°C

−40°C

85°C

= 5 V to 10 V,

= 1.4 V

SVR

(∆V

/∆V )

25°C

560

800

400

= 2.5 V,

Supply current (two amplifiers)

−40°C

85°C

µA

No load

†

Full range is −40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋ

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ꢊ

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ꢍ

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ꢏ

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ꢐ

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ꢓ

ꢇ

ꢁ

ꢋ

ꢍꢏ

ꢎ

ꢇꢀ

ꢐ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

electrical characteristics at specified free-air temperature, V

= 10 V (unless otherwise noted)

TLC27M2I

TLC27M2AI

†

TLC27M2BI

TLC27M7I

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

25°C

Full range

25°C

1.1

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

TLC27M2I

TLC27M2AI

TLC27M2BI

TLC27M7I

0.9

224

190

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

25°C

Input offset voltage

2000

3500

800

2900

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

25°C

µV

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

Average temperature coefficient of input

offset voltage

25°C to

85°C

VIO

2.1

µV/°C

25°C

85°C

25°C

0.1

1000

Input offset current (see Note 4)

Input bias current (see Note 4)

= 5 V,

= 5 V

0.7

200

85°C

220

−0.2

−0.3

9.2

25°C

Common-mode input voltage range

(see Note 5)

ICR

−0.2

Full range

8.5

25°C

−40°C

85°C

7.8

8.7

High-level output voltage

Low-level output voltage

= 100 mV,

= −100 mV,

= 1 V to 6 V,

= 100 kΩ

= 0

V/mV

25°C

−40°C

85°C

25°C

275

390

220

Large-signal differential voltage

amplification

−40°C

85°C

= 100 kΩ

25°C

−40°C

85°C

CMRR Common-mode rejection ratio

Supply-voltage rejection ratio

= V min

ICR

25°C

−40°C

85°C

= 5 V to 10 V,

= 1.4 V

SVR

(∆V

/∆V )

25°C

285

450

205

600

900

520

= 5 V,

Supply current

−40°C

85°C

µA

No load

†

Full range is −40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

electrical characteristics at specified free-air temperature, V

= 5 V (unless otherwise noted)

TLC27M2M

TLC27M7M

†

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

25°C

Full range

25°C

1.1

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

TLC27M2M

TLC27M7M

Input offset voltage

185

500

3750

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

Average temperature coefficient of input

offset voltage

25°C to

125°C

VIO

1.7

µV/°C

25°C

125°C

25°C

0.1

1.4

0.6

Input offset current (see Note 4)

Input bias current (see Note 4)

= 2.5 V,

= 2.5 V

125°C

−0.3

4.2

25°C

Common-mode input voltage range

(see Note 5)

ICR

Full range

3.5

25°C

−55°C

125°C

25°C

3.2

3.9

High-level output voltage

Low-level output voltage

= 100 mV,

= 100 kΩ

= 0

V/mV

−55°C

125°C

25°C

= −100 mV,

= 0.25 V to 2 V,

170

290

120

210

340

140

Large-signal differential voltage

amplification

−55°C

125°C

25°C

= 100 kΩ

−55°C

125°C

25°C

CMRR

Common-mode rejection ratio

Supply-voltage rejection ratio

= V min

ICR

−55°C

125°C

25°C

= 5 V to 10 V,

= 1.4 V

SVR

(∆V

/∆V )

560

880

360

= 2.5 V,

Supply current (two amplifiers)

−55°C

125°C

µA

No load

†

Full range is −55°C to 125°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢂ

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ꢍ

ꢎ

ꢏ

ꢂ

ꢐꢌ

ꢐ

ꢋꢑ

ꢒ

ꢓ

ꢇ

ꢁ

ꢋ

ꢍꢏ

ꢎ

ꢇꢀ

ꢐ

ꢑ

ꢇ

ꢁ

ꢇ

ꢅ

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ꢐ

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ꢐ

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ꢌ

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

electrical characteristics at specified free-air temperature, V

= 10 V (unless otherwise noted)

TLC27M2M

TLC27M7M

†

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

25°C

Full range

25°C

1.1

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

TLC27M2M

TLC27M7M

Input offset voltage

190

800

4300

= 1.4 V,

= 50 Ω,

= 0,

= 100 kΩ

Full range

Average temperature coefficient of input

offset voltage

25°C to

125°C

2.1

µV/°C

VIO

25°C

125°C

25°C

0.1

1.8

0.7

Input offset current (see Note 4)

Input bias current (see Note 4)

= 5 V,

= 5 V

125°C

−0.3

9.2

25°C

Common-mode input voltage range

(see Note 5)

ICR

Full range

8.5

25°C

−55°C

125°C

25°C

7.8

8.7

8.6

8.8

High-level output voltage

Low-level output voltage

= 100 mV,

= −100 mV,

= 1 V to 6 V,

= 100 kΩ

= 0

V/mV

−55°C

125°C

25°C

275

420

190

Large-signal differential voltage

amplification

−55°C

125°C

25°C

= 100 kΩ

−55°C

125°C

25°C

CMRR Common-mode rejection ratio

Supply-voltage rejection ratio

= V min

ICR

−55°C

125°C

25°C

= 5 V to 10 V,

= 1.4 V

SVR

(∆V

/∆V )

285

490

180

600

1000

480

= 5 V,

Supply current (two amplifiers)

−55°C

125°C

µA

No load

†

Full range is −55°C to 125°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.

5. This range also applies to each input individually.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

operating characteristics at specified free-air temperature, V

= 5 V

TLC27M2C

TLC27M2AC

TLC27M2BC

TLC27M7C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

0.43

0.46

0.36

0.40

0.43

0.34

MAX

25°C

0°C

= 1 V

I(PP)

= 100 kΩ,

= 20 pF,

70°C

25°C

0°C

Slew rate at unity gain

V/µs

See Figure 1

= 2.5 V

I(PP)

70°C

f = 1 kHz,

See Figure 2

= 20 Ω,

Equivalent input noise voltage

25°C

nV/√Hz

25°C

0°C

= V

= 100 kΩ,

= 20 pF,

kHz

Maximum output-swing bandwidth

See Figure 1

70°C

25°C

0°C

525

600

400

40°

41°

39°

V = 10 mV,

See Figure 3

C = 20 pF,

kHz

Unity-gain bandwidth

Phase margin

70°C

25°C

0°C

V = 10 mV,

f = B ,

See Figure 3

= 20 pF,

70°C

operating characteristics at specified free-air temperature, V

= 10 V

TLC27M2C

TLC27M2AC

TLC27M2BC

TLC27M7C

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

0.62

0.67

0.51

0.56

0.61

0.46

MAX

25°C

0°C

= 1 V

I(PP)

= 100 kΩ,

70°C

25°C

0°C

= 20 pF,

Slew rate at unity gain

V/µs

See Figure 1

= 5.5 V

I(PP)

70°C

f = 1 kHz,

See Figure 2

= 20 Ω,

Equivalent input noise voltage

25°C

nV/√Hz

25°C

0°C

= V

= 100 kΩ,

= 20 pF,

Maximum output-swing bandwidth

kHz

See Figure 1

70°C

25°C

0°C

635

710

510

43°

44°

42°

V = 10 mV,

See Figure 3

C = 20 pF,

Unity-gain bandwidth

Phase margin

kHz

70°C

25°C

0°C

V = 10 mV,

f = B ,

See Figure 3

= 20 pF,

70°C

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ꢅꢋ

ꢍꢎ ꢏꢂ ꢐꢌ ꢐ ꢋꢑ ꢒꢓ ꢇꢁ ꢋ ꢍꢏ ꢎꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍꢁ ꢐꢔ ꢐꢏ ꢎꢌ

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

operating characteristics at specified free-air temperature, V

= 5 V

TLC27M2I

TLC27M2AI

TLC27M2BI

TLC27M7I

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

0.43

0.51

0.35

0.40

0.48

0.32

MAX

25°C

−40°C

85°C

= 1 V

I(PP)

= 100 kΩ,

= 20 pF,

Slew rate at unity gain

V/µs

25°C

See Figure 1

−40°C

85°C

= 2.5 V

I(PP)

f = 1 kHz,

See Figure 2

= 20 Ω,

Equivalent input noise voltage

25°C

nV/√Hz

25°C

−40°C

85°C

= V

= 100 kΩ,

= 20 pF,

Maximum output-swing bandwidth

kHz

See Figure 1

25°C

525

770

370

40°

43°

38°

V = 10 mV,

See Figure 3

C = 20 pF,

−40°C

85°C

Unity-gain bandwidth

Phase margin

kHz

25°C

V = 10 mV,

f = B ,

See Figure 3

−40°C

85°C

= 20 pF,

operating characteristics at specified free-air temperature, V

= 10 V

TLC27M2I

TLC27M2AI

TLC27M2BI

TLC27M7I

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

0.62

0.77

0.47

0.56

0.70

0.44

MAX

25°C

−40°C

85°C

= 1 V

I(PP)

= 100 kΩ,

= 20 pF,

Slew rate at unity gain

V/µs

25°C

See Figure 1

−40°C

85°C

= 5.5 V

I(PP)

f = 1 kHz,

See Figure 2

= 20 Ω,

Equivalent input noise voltage

25°C

nV/√Hz

25°C

−40°C

85°C

= V

= 100 kΩ,

= 20 pF,

Maximum output-swing bandwidth

kHz

See Figure 1

25°C

635

880

480

43°

46°

41°

V = 10 mV,

See Figure 3

C = 20 pF,

−40°C

85°C

Unity-gain bandwidth

Phase margin

kHz

25°C

V = 10 mV,

f = B ,

See Figure 3

−40°C

85°C

= 20 pF,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

operating characteristics at specified free-air temperature, V

= 5 V

TLC27M2M

TLC27M7M

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

0.43

0.54

0.29

0.40

0.49

0.28

MAX

25°C

−55°C

125°C

25°C

= 1 V

I(PP)

= 100 kΩ,

= 20 pF,

Slew rate at unity gain

V/µs

See Figure 1

−55°C

125°C

= 2.5 V

f = 1 kHz,

See Figure 2

= 20 Ω,

Equivalent input noise voltage

25°C

nV/√Hz

25°C

−55°C

125°C

25°C

= V

= 20 pF,

Maximum output-swing bandwidth

kHz

= 100 kΩ, See Figure 1

525

850

330

40°

44°

36°

V = 10 mV,

See Figure 3

C = 20 pF,

−55°C

125°C

25°C

Unity-gain bandwidth

Phase margin

kHz

V = 10 mV,

f = B ,

See Figure 3

−55°C

125°C

= 20 pF,

operating characteristics at specified free-air temperature, V

= 10 V

TLC27M2M

TLC27M7M

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

0.62

0.81

0.38

0.56

0.73

0.35

MAX

25°C

−55°C

125°C

25°C

= 1 V

I(PP)

= 100 kΩ,

= 20 pF,

Slew rate at unity gain

V/µs

See Figure 1

−55°C

125°C

= 5.5 V

f = 1 kHz,

See Figure 2

= 20 Ω,

Equivalent input noise voltage

25°C

nV/√Hz

25°C

−55°C

125°C

25°C

= V

= 20 pF,

Maximum output-swing bandwidth

kHz

= 100 kΩ, See Figure 1

635

960

440

43°

47°

39°

V = 10 mV,

See Figure 3

C = 20 pF,

−55°C

125°C

25°C

Unity gain bandwidth

Phase margin

kHz

V = 10 mV,

f = B ,

See Figure 3

−55°C

125°C

= 20 pF,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits

Because the TLC27M2 and TLC27M7 are optimized for single-supply operation, circuit configurations used for

the various tests often present some inconvenience since the input signal, in many cases, must be offset from

ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to

the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either

circuit gives the same result.

−

(a) SINGLE SUPPLY

(b) SPLIT SUPPLY

Figure 1. Unity-Gain Amplifier

2 kΩ

20 Ω

−

1/2 V

20 Ω

−

(a) SINGLE SUPPLY

(b) SPLIT SUPPLY

Figure 2. Noise-Test Circuit

10 kΩ

100 Ω

−

1/2 V

−

(a) SINGLE SUPPLY

(b) SPLIT SUPPLY

Figure 3. Gain-of-100 Inverting Amplifier

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

PARAMETER MEASUREMENT INFORMATION

input bias current

Because of the high input impedance of the TLC27M2 and TLC27M7 operational amplifiers, attempts to

measure the input bias current can result in erroneous readings. The bias current at normal room ambient

temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two

suggestions are offered to avoid erroneous measurements:

1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the

device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.

2. Compensate for the leakage of the test socket by actually performing an input bias current test (using

a picoammeter) with no device in the test socket. The actual input bias current can then be calculated

by subtracting the open-socket leakage readings from the readings obtained with a device in the test

socket.

One word of caution—many automatic testers as well as some bench-top operational amplifier testers

use the servo-loop technique with a resistor in series with the device input to measure the input bias

current (the voltage drop across the series resistor is measured and the bias current is calculated). This

method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an

open-socket reading is not feasible using this method.

V = V

Figure 4. Isolation Metal Around Device Inputs (JG and P packages)

low-level output voltage

To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise

results in the device low-level output being dependent on both the common-mode input voltage level as well

as the differential input voltage level. When attempting to correlate low-level output readings with those quoted

in the electrical specifications, these two conditions should be observed. If conditions other than these are to

be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.

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ꢇ

ꢀ

ꢐ

ꢋ

ꢑ

ꢇ

ꢁ

ꢇ

ꢅ

ꢍ

ꢁ

ꢐ

ꢔ

ꢐ

ꢏ

ꢎ

ꢌ

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

PARAMETER MEASUREMENT INFORMATION

input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This

parameter is actually a calculation using input offset voltage measurements obtained at two different

temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device

and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input

offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage, since

the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these

measurements be performed at temperatures above freezing to minimize error.

full-power response

Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage

swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is

generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal

input signal until the maximum frequency is found above which the output contains significant distortion. The

full-peak response is defined as the maximum output frequency, without regard to distortion, above which full

peak-to-peak output swing cannot be maintained.

Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified

in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal

input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is

increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same

amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained

(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum

peak-to-peak output is reached.

(a) f = 1 kHz

(b) B

> f > 1 kHz

(d) f > B

Figure 5. Full-Power-Response Output Signal

test time

Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,

short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET

devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more

pronounced with reduced supply levels and lower temperatures.

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

6, 7

Input offset voltage

Distribution

Temperature coefficient

Distribution

8, 9

VIO

vs High-level output current

vs Supply voltage

vs Free-air temperature

10, 11

High-level output voltage

vs Common-mode input voltage

vs Differential input voltage

vs Free-air temperature

14, 15

Low-level output voltage

vs Low-level output current

18, 19

vs Supply voltage

vs Free-air temperature

vs Frequency

32, 33

Differential voltage amplification

Input bias and input offset current

Common-mode input voltage

vs Free-air temperature

vs Supply voltage

IB IO

vs Supply voltage

vs Free-air temperature

Supply current

Slew rate

vs Supply voltage

vs Free-air temperature

Normalized slew rate

vs Free-air temperature

vs Frequency

Maximum peak-to-peak output voltage

O(PP)

vs Free-air temperature

vs Supply voltage

Unity-gain bandwidth

Phase margin

vs Supply voltage

vs Free-air temperature

vs Capacitive loads

Equivalent input noise voltage

Phase shift

vs Frequency

32, 33

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS

DISTRIBUTION OF TLC27M2

INPUT OFFSET VOLTAGE

DISTRIBUTION OF TLC27M2

INPUT OFFSET VOLTAGE

612 Amplifiers Tested From 4 Wafer Lots

= 5 V

= 25°C

= 10 V

= 25°C

P Package

−5 −4 −3 −2 −1

− Input Offset Voltage − mV

Figure 6

Figure 7

DISTRIBUTION OF TLC27M2 AND TLC27M7

INPUT OFFSET VOLTAGE

DISTRIBUTION OF TLC27M2 AND TLC27M7

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

224 Amplifiers Tested From 6 Wafer Lots

= 5 V

= 10 V

= 25°C to 125°C

P Package

Outliers:

(1) 33.0 µV/°C

P Package

Outliers:

(1) 34.6 µV/°C

−10 −8 −6 −4 −2

− Temperature Coefficient − µV/°C

VIO

Figure 8

Figure 9

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

†

TYPICAL CHARACTERISTICS

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

= 100 mV

= 25°C

= 100 mV

= 25°C

= 16 V

= 5 V

= 4 V

= 10 V

= 3 V

−2

−4

−6

−8

−10

−20

−30

−40

− High-Level Output Current − mA

Figure 10

Figure 11

HIGH-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

−1.6

−1.7

−1.8

−1.9

−2

= 100 mV

= −5 mA

= 100 kΩ

= 25°C

= 100 mA

= 5 V

= 10 V

−2.1

−2.2

−2.3

−2.4

−75 −50 −25

100 125

− Free-Air Temperature − °C

− Supply Voltage − V

Figure 12

Figure 13

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

†

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE

COMMON-MODE INPUT VOLTAGE

700

500

450

400

350

300

250

= 5 V

= 5 mA

= 25°C

= 10 V

650

600

= 5 mA

= 25°C

550

500

450

400

= −100 mV

= −1 V

= −2.5 V

= −1 V

350

300

− Common-Mode Input Voltage − V

Figure 14

Figure 15

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

DIFFERENTIAL INPUT VOLTAGE

900

800

700

600

500

400

300

200

100

800

700

600

500

400

300

200

100

= 5 mA

= −1 V

= 0.5 V

= 5 mA

= |V /2|

= 25°C

= 5 V

= 10 V

−75 −50 −25

100 125

−1 −2 −3 −4 −5 −6 −7 −8 −9 −10

− Free-Air Temperature − °C

− Differential Input Voltage − V

Figure 16

Figure 17

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

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TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

2.5

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

= −1 V

= 0.5 V

= 25°C

= −1 V

= 0.5 V

= 16 V

= 25°C

= 5 V

= 4 V

= 10 V

= 3 V

1.5

0.5

− Low-Level Output Current − mA

Figure 18

Figure 19

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

500

450

400

350

300

250

200

150

100

500

450

400

350

300

250

200

150

100

= −55°C

−40°C

= 100 kΩ

0°C

= 10 V

25°C

70°C

85°C

125°C

= 5 V

−75 −50 −25

100 125

− Free-Air Temperature − °C

− Supply Voltage − V

Figure 20

Figure 21

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

†

TYPICAL CHARACTERISTICS

COMMON-MODE

INPUT BIAS CURRENT AND INPUT OFFSET

INPUT VOLTAGE POSITIVE LIMIT

CURRENT

SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

10000

1000

100

= 10 V

T = 25°C

= 5 V

See Note A

0.1

105

125

− Supply Voltage − V

− Free-Air Temperature − °C

NOTE A: The typical values of input bias current and input offset

current below 5 pA were determined mathematically.

Figure 22

Figure 23

SUPPLY CURRENT

FREE-AIR TEMPERATURE

SUPPLY CURRENT

SUPPLY VOLTAGE

500

450

400

350

300

250

200

150

100

800

= V /2

= −55°C

700

600

500

400

300

200

100

No Load

−40°C

= 10 V

0°C

25°C

70°C

= 5 V

125°C

−75 −50 −25

100 125

− Free-Air Temperature − °C

− Supply Voltage − V

Figure 24

Figure 25

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

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TYPICAL CHARACTERISTICS

SLEW RATE

SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

= 1

= 1 V

= 100 kΩ

= 20 pF

= 1

= 100 kΩ

= 20 pF

IPP

= 10 V

= 5.5 V

I(PP)

See Figure 1

= 25°C

See Figure 1

= 10 V

= 1 V

I(PP)

= 5 V

I(PP)

= 1 V

= 5 V

= 2.5 V

I(PP)

− 75 − 50 − 25

100 125

− Supply Voltage − V

− Free-Air Temperature − °C

Figure 26

Figure 27

MAXIMUM PEAK-TO-PEAK OUTPUT

NORMALIZED SLEW RATE

VOLTAGE

FREE-AIR TEMPERATURE

FREQUENCY

1.4

1.3

1.2

1.1

= 1

= 1 V

I(PP)

= 10 V

= 100 kΩ

= 20 pF

= 10 V

= 5 V

= 125°C

= 25°C

= −55°C

0.9

0.8

0.7

0.6

0.5

= 5 V

= 100 kΩ

See Figure 1

−75 −50 −25

100 125

100

1000

− Free-Air Temperature − °C

f − Frequency − kHz

Figure 28

Figure 29

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

†

TYPICAL CHARACTERISTICS

UNITY-GAIN BANDWIDTH

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

900

800

700

600

500

400

300

800

750

700

650

600

550

500

450

400

V = 10 mV

= 5 V

V = 10 mV

= 20 pF

= 25°C

= 20 pF

See Figure 3

−75 −50 −25

100 125

− Free-Air Temperature − C

− Supply Voltage − V

Figure 30

Figure 31

LARGE-SCALE DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE SHIFT

FREQUENCY

= 5 V

= 100 kΩ

= 25°C

0°

30°

60°

90°

Phase Shift

120°

150°

180°

0.1

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

Figure 32

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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TYPICAL CHARACTERISTICS

LARGE-SCALE DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE SHIFT

FREQUENCY

= 10 V

= 100 kΩ

= 25°C

0°

30°

60°

90°

Phase Shift

120°

150°

180°

0.1

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

Figure 33

PHASE MARGIN

SUPPLY VOLTAGE

FREE-AIR TEMPERATURE

45°

43°

41°

39°

37°

35°

50°

48°

46°

44°

42°

40°

38°

= 5 V

V = 10 mV

= 20 pF

= 25°C

= 20 pF

See Figure 3

−75 −50 −25

100 125

− Free-Air Temperature − C

− Supply Voltage − V

Figure 34

Figure 35

†

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

TYPICAL CHARACTERISTICS

PHASE MARGIN

CAPACITIVE LOAD

44°

42°

40°

38°

36°

34°

32°

30°

= 5 V

V = 10 mV

= 25°C

See Figure 3

28°

10 20 30 40 50 60 70 80 90 100

− Capacitive Load − pF

Figure 36

EQUIVALENT INPUT NOISE VOLTAGE

FREQUENCY

300

250

200

150

100

= 5 V

= 20 Ω

= 25°C

See Figure 2

100

1000

f −Frequency − Hz

Figure 37

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APPLICATION INFORMATION

single-supply operation

While the TLC27M2 and TLC27M7 perform well using dual power supplies (also called balanced or split

supplies), the design is optimized for single-supply operation. This design includes an input common-mode

voltage range that encompasses ground, as well as an output voltage range that pulls down to ground. The

supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly

available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is

recommended.

Many single-supply applications require that a voltage be applied to one input to establish a reference level that

is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).

The low input bias current of the TLC27M2 and TLC27M7 permits the use of very large resistive values to

implement the voltage divider, thus minimizing power consumption.

The TLC27M2 and TLC27M7 work well in conjunction with digital logic; however, when powering both linear

devices and digital logic from the same power supply, the following precautions are recommended:

1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear

device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital

logic.

2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive

decoupling is often adequate; however, high-frequency applications may require RC decoupling.

)

+ V

REF

−

ǒ_VREF_–VǓ

)

REF

0.01µF

Figure 38. Inverting Amplifier With Voltage Reference

−

Power

Supply

Logic

Output

(a) COMMON SUPPLY RAILS

−

Power

Supply

Logic

Output

(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)

Figure 39. Common Versus Separate Supply Rails

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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

APPLICATION INFORMATION

input characteristics

The TLC27M2 and TLC27M7 are specified with a minimum and a maximum input voltage that, if exceeded at

either input, could cause the device to malfunction. Exceeding this specified range is a common problem,

especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper

range limit is specified at V

−1 V at T = 25°C and at V

−1.5 V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M2 and TLC27M7

very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage

drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus

dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)

alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.

The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of

operation.

Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M2 and

TLC27M7 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards

and sockets can easily exceed bias current requirements and cause a degradation in device performance. It

is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement

Information section). These guards should be driven from a low-impedance source at the same voltage level

as the common-mode input (see Figure 40).

The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.

noise performance

The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage

differential amplifier. The low input bias current requirements of the TLC27M2 and TLC27M7 result in a very

low noise current, which is insignificant in most applications. This feature makes the devices especially

favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices

exhibit greater noise currents.

−

(b) INVERTING AMPLIFIER

(a) NONINVERTING AMPLIFIER

Figure 40. Guard-Ring Schemes

output characteristics

The output stage of the TLC27M2 and TLC27M7 is designed to sink and source relatively high amounts of

current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current

capability can cause device damage under certain conditions. Output current capability increases with supply

voltage.

All operating characteristics of the TLC27M2 and TLC27M7 were measured using a 20-pF load. The devices

drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole

occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many

cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

ꢁꢉ

ꢊ

ꢂ

ꢅ

ꢋ

ꢌ 

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

APPLICATION INFORMATION

(a) C = 20 pF, R = NO LOAD

(b) C = 170 pF, R = NO LOAD

L L

2.5 V

−

= 25°C

f = 1 kHz

= 1 V

I(PP)

−2.5 V

(d) TEST CIRCUIT

Figure 41. Effect of Capacitive Loads and Test Circuit

output characteristics (continued)

Although the TLC27M2 and TLC27M7 possess excellent high-level output voltage and current capability,

methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup

resistor (R ) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages

to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a

comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance

between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With

very low values of R , a voltage offset from 0 V at the output occurs. Second, pullup resistor R acts as a drain

load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying

the output current.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ

ꢌ 

ꢁ

ꢉ

ꢊ

ꢂ

ꢅꢋ

ꢍꢎ ꢏꢂ ꢐꢌ ꢐ ꢋꢑ ꢒꢓ ꢇꢁ ꢋ ꢍꢏ ꢎꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍꢁ ꢐꢔ ꢐꢏ ꢎꢌ

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

APPLICATION INFORMATION

output characteristics (continued)

−

* V

) I ) I

= Pullup current required by the op-

erational amplifier (typically 500 µA)

Figure 43. Compensation for Input Capacitance

Figure 42. Resistive Pullup to Increase V

feedback

Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for

oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads

(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with

the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.

electrostatic-discharge protection

The TLC27M2 and TLC27M7 incorporate an internal electrostatic-discharge (ESD) protection circuit that

prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care

should be exercised, however, when handling these devices as exposure to ESD may result in the degradation

of the device parametric performance. The protection circuit also causes the input bias currents to be

temperature dependent and have the characteristics of a reverse-biased diode.

latch-up

Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M2 and

TLC27M7 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up;

however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection

diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply

voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.

Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the

supply rails as close to the device as possible.

The current path established if latch-up occurs is usually between the positive supply rail and ground and can

be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply

voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the

forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of

latch-up occurring increases with increasing temperature and supply voltages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

ꢁꢉ

ꢊ

ꢂ

ꢅ

ꢋ

ꢌ 

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

APPLICATION INFORMATION

1N4148

470 kΩ

100 kΩ

5 V

1/2

TLC27M2

−

5 V

1/2

TLC27M7

47 kΩ

100 kΩ

−

2N3821

68 kΩ

100 kΩ

1 µF

2.2 nF

68 kΩ

2.2 nF

NOTES: V

≈ 2 V

NOTES: V = 0 V to 3 V

O(PP)

V_I

2p R1R2C1C2

Figure 45. Precision Low-Current Sink

Figure 44. Wien Oscillator

5 V

Gain Control

1 MΩ

100 kΩ

(see Note A)

1µ F

−

10 kΩ

1 kΩ

−

1/2

TLC27M2

−

0.1 µF

100 kΩ

0.1 µF

100 kΩ

NOTE A: Low to medium impedance dynamic mike

Figure 46. Microphone Preamplifier

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ

ꢌ 

ꢁ

ꢉ

ꢊ

ꢂ

ꢅꢋ

ꢍꢎ ꢏꢂ ꢐꢌ ꢐ ꢋꢑ ꢒꢓ ꢇꢁ ꢋ ꢍꢏ ꢎꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍꢁ ꢐꢔ ꢐꢏ ꢎꢌ

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

APPLICATION INFORMATION

10 MΩ

−

1/2

TLC27M2

1 kΩ

−

1/2

TLC27M2

15 nF

REF

100 kΩ

150 pF

NOTES: V

= 4 V to 15 V

ref

= 0 V to V − 2 V

Figure 47. Photo-Diode Amplifier With Ambient Light Rejection

1 MΩ

33 pF

−

1/2

TLC27M2

1N4148

100 kΩ

NOTES: V

= 8 V to 16 V

= 5 V, 10 mA

Figure 48. 5-V Low-Power Voltage Regulator

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ

ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ

ꢁꢉ

ꢊ

ꢂ

ꢅ

ꢋ

ꢌ 

SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008

APPLICATION INFORMATION

5 V

1 MΩ

0.1 µ F

0.22 µF

−

1/2

TLC27M2

1 MΩ

100 kΩ

10 kΩ

0.1 µF

Figure 49. Single-Rail AC Amplifiers

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TLC27M2ACD

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOIC

PDIP

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

27M2AC

TLC27M2ACDG4

TLC27M2ACDR

TLC27M2ACDRG4

TLC27M2ACP

ACTIVE

2500

Green (RoHS

& no Sb/Br)

0 to 70

27M2AC

Green (RoHS

& no Sb/Br)

0 to 70

27M2AC

Green (RoHS

& no Sb/Br)

0 to 70

27M2AC

Pb-Free

(RoHS)

0 to 70

TLC27M2AC

27M2AI

TLC27M2ACPE4

TLC27M2AID

Pb-Free

(RoHS)

N / A for Pkg Type

0 to 70

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

-40 to 85

0 to 70

TLC27M2AIDG4

TLC27M2AIDR

TLC27M2AIDRG4

TLC27M2AIP

Green (RoHS

& no Sb/Br)

27M2AI

2500

Green (RoHS

& no Sb/Br)

27M2AI

Green (RoHS

& no Sb/Br)

27M2AI

Pb-Free

(RoHS)

TLC27M2AI

27M2BC

TLC27M2AIPE4

TLC27M2BCD

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

TLC27M2BCDG4

TLC27M2BCDR

TLC27M2BCDRG4

TLC27M2BCP

Green (RoHS

& no Sb/Br)

0 to 70

27M2BC

2500

Green (RoHS

& no Sb/Br)

0 to 70

27M2BC

Green (RoHS

& no Sb/Br)

0 to 70

27M2BC

Pb-Free

(RoHS)

0 to 70

TLC27M2BC

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

TLC27M2BCPE4

TLC27M2BID

ACTIVE

PDIP

SOIC

PDIP

SOIC

PDIP

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

TLC27M2BC

ACTIVE

Green (RoHS

& no Sb/Br)

-40 to 85

0 to 70

27M2BI

TLC27M2BIDG4

TLC27M2BIDR

TLC27M2BIDRG4

TLC27M2BIP

Green (RoHS

& no Sb/Br)

27M2BI

2500

Green (RoHS

& no Sb/Br)

27M2BI

Green (RoHS

& no Sb/Br)

27M2BI

Pb-Free

(RoHS)

TLC27M2BI

27M2C

TLC27M2BIPE4

TLC27M2CD

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

TLC27M2CDG4

TLC27M2CDR

TLC27M2CDRG4

TLC27M2CP

Green (RoHS

& no Sb/Br)

0 to 70

27M2C

2500

Green (RoHS

& no Sb/Br)

0 to 70

27M2C

Green (RoHS

& no Sb/Br)

0 to 70

27M2C

Pb-Free

(RoHS)

0 to 70

TLC27M2CP

TLC27M2CPE4

Pb-Free

(RoHS)

N / A for Pkg Type

0 to 70

TLC27M2CPSLE

TLC27M2CPSR

OBSOLETE

ACTIVE

TBD

Call TI

0 to 70

2000

150

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

P27M2

TLC27M2CPSRG4

TLC27M2CPW

ACTIVE

Green (RoHS

& no Sb/Br)

CU NIPDAU

Call TI

Level-1-260C-UNLIM

Call TI

0 to 70

TSSOP

Green (RoHS

& no Sb/Br)

TLC27M2CPWG4

TLC27M2CPWLE

ACTIVE

150

Green (RoHS

& no Sb/Br)

OBSOLETE

TBD

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

TLC27M2CPWR

TLC27M2CPWRG4

TLC27M2ID

ACTIVE

TSSOP

SOIC

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

P27M2

ACTIVE

2000

Green (RoHS

& no Sb/Br)

0 to 70

P27M2

Green (RoHS

& no Sb/Br)

-40 to 85

0 to 70

27M2I

TLC27M2IDG4

TLC27M2IDR

SOIC

Green (RoHS

& no Sb/Br)

27M2I

SOIC

2500

Green (RoHS

& no Sb/Br)

27M2I

TLC27M2IDRG4

TLC27M2IP

SOIC

Green (RoHS

& no Sb/Br)

27M2I

PDIP

Pb-Free

(RoHS)

TLC27M2IP

P27M2I

27M2M

TLC27M2IPE4

TLC27M2IPW

PDIP

Pb-Free

(RoHS)

N / A for Pkg Type

TSSOP

SOIC

150

2000

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

TLC27M2IPWG4

TLC27M2IPWR

TLC27M2IPWRG4

TLC27M2MD

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

-55 to 125

TLC27M2MDG4

SOIC

Green (RoHS

& no Sb/Br)

TLC27M2MFKB

TLC27M2MJG

TLC27M2MJGB

TLC27M7CD

OBSOLETE

ACTIVE

LCCC

CDIP

SOIC

TBD

Call TI

-55 to 125

0 to 70

Call TI

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

27M7C

TLC27M7CDG4

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

TLC27M7CDR

TLC27M7CDRG4

TLC27M7CP

ACTIVE

SOIC

PDIP

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

27M7C

ACTIVE

2500

Green (RoHS

& no Sb/Br)

0 to 70

27M7C

Pb-Free

(RoHS)

0 to 70

TLC27M7CP

P27M7

TLC27M7CPE4

TLC27M7CPSR

TLC27M7CPSRG4

TLC27M7ID

Pb-Free

(RoHS)

N / A for Pkg Type

0 to 70

2000

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

N / A for Pkg Type

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

P27M7

SOIC

PDIP

Green (RoHS

& no Sb/Br)

-40 to 85

27M7I

TLC27M7IDG4

TLC27M7IDR

Green (RoHS

& no Sb/Br)

27M7I

2500

Green (RoHS

& no Sb/Br)

27M7I

TLC27M7IDRG4

TLC27M7IP

Green (RoHS

& no Sb/Br)

27M7I

Pb-Free

(RoHS)

TLC27M7IP

TLC27M7IPE4

Pb-Free

(RoHS)

N / A for Pkg Type

TLC27M7MFKB

TLC27M7MJG

TLC27M7MJGB

TLC27M7MUB

OBSOLETE

LCCC

CDIP

CFP

TBD

Call TI

-55 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLC27M2ACDR

TLC27M2AIDR

TLC27M2BCDR

TLC27M2BIDR

TLC27M2CDR

TLC27M2CPSR

TLC27M2CPWR

TLC27M2IDR

SOIC

2500

2000

2500

2000

2500

330.0

12.4

16.4

12.4

16.4

12.4

6.4

8.2

7.0

6.4

8.2

6.4

5.2

6.6

3.6

5.2

6.6

5.2

2.1

2.5

1.6

2.1

2.5

2.1

8.0

12.0

8.0

12.0

8.0

12.0

16.0

12.0

16.0

12.0

TSSOP

SOIC

TLC27M7CDR

TLC27M7CPSR

TLC27M7IDR

SOIC

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLC27M2ACDR

TLC27M2AIDR

TLC27M2BCDR

TLC27M2BIDR

TLC27M2CDR

TLC27M2CPSR

TLC27M2CPWR

TLC27M2IDR

SOIC

2500

2000

2500

2000

2500

340.5

367.0

340.5

367.0

340.5

338.1

367.0

338.1

367.0

338.1

20.6

38.0

35.0

20.6

38.0

20.6

TSSOP

SOIC

TLC27M7CDR

TLC27M7CPSR

TLC27M7IDR

SOIC

Pack Materials-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.280 (7,11)

0.245 (6,22)

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

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