TLC27M2CPS [TI]
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS;
| 型号： | TLC27M2CPS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS 放大器 光电二极管 |
| 文件： | 总49页 (文件大小：1800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
D
Trimmed Offset Voltage:
TLC27M7 . . . 500 µV Max at 25°C,
= 5 V
D
D
D
D
D
D
D
Low Noise . . . Typically 32 nV/√Hz at
f = 1 kHz
V
DD
Low Power . . . Typically 2.1 mW at 25°C,
D
D
Input Offset Voltage Drift . . . Typically
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Ranges:
0°C to 70°C . . . 3 V to 16 V
−40°C to 85°C . . . 4 V to 16 V
−55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
V
= 5 V
DD
Output Voltage Range Includes Negative
Rail
12
High Input impedance . . . 10 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
D
D
Designed-In Latch-Up Immunity
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix Types)
DISTRIBUTION OF TLC27M7
INPUT OFFSET VOLTAGE
D, JG, P OR PW PACKAGE
(TOP VIEW)
FK PACKAGE
(TOP VIEW)
30
340 Units Tested From 2 Wafer Lots
1OUT
1IN −
1IN +
GND
V
CC
1
2
3
4
8
7
6
5
V
T
= 5 V
DD
= 25°C
25
20
2OUT
2IN −
2IN +
A
P Package
3
2
1
20 19
18
NC
NC
1IN −
NC
4
5
6
7
8
2OUT
NC
17
16
15
14
15
10
5
2IN −
NC
1IN +
NC
9 10 11 12 13
0
−800
−400
0
400
800
NC − No internal connection
V
IO
− Input Offset Voltage − µV
AVAILABLE OPTIONS
PACKAGE
V
max
IO
T
A
SMALL OUTLINE
CHIP CARRIER
(FK)
CERAMIC DIP
(JG)
PLASTIC DIP
(P)
TSSOP
(PW)
AT 25°C
(D)
500 µV
2 mV
TLC27M7CD
TLC27M2BCD
TLC27M2ACD
TLC27M2CD
TLC27M7ID
TLC27M2BID
TLC27M2AID
TLC27M2ID
TLC27M7MD
TLC27M2MD
—
—
TLC27M7CP
TLC27M2BCP
TLC27M2ACP
TLC27M2CP
TLC27M7IP
—
—
—
—
—
0°C to 70°C
5 mV
—
—
10 mV
500 µV
2 mV
—
—
TLC27M2CPW
—
—
—
—
—
TLC27M2BIP
TLC27M2AIP
TLC27M2IP
—
−40°C to 85°C
−55°C to 125°C
5 mV
—
—
—
10 mV
500 µV
10 mV
—
—
TLC27M2IPW
TLC27M7MFK
TLC27M2MFK
TLC27M7MJG
TLC27M2MJG
TLC27M7MP
TLC27M2MP
—
—
The D and PW package are available taped and reeled. Add R suffix to the device type (e.g.,TLC27M7CDR). For the most current package and
ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
LinCMOS is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
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Copyright 1987 − 2008, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
description
The TLC27M2 and TLC27M7 dual operational amplifiers combine a wide range of input offset voltage grades
with low offset voltage drift, high input impedance, low noise, and speeds approaching that of general-purpose
bipolar devices.These devices use Texas Instruments silicon-gate LinCMOS technology, which provides offset
voltage stability far exceeding the stability available with conventional metal-gate processes.
The extremely high input impedance, low bias currents, and high slew rates make these cost-effective devices
ideal for applications which have previously been reserved for general-purpose bipolar products, but with only
a fraction of the power consumption. Four offset voltage grades are available (C-suffix and I-suffix types),
ranging from the low-cost TLC27M2 (10 mV) to the high-precision TLC27M7 (500 µV). These advantages, in
combination with good common-mode rejection and supply voltage rejection, make these devices a good
choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC27M2 and
TLC27M7. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote
and inaccessible battery-powered applications. The common-mode input voltage range includes the negative
rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27M2 and TLC27M7 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
equivalent schematic (each amplifier)
V
DD
P3
P4
R6
R1
R2
N5
C1
IN −
P5
P6
P1
P2
IN +
R5
OUT
N3
D2
N1
R3
N2
D1
N4
N6
R7
N7
R4
GND
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V
V
ID
DD
DD
I
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
DD
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN−.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING
A
D
FK
JG
P
725 mW
5.8 mW/°C
11.0 mW/°C
8.4 mW/°C
8.0 mW/°C
464 mW
880 mW
672 mW
640 mW
377 mW
715 mW
546 mW
520 mW
1375 mW
275 mW
210 mW
1050 mW
1000 mW
recommended operating conditions
C SUFFIX
I SUFFIX
M SUFFIX
UNIT
MIN
3
MAX
16
MIN
4
MAX
16
MIN
4
MAX
Supply voltage, V
DD
16
3.5
8.5
125
V
V
V
= 5 V
−0.2
−0.2
0
3.5
8.5
70
−0.2
−0.2
−40
3.5
8.5
85
0
DD
Common-mode input voltage, V
IC
V
= 10 V
0
DD
Operating free-air temperature, T
−55
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C
PARAMETER
TEST CONDITIONS
UNIT
†
T
A
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
= 0,
O
S
IC
R = 100 kΩ
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C
12
I
mV
0.9
220
185
5
V
R
= 1.4 V,
= 50 Ω,
V
= 0,
O
IC
R = 100 kΩ
Full range
25°C
6.5
S
I
V
IO
Input offset voltage
2000
3000
500
1500
V
R
= 1.4 V,
= 50 Ω,
V
= 0,
O
IC
R = 100 kΩ
Full range
25°C
S
I
µV
V
R
= 1.4 V,
= 50 Ω,
V
= 0,
O
IC
R = 100 kΩ
Full range
S
I
Average temperature coefficient of input
offset voltage
25°C to
70°C
α
1.7
µV/°C
pA
VIO
25°C
70°C
25°C
70°C
0.1
7
60
300
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 2.5 V,
= 2.5 V,
V
V
= 2.5 V
= 2.5 V
O
O
IC
0.6
40
I
IB
pA
IC
600
−0.2
to
−0.3
to
4.2
25°C
V
V
4
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
3.5
25°C
0°C
3.2
3
3.9
3.9
4
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
R
= 100 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
70°C
25°C
0°C
3
0
50
50
50
0
= −100 mV,
= 0.25 V to 2 V,
I
OL
OL
70°C
25°C
0°C
0
25
15
15
65
60
60
70
60
60
170
200
140
91
91
92
93
92
94
210
250
170
Large-signal differential voltage
amplification
A
R
= 100 kΩ
VD
L
70°C
25°C
0°C
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
70°C
25°C
0°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
70°C
25°C
0°C
560
640
440
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (two amplifiers)
µA
DD
No load
70°C
†
Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
5
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
electrical characteristics at specified free-air temperature, V
= 10 V (unless otherwise noted)
DD
TLC27M2C
TLC27M2AC
†
TLC27M2BC
TLC27M7C
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
MAX
25°C
Full range
25°C
1.1
10
12
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
S
IC
L
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C
mV
0.9
224
190
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
25°C
6.5
S
L
V
IO
Input offset voltage
2000
3000
800
1900
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
70°C
α
2.1
µV/°C
pA
VIO
25°C
70°C
25°C
70°C
0.1
7
60
300
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 5 V,
= 5 V,
V
V
= 5 V
= 5 V
O
O
IC
0.7
50
I
IB
pA
IC
600
−0.2
to
−0.3
to
9.2
25°C
V
V
9
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
8.5
25°C
0°C
8
7.8
7.8
8.7
8.7
8.7
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 100 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
70°C
25°C
0°C
50
50
50
0
I
OL
OL
70°C
25°C
0°C
0
25
15
15
65
60
60
70
60
60
275
320
230
94
Large-signal differential voltage
amplification
A
R
= 100 kΩ
VD
L
70°C
25°C
0°C
94
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
70°C
25°C
0°C
94
93
92
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
70°C
25°C
0°C
94
285
345
220
600
800
560
= 5 V,
= 5 V,
O
IC
I
Supply current (two amplifiers)
µA
DD
No load
70°C
†
Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ
ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁꢉ
ꢊ
ꢂ
ꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC27M2I
TLC27M2AI
†
TLC27M2BI
TLC27M7I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
S
IC
L
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I
13
mV
0.9
220
185
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
25°C
7
S
L
V
IO
Input offset voltage
2000
3500
500
2000
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
85°C
α
1.7
µV/°C
pA
VIO
25°C
85°C
25°C
85°C
0.1
24
60
1000
60
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 2.5 V,
= 2.5 V,
V
V
= 2.5 V
= 2.5 V
O
O
IC
0.6
200
I
IB
pA
IC
2000
−0.2
to
−0.3
to
4.2
25°C
V
V
4
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
3.5
25°C
−40°C
85°C
3.2
3
3.9
3.9
4
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
R
= 100 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
3
25°C
0
50
50
50
−40°C
85°C
0
= −100 mV,
= 0.25 V to 2 V,
I
OL
OL
0
25°C
25
15
15
65
60
60
70
60
60
170
270
130
91
90
90
93
91
94
210
315
160
Large-signal differential voltage
amplification
−40°C
85°C
A
R
= 100 kΩ
VD
L
25°C
−40°C
85°C
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
25°C
−40°C
85°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
25°C
560
800
400
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (two amplifiers)
−40°C
85°C
µA
DD
No load
†
Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ
ꢋ
ꢁ
ꢉ
ꢊ
ꢂ
ꢅ
ꢋ
ꢌ
ꢍꢎ
ꢏꢂ
ꢐ
ꢌ
ꢐ
ꢋꢑ
ꢒ
ꢓ
ꢇꢁ
ꢍꢏ
ꢎꢇꢀ
ꢐꢋ
ꢑꢇ
ꢁ
ꢇ
ꢅ
ꢍ
ꢁ
ꢐ
ꢔ
ꢐ
ꢏ
ꢎ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
electrical characteristics at specified free-air temperature, V
= 10 V (unless otherwise noted)
DD
TLC27M2I
TLC27M2AI
†
TLC27M2BI
TLC27M7I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
S
IC
L
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I
13
mV
0.9
224
190
5
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
25°C
7
S
L
V
IO
Input offset voltage
2000
3500
800
2900
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
25°C
S
L
µV
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
85°C
α
VIO
2.1
µV/°C
25°C
85°C
25°C
0.1
26
60
1000
60
I
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 5 V,
= 5 V,
V
V
= 5 V
= 5 V
pA
IO
O
O
IC
0.7
I
IB
pA
200
0
IC
85°C
220
−0.2
to
−0.3
to
9.2
25°C
V
V
9
Common-mode input voltage range
(see Note 5)
V
ICR
−0.2
to
Full range
8.5
25°C
−40°C
85°C
8
7.8
7.8
8.7
8.7
8.7
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 100 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
25°C
50
50
50
−40°C
85°C
0
I
OL
OL
0
25°C
25
15
15
65
60
60
70
60
60
275
390
220
94
Large-signal differential voltage
amplification
−40°C
85°C
A
VD
R
= 100 kΩ
L
25°C
−40°C
85°C
93
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
94
25°C
93
−40°C
85°C
91
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
94
25°C
285
450
205
600
900
520
= 5 V,
= 5 V,
O
IC
I
Supply current
−40°C
85°C
µA
DD
No load
†
Full range is −40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ
ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁꢉ
ꢊ
ꢂꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC27M2M
TLC27M7M
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
S
IC
L
TLC27M2M
TLC27M7M
12
V
IO
Input offset voltage
mV
185
500
3750
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
125°C
α
VIO
1.7
µV/°C
25°C
125°C
25°C
0.1
1.4
0.6
9
60
15
60
35
pA
nA
pA
nA
I
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 2.5 V,
= 2.5 V,
V
V
= 2.5 V
= 2.5 V
IO
O
O
IC
I
IB
IC
125°C
0
to
4
−0.3
to
4.2
25°C
V
V
Common-mode input voltage range
(see Note 5)
V
ICR
0
to
Full range
3.5
25°C
−55°C
125°C
25°C
3.2
3
3.9
3.9
4
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
R
= 100 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
3
0
50
50
50
−55°C
125°C
25°C
0
= −100 mV,
= 0.25 V to 2 V,
I
OL
OL
0
25
15
15
65
60
60
70
60
60
170
290
120
91
89
91
93
91
94
210
340
140
Large-signal differential voltage
amplification
−55°C
125°C
25°C
A
VD
R
= 100 kΩ
L
−55°C
125°C
25°C
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
−55°C
125°C
25°C
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
/∆V )
DD
IO
560
880
360
= 2.5 V,
= 2.5 V,
O
IC
I
Supply current (two amplifiers)
−55°C
125°C
µA
DD
No load
†
Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ
ꢋ
ꢁ
ꢉ
ꢊ
ꢂ
ꢅꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢂ
ꢐ
ꢌ
ꢐ
ꢋꢑ
ꢒ
ꢓ
ꢇꢁ
ꢍꢏ
ꢎꢇꢀ
ꢐ
ꢋ
ꢑꢇ
ꢁ
ꢇ
ꢅ
ꢍ
ꢁ
ꢐ
ꢔ
ꢐ
ꢏ
ꢎ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
electrical characteristics at specified free-air temperature, V
= 10 V (unless otherwise noted)
DD
TLC27M2M
TLC27M7M
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
10
25°C
Full range
25°C
1.1
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
S
IC
L
TLC27M2M
TLC27M7M
12
V
IO
Input offset voltage
mV
190
800
4300
V
R
= 1.4 V,
= 50 Ω,
V
R
= 0,
= 100 kΩ
O
IC
Full range
S
L
Average temperature coefficient of input
offset voltage
25°C to
125°C
α
2.1
µV/°C
pA
VIO
25°C
125°C
25°C
0.1
1.8
0.7
10
60
15
60
35
I
IO
Input offset current (see Note 4)
Input bias current (see Note 4)
V
V
= 5 V,
= 5 V,
V
V
= 5 V
= 5 V
O
O
IC
I
IB
pA
IC
125°C
0
to
9
−0.3
to
9.2
25°C
V
V
Common-mode input voltage range
(see Note 5)
V
ICR
0
to
Full range
8.5
25°C
−55°C
125°C
25°C
8
7.8
7.8
8.7
8.6
8.8
0
V
V
High-level output voltage
Low-level output voltage
V
V
V
V
= 100 mV,
= −100 mV,
= 1 V to 6 V,
R
= 100 kΩ
= 0
V
mV
V/mV
dB
OH
ID
ID
O
L
50
50
50
−55°C
125°C
25°C
0
I
OL
OL
0
25
15
15
65
60
60
70
60
60
275
420
190
94
Large-signal differential voltage
amplification
−55°C
125°C
25°C
A
R
= 100 kΩ
VD
L
−55°C
125°C
25°C
93
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
= V min
ICR
IC
93
93
−55°C
125°C
25°C
91
k
V
V
= 5 V to 10 V,
V
V
= 1.4 V
dB
SVR
DD
O
(∆V
DD
/∆V )
IO
94
285
490
180
600
1000
480
= 5 V,
= 5 V,
O
IC
I
Supply current (two amplifiers)
−55°C
125°C
µA
DD
No load
†
Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ
ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁꢉ
ꢊ
ꢂꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
0.43
0.46
0.36
0.40
0.43
0.34
MAX
25°C
0°C
V
V
= 1 V
I(PP)
R
C
= 100 kΩ,
= 20 pF,
L
L
70°C
25°C
0°C
SR
Slew rate at unity gain
V/µs
See Figure 1
= 2.5 V
I(PP)
70°C
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
0°C
55
60
V
R
= V
OH
= 100 kΩ,
,
C
= 20 pF,
O
L
kHz
B
B
Maximum output-swing bandwidth
OM
See Figure 1
70°C
25°C
0°C
50
525
600
400
40°
41°
39°
V = 10 mV,
I
See Figure 3
C = 20 pF,
L
kHz
Unity-gain bandwidth
Phase margin
1
70°C
25°C
0°C
V = 10 mV,
f = B ,
1
See Figure 3
I
L
φ
m
C
= 20 pF,
70°C
operating characteristics at specified free-air temperature, V
= 10 V
DD
TLC27M2C
TLC27M2AC
TLC27M2BC
TLC27M7C
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
0.62
0.67
0.51
0.56
0.61
0.46
MAX
25°C
0°C
V
V
= 1 V
I(PP)
R
C
= 100 kΩ,
L
L
70°C
25°C
0°C
= 20 pF,
SR
Slew rate at unity gain
V/µs
See Figure 1
= 5.5 V
I(PP)
70°C
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
0°C
35
40
V
R
= V
OH
= 100 kΩ,
,
C
= 20 pF,
O
L
B
B
Maximum output-swing bandwidth
kHz
OM
See Figure 1
70°C
25°C
0°C
30
635
710
510
43°
44°
42°
V = 10 mV,
I
See Figure 3
C = 20 pF,
L
Unity-gain bandwidth
Phase margin
kHz
1
70°C
25°C
0°C
V = 10 mV,
f = B ,
1
See Figure 3
I
L
φ
m
C
= 20 pF,
70°C
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ
ꢉ
ꢁ
ꢊ
ꢂ
ꢅꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢂ
ꢐ
ꢌ
ꢐ
ꢋ
ꢑ
ꢒ
ꢓ
ꢇ
ꢁ
ꢋ
ꢍ
ꢏ
ꢎ
ꢇ
ꢀ
ꢐ
ꢋ
ꢑ
ꢇ
ꢁ
ꢇ
ꢅ
ꢍ
ꢁ
ꢐ
ꢔ
ꢐ
ꢏ
ꢎ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
0.43
0.51
0.35
0.40
0.48
0.32
MAX
25°C
−40°C
85°C
V
V
= 1 V
I(PP)
R
C
= 100 kΩ,
= 20 pF,
L
L
SR
Slew rate at unity gain
V/µs
25°C
See Figure 1
−40°C
85°C
= 2.5 V
I(PP)
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
−40°C
85°C
55
75
V
R
= V
OH
= 100 kΩ,
,
C
= 20 pF,
O
L
B
B
Maximum output-swing bandwidth
kHz
OM
See Figure 1
45
25°C
525
770
370
40°
43°
38°
V = 10 mV,
I
See Figure 3
C = 20 pF,
L
−40°C
85°C
Unity-gain bandwidth
Phase margin
kHz
1
25°C
V = 10 mV,
f = B ,
1
See Figure 3
I
L
φ
m
−40°C
85°C
C
= 20 pF,
operating characteristics at specified free-air temperature, V
= 10 V
DD
TLC27M2I
TLC27M2AI
TLC27M2BI
TLC27M7I
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
0.62
0.77
0.47
0.56
0.70
0.44
MAX
25°C
−40°C
85°C
V
V
= 1 V
I(PP)
R
C
= 100 kΩ,
L
L
= 20 pF,
SR
Slew rate at unity gain
V/µs
25°C
See Figure 1
−40°C
85°C
= 5.5 V
I(PP)
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
−40°C
85°C
35
45
V
R
= V
OH
= 100 kΩ,
,
C
= 20 pF,
O
L
B
B
Maximum output-swing bandwidth
kHz
OM
See Figure 1
25
25°C
635
880
480
43°
46°
41°
V = 10 mV,
I
See Figure 3
C = 20 pF,
L
−40°C
85°C
Unity-gain bandwidth
Phase margin
kHz
1
25°C
V = 10 mV,
f = B ,
1
See Figure 3
I
L
φ
m
−40°C
85°C
C
= 20 pF,
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC27M2M
TLC27M7M
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
0.43
0.54
0.29
0.40
0.49
0.28
MAX
25°C
−55°C
125°C
25°C
V
= 1 V
I(PP)
I(PP)
R
C
= 100 kΩ,
L
L
= 20 pF,
SR
Slew rate at unity gain
V/µs
See Figure 1
−55°C
125°C
V
= 2.5 V
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
−55°C
125°C
25°C
55
80
V
R
= V
OH
,
C
= 20 pF,
O
L
L
B
B
Maximum output-swing bandwidth
kHz
OM
= 100 kΩ, See Figure 1
40
525
850
330
40°
44°
36°
V = 10 mV,
I
See Figure 3
C = 20 pF,
L
−55°C
125°C
25°C
Unity-gain bandwidth
Phase margin
kHz
1
V = 10 mV,
f = B ,
1
See Figure 3
I
φ
m
−55°C
125°C
C
= 20 pF,
L
operating characteristics at specified free-air temperature, V
= 10 V
DD
TLC27M2M
TLC27M7M
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP
0.62
0.81
0.38
0.56
0.73
0.35
MAX
25°C
−55°C
125°C
25°C
V
= 1 V
I(PP)
I(PP)
R
C
= 100 kΩ,
= 20 pF,
L
L
SR
Slew rate at unity gain
V/µs
See Figure 1
−55°C
125°C
V
= 5.5 V
f = 1 kHz,
See Figure 2
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
32
nV/√Hz
25°C
−55°C
125°C
25°C
35
50
V
R
= V
OH
,
C
= 20 pF,
O
L
L
B
B
Maximum output-swing bandwidth
kHz
OM
= 100 kΩ, See Figure 1
20
635
960
440
43°
47°
39°
V = 10 mV,
I
See Figure 3
C = 20 pF,
L
−55°C
125°C
25°C
Unity gain bandwidth
Phase margin
kHz
1
V = 10 mV,
f = B ,
1
See Figure 3
I
φ
m
−55°C
125°C
C
= 20 pF,
L
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ꢉ
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ꢎ
ꢏ
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ꢐ
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ꢐ
ꢋ
ꢑ
ꢒ
ꢓ
ꢇ
ꢁ
ꢋ
ꢍ
ꢏ
ꢎ
ꢇ
ꢀ
ꢐ
ꢋ
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ꢇ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC27M2 and TLC27M7 are optimized for single-supply operation, circuit configurations used for
the various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.
V
DD
+
V
DD
−
−
V
O
V
O
+
+
V
I
V
I
R
C
R
C
L
L
L
L
V
DD
−
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
2 kΩ
2 kΩ
V
DD
V
DD
+
20 Ω
−
−
+
1/2 V
DD
V
O
V
O
20 Ω
+
20 Ω
20 Ω
V
DD
−
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 2. Noise-Test Circuit
10 kΩ
10 kΩ
V
DD
+
V
DD
100 Ω
100 Ω
−
+
−
+
V
I
V
I
V
O
V
O
1/2 V
DD
C
L
C
L
V
DD
−
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC27M2 and TLC27M7 operational amplifiers, attempts to
measure the input bias current can result in erroneous readings. The bias current at normal room ambient
temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two
suggestions are offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution—many automatic testers as well as some bench-top operational amplifier testers
use the servo-loop technique with a resistor in series with the device input to measure the input bias
current (the voltage drop across the series resistor is measured and the bias current is calculated). This
method requires that a device be inserted into the test socket to obtain a correct reading; therefore, an
open-socket reading is not feasible using this method.
5
8
8
5
V = V
IC
1
4
Figure 4. Isolation Metal Around Device Inputs (JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
PARAMETER MEASUREMENT INFORMATION
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage, since
the moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz
(b) B
> f > 1 kHz
(c) f = B
OM
(d) f > B
OM
OM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
16
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
6, 7
V
IO
Input offset voltage
Distribution
α
Temperature coefficient
Distribution
8, 9
VIO
vs High-level output current
vs Supply voltage
vs Free-air temperature
10, 11
12
13
V
OH
High-level output voltage
vs Common-mode input voltage
vs Differential input voltage
vs Free-air temperature
14, 15
16
17
V
OL
Low-level output voltage
vs Low-level output current
18, 19
vs Supply voltage
vs Free-air temperature
vs Frequency
20
21
32, 33
A
VD
Differential voltage amplification
I
/I
Input bias and input offset current
Common-mode input voltage
vs Free-air temperature
vs Supply voltage
22
23
IB IO
V
IC
vs Supply voltage
vs Free-air temperature
24
25
I
Supply current
Slew rate
DD
vs Supply voltage
vs Free-air temperature
26
27
SR
Normalized slew rate
vs Free-air temperature
vs Frequency
28
29
V
Maximum peak-to-peak output voltage
O(PP)
vs Free-air temperature
vs Supply voltage
30
31
B
Unity-gain bandwidth
Phase margin
1
vs Supply voltage
vs Free-air temperature
vs Capacitive loads
34
35
36
φ
m
V
Equivalent input noise voltage
Phase shift
vs Frequency
vs Frequency
37
n
φ
32, 33
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC27M2
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC27M2
INPUT OFFSET VOLTAGE
60
50
40
30
20
10
0
60
50
40
30
20
10
0
612 Amplifiers Tested From 4 Wafer Lots
612 Amplifiers Tested From 4 Wafer Lots
V
= 5 V
DD
= 25°C
V
T
A
= 10 V
DD
= 25°C
T
A
P Package
P Package
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 6
Figure 7
DISTRIBUTION OF TLC27M2 AND TLC27M7
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC27M2 AND TLC27M7
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
TEMPERATURE COEFFICIENT
60
50
40
30
20
10
0
60
50
40
30
20
10
0
224 Amplifiers Tested From 6 Wafer Lots
224 Amplifiers Tested From 6 Wafer Lots
V
T
A
= 5 V
V
T
A
= 10 V
DD
= 25°C to 125°C
DD
= 25°C to 125°C
P Package
Outliers:
(1) 33.0 µV/°C
P Package
Outliers:
(1) 34.6 µV/°C
−10 −8 −6 −4 −2
0
2
4
6
8
10
−10 −8 −6 −4 −2
0
2
4
6
8
10
α
− Temperature Coefficient − µV/°C
α
− Temperature Coefficient − µV/°C
VIO
VIO
Figure 8
Figure 9
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5
4
3
2
1
0
16
14
12
10
8
V
= 100 mV
ID
= 25°C
V
= 100 mV
ID
= 25°C
T
A
T
A
V
= 16 V
DD
DD
V
= 5 V
DD
V
= 4 V
DD
V
= 10 V
V
DD
= 3 V
6
4
2
0
0
−2
−4
−6
−8
−10
0
−10
−20
−30
−40
I
− High-Level Output Current − mA
I
− High-Level Output Current − mA
OH
OH
Figure 10
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
V
V
V
V
−1.6
−1.7
−1.8
−1.9
−2
16
14
12
10
8
DD
DD
DD
V
R
T
= 100 mV
ID
I
= −5 mA
OH
= 100 kΩ
= 25°C
L
V
= 100 mA
ID
V
DD
= 5 V
A
DD
V
DD
V
DD
= 10 V
V
DD
V
DD
V
DD
V
DD
−2.1
−2.2
−2.3
−2.4
6
4
2
0
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 12
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
700
500
450
400
350
300
250
V
= 5 V
= 5 mA
= 25°C
DD
V
DD
= 10 V
650
600
I
T
OL
A
I
= 5 mA
OL
T
A
= 25°C
550
500
450
400
V
= −100 mV
ID
V
ID
V
ID
V
ID
= −100 mV
= −1 V
= −2.5 V
V
ID
= −1 V
350
300
0
1
2
3
4
5
6
7
8
7
10
0
1
2
3
4
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 14
Figure 15
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL INPUT VOLTAGE
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
I
OL
= 5 mA
= −1 V
= 0.5 V
I
V
= 5 mA
OL
V
ID
V
IC
= |V /2|
ID
IC
= 25°C
T
A
V
= 5 V
DD
V
= 5 V
DD
V
DD
= 10 V
V
= 10 V
DD
−75 −50 −25
0
25
50
75
100 125
0
−1 −2 −3 −4 −5 −6 −7 −8 −9 −10
T
A
− Free-Air Temperature − °C
V
ID
− Differential Input Voltage − V
Figure 16
Figure 17
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁꢉ
ꢊ
ꢂ
ꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3
2.5
2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= −1 V
= 0.5 V
= 25°C
ID
V
V
= −1 V
ID
V
IC
T
= 0.5 V
IC
A
V
= 16 V
DD
T
A
= 25°C
V
= 5 V
DD
V
= 4 V
DD
V
= 10 V
DD
V
= 3 V
DD
1.5
1
0.5
0
0
5
10
15
20
25
30
0
1
2
3
4
5
6
7
8
I
− Low-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
OL
Figure 18
Figure 19
LARGE-SIGNAL
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
T
= −55°C
−40°C
A
R
= 100 kΩ
R
= 100 kΩ
L
L
0°C
V
= 10 V
25°C
70°C
DD
85°C
125°C
V
0
= 5 V
DD
0
0
−75 −50 −25
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 20
Figure 21
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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ꢉ
ꢁ
ꢊ
ꢂ
ꢅꢋ
ꢌ
ꢍꢎ ꢏꢂ ꢐꢌ ꢐ ꢋꢑ ꢒꢓ ꢇꢁ ꢋ ꢍꢏ ꢎꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍꢁ ꢐꢔ ꢐꢏ ꢎꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
COMMON-MODE
INPUT BIAS CURRENT AND INPUT OFFSET
INPUT VOLTAGE POSITIVE LIMIT
CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
16
14
12
10
8
10000
1000
100
10
V
V
= 10 V
T = 25°C
A
DD
= 5 V
IC
See Note A
I
IB
I
IO
6
4
1
2
0
0.1
0
2
4
V
6
8
10
12
14
16
25
45
A
65
85
105
125
− Supply Voltage − V
T
− Free-Air Temperature − °C
DD
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
Figure 22
Figure 23
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
500
450
400
350
300
250
200
150
100
50
800
V
= V /2
DD
V
= V /2
DD
O
O
T
= −55°C
700
600
500
400
300
200
100
0
No Load
A
No Load
−40°C
V
= 10 V
DD
0°C
25°C
70°C
V
= 5 V
DD
125°C
0
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 24
Figure 25
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁꢉ
ꢊ
ꢂꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
SLEW RATE
vs
SLEW RATE
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
A
= 1
= 1 V
= 100 kΩ
= 20 pF
V
A
R
C
= 1
= 100 kΩ
= 20 pF
V
R
C
V
L
L
IPP
L
V
V
= 10 V
= 5.5 V
DD
I(PP)
L
See Figure 1
T
= 25°C
A
See Figure 1
V
V
= 10 V
DD
= 1 V
I(PP)
V
V
= 5 V
DD
I(PP)
= 1 V
V
V
= 5 V
DD
= 2.5 V
I(PP)
0
2
4
6
8
10
12
14
16
− 75 − 50 − 25
0
25
50
75
100 125
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 26
Figure 27
MAXIMUM PEAK-TO-PEAK OUTPUT
NORMALIZED SLEW RATE
vs
VOLTAGE
vs
FREE-AIR TEMPERATURE
FREQUENCY
1.4
1.3
1.2
1.1
1
10
9
8
7
6
5
4
3
2
1
0
A
= 1
V
V
R
C
= 1 V
I(PP)
V
= 10 V
DD
= 100 kΩ
= 20 pF
L
L
V
V
= 10 V
DD
V
DD
= 5 V
T
= 125°C
= 25°C
A
T
A
T
= −55°C
A
0.9
0.8
0.7
0.6
0.5
= 5 V
DD
R
= 100 kΩ
L
See Figure 1
−75 −50 −25
0
25
50
75
100 125
1
10
100
1000
T
A
− Free-Air Temperature − °C
f − Frequency − kHz
Figure 28
Figure 29
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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ꢉ
ꢁ
ꢊ
ꢂ
ꢅꢋ
ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
UNITY-GAIN BANDWIDTH
UNITY-GAIN BANDWIDTH
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
900
800
700
600
500
400
300
800
750
700
650
600
550
500
450
400
V = 10 mV
V
= 5 V
I
DD
V = 10 mV
C
= 20 pF
= 25°C
L
I
C
T
= 20 pF
A
L
See Figure 3
See Figure 3
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − C
V
DD
− Supply Voltage − V
Figure 30
Figure 31
LARGE-SCALE DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
6
5
4
3
2
10
10
10
10
10
10
V
= 5 V
= 100 kΩ
= 25°C
DD
R
L
T
A
0°
30°
A
VD
60°
90°
Phase Shift
10
1
120°
150°
180°
0.1
0
10
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
Figure 32
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁ
ꢉ
ꢊ
ꢂꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
†
TYPICAL CHARACTERISTICS
LARGE-SCALE DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
6
5
4
3
2
10
10
10
10
10
10
V
R
T
A
= 10 V
= 100 kΩ
= 25°C
DD
L
0°
30°
A
VD
60°
90°
Phase Shift
10
1
120°
150°
180°
0.1
0
10
100
1 k
10 k
100 k
1 M
f − Frequency − Hz
Figure 33
PHASE MARGIN
PHASE MARGIN
vs
SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
45°
43°
41°
39°
37°
35°
50°
48°
46°
44°
42°
40°
38°
V
= 5 V
V = 10 mV
DD
V = 10 mV
I
C
T
A
= 20 pF
= 25°C
I
L
C
= 20 pF
L
See Figure 3
See Figure 3
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − C
V
DD
− Supply Voltage − V
Figure 34
Figure 35
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
25
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ꢉ
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ꢍꢎ ꢏꢂ ꢐꢌ ꢐ ꢋꢑ ꢒꢓ ꢇꢁ ꢋ ꢍꢏ ꢎꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍꢁ ꢐꢔ ꢐꢏ ꢎꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
44°
42°
40°
38°
36°
34°
32°
30°
V
= 5 V
DD
V = 10 mV
I
T
A
= 25°C
See Figure 3
28°
0
10 20 30 40 50 60 70 80 90 100
C
− Capacitive Load − pF
L
Figure 36
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
300
250
200
150
100
50
V
= 5 V
= 20 Ω
= 25°C
DD
S
R
T
A
See Figure 2
0
1
10
100
1000
f −Frequency − Hz
Figure 37
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
single-supply operation
While the TLC27M2 and TLC27M7 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground, as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27M2 and TLC27M7 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27M2 and TLC27M7 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
V
DD
R4
R3
)
R1
R3
V
+ V
R2
REF
DD
R1
R3
−
+
V
I
R4
R2
V
O
ǒVREF–V Ǔ
V
+
)
V
O
I
REF
V
REF
C
0.01µF
Figure 38. Inverting Amplifier With Voltage Reference
−
Power
Supply
Logic
Logic
Logic
Output
+
(a) COMMON SUPPLY RAILS
−
Power
Supply
Logic
Logic
Logic
Output
+
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common Versus Separate Supply Rails
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ꢉ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
input characteristics
The TLC27M2 and TLC27M7 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at V
−1 V at T = 25°C and at V
−1.5 V at all other temperatures.
DD
A
DD
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27M2 and TLC27M7
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27M2 and
TLC27M7 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27M2 and TLC27M7 result in a very
low noise current, which is insignificant in most applications. This feature makes the devices especially
favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices
exhibit greater noise currents.
−
−
V
I
V
O
−
+
+
V
O
V
I
+
V
O
V
I
(c) UNITY-GAIN AMPLIFIER
(b) INVERTING AMPLIFIER
(a) NONINVERTING AMPLIFIER
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC27M2 and TLC27M7 is designed to sink and source relatively high amounts of
current (see typical characteristics). If the output is subjected to a short-circuit condition, this high current
capability can cause device damage under certain conditions. Output current capability increases with supply
voltage.
All operating characteristics of the TLC27M2 and TLC27M7 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
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ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
(a) C = 20 pF, R = NO LOAD
(b) C = 170 pF, R = NO LOAD
L L
L
L
2.5 V
−
V
O
+
T
= 25°C
A
V
I
C
f = 1 kHz
= 1 V
L
V
I(PP)
−2.5 V
(d) TEST CIRCUIT
(c) C = 190 pF, R = NO LOAD
L
L
Figure 41. Effect of Capacitive Loads and Test Circuit
output characteristics (continued)
Although the TLC27M2 and TLC27M7 possess excellent high-level output voltage and current capability,
methods for boosting this capability are available, if needed. The simplest method involves the use of a pullup
resistor (R ) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages
P
to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a
comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance
between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With
very low values of R , a voltage offset from 0 V at the output occurs. Second, pullup resistor R acts as a drain
P
P
load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying
the output current.
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SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
output characteristics (continued)
V
DD
V
I
R
P
+
−
I
P
V
O
C
−
I
I
P
R2
R1
R
L
L
V
O
V
* V
+
DD
O
R
+
P
I
) I ) I
F
L
P
I
= Pullup current required by the op-
P
erational amplifier (typically 500 µA)
Figure 43. Compensation for Input Capacitance
Figure 42. Resistive Pullup to Increase V
OH
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic-discharge protection
The TLC27M2 and TLC27M7 incorporate an internal electrostatic-discharge (ESD) protection circuit that
prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care
should be exercised, however, when handling these devices as exposure to ESD may result in the degradation
of the device parametric performance. The protection circuit also causes the input bias currents to be
temperature dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27M2 and
TLC27M7 inputs and outputs were designed to withstand −100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ
ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁꢉ
ꢊ
ꢂꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
1N4148
470 kΩ
100 kΩ
5 V
1/2
TLC27M2
−
+
5 V
I
S
1/2
TLC27M7
47 kΩ
V
I
V
O
+
100 kΩ
−
2N3821
R2
68 kΩ
100 kΩ
1 µF
C2
2.2 nF
R1
68 kΩ
C1
2.2 nF
R
NOTES: V
f
≈ 2 V
NOTES: V = 0 V to 3 V
I
O(PP)
1
VI
+
O
I
+
Ǹ
2p R1R2C1C2
S
R
Figure 45. Precision Low-Current Sink
Figure 44. Wien Oscillator
5 V
Gain Control
1 MΩ
100 kΩ
(see Note A)
1µ F
−
+
+
10 kΩ
1 kΩ
+
−
−
+
1/2
TLC27M2
−
0.1 µF
100 kΩ
0.1 µF
100 kΩ
NOTE A: Low to medium impedance dynamic mike
Figure 46. Microphone Preamplifier
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀꢁ ꢂꢃ ꢄ ꢅꢃ ꢈ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄ
ꢉ
ꢁ
ꢊ
ꢂ
ꢅ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢂ
ꢐ
ꢌ
ꢐ
ꢋ
ꢑ
ꢒ
ꢓ
ꢇ
ꢁ
ꢋ
ꢍ
ꢏ
ꢎ
ꢇ
ꢀ
ꢐ
ꢋ
ꢑ
ꢇ
ꢁ
ꢇ
ꢅ
ꢍ
ꢁ
ꢐ
ꢔ
ꢐ
ꢏ
ꢎ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
10 MΩ
V
DD
−
+
1/2
TLC27M2
1 kΩ
−
+
V
1/2
O
TLC27M2
15 nF
V
REF
100 kΩ
150 pF
NOTES: V
= 4 V to 15 V
DD
V
ref
= 0 V to V − 2 V
DD
Figure 47. Photo-Diode Amplifier With Ambient Light Rejection
1 MΩ
V
DD
33 pF
−
+
V
O
1/2
TLC27M2
1N4148
100 kΩ
100 kΩ
NOTES: V
= 8 V to 16 V
DD
= 5 V, 10 mA
V
O
Figure 48. 5-V Low-Power Voltage Regulator
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢈꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢄ
ꢍꢎ ꢏꢂꢐꢌ ꢐꢋ ꢑ ꢒꢓꢇ ꢁ ꢋ ꢍꢏꢎ ꢇꢀ ꢐꢋ ꢑꢇꢁ ꢇꢅ ꢍ ꢁꢐ ꢔꢐ ꢏꢎ ꢌ
ꢁ
ꢉ
ꢊ
ꢂꢅ
ꢋ
ꢌ
SLOS051E − OCTOBER 1987 − REVISED AUGUST 2008
APPLICATION INFORMATION
5 V
1 MΩ
0.1 µ F
V
I
0.22 µF
+
V
O
−
1/2
TLC27M2
1 MΩ
100 kΩ
100 kΩ
10 kΩ
0.1 µF
Figure 49. Single-Rail AC Amplifiers
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC27M2ACD
TLC27M2ACDR
TLC27M2ACDRG4
TLC27M2ACP
TLC27M2ACPE4
TLC27M2AID
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
D
D
D
P
P
D
D
D
P
D
D
D
P
D
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
27M2AC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2500
2500
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
27M2AC
27M2AC
TLC27M2AC
TLC27M2AC
27M2AI
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
TLC27M2AIDR
TLC27M2AIDRG4
TLC27M2AIP
2500
2500
50
Green (RoHS
& no Sb/Br)
27M2AI
Green (RoHS
& no Sb/Br)
27M2AI
Green (RoHS
& no Sb/Br)
TLC27M2AI
27M2BC
27M2BC
27M2BC
TLC27M2BC
27M2BI
TLC27M2BCD
TLC27M2BCDG4
TLC27M2BCDR
TLC27M2BCP
TLC27M2BID
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
75
Green (RoHS
& no Sb/Br)
0 to 70
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
TLC27M2BIDG4
TLC27M2BIDR
75
Green (RoHS
& no Sb/Br)
27M2BI
2500
Green (RoHS
& no Sb/Br)
27M2BI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC27M2BIP
TLC27M2CD
ACTIVE
PDIP
SOIC
SOIC
PDIP
P
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
50
Green (RoHS
& no Sb/Br)
NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
0 to 70
TLC27M2BI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
27M2C
TLC27M2CDR
TLC27M2CP
D
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
27M2C
P
Green (RoHS
& no Sb/Br)
0 to 70
TLC27M2CP
TLC27M2CP
P27M2
TLC27M2CPE4
TLC27M2CPS
TLC27M2CPSR
TLC27M2CPW
TLC27M2CPWR
TLC27M2ID
PDIP
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
SO
PS
PS
PW
PW
D
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
SO
2000
150
2000
75
Green (RoHS
& no Sb/Br)
0 to 70
P27M2
TSSOP
TSSOP
SOIC
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
0 to 70
P27M2
Green (RoHS
& no Sb/Br)
0 to 70
P27M2
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
27M2I
TLC27M2IDG4
TLC27M2IDR
TLC27M2IP
D
75
Green (RoHS
& no Sb/Br)
27M2I
D
2500
50
Green (RoHS
& no Sb/Br)
27M2I
P
Green (RoHS
& no Sb/Br)
TLC27M2IP
P27M2I
P27M2I
P27M2I
27M2M
TLC27M2IPW
TLC27M2IPWR
TLC27M2IPWRG4
TLC27M2MD
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
D
150
2000
2000
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-55 to 125
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC27M2MDG4
TLC27M7CD
TLC27M7CDG4
TLC27M7CDR
TLC27M7CP
TLC27M7CPS
TLC27M7CPSR
TLC27M7ID
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-55 to 125
0 to 70
27M2M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
27M7C
D
75
Green (RoHS
& no Sb/Br)
0 to 70
27M7C
D
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
27M7C
P
Green (RoHS
& no Sb/Br)
0 to 70
TLC27M7CP
P27M7
PS
PS
D
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
SO
2000
75
Green (RoHS
& no Sb/Br)
0 to 70
P27M7
SOIC
SOIC
PDIP
PDIP
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
27M7I
TLC27M7IDR
TLC27M7IP
D
2500
50
Green (RoHS
& no Sb/Br)
27M7I
P
Green (RoHS
& no Sb/Br)
TLC27M7IP
TLC27M7IP
TLC27M7IPE4
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC27M2ACDR
TLC27M2AIDR
TLC27M2BCDR
TLC27M2BIDR
TLC27M2CDR
TLC27M2CPSR
TLC27M2CPWR
TLC27M2IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2000
2000
2500
2000
2500
2000
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.4
12.4
12.4
16.4
12.4
6.4
6.4
6.4
6.4
6.4
8.35
7.0
6.4
7.0
6.4
8.35
6.4
5.2
5.2
5.2
5.2
5.2
6.6
3.6
5.2
3.6
5.2
6.6
5.2
2.1
2.1
2.1
2.1
2.1
2.5
1.6
2.1
1.6
2.1
2.5
2.1
8.0
8.0
8.0
8.0
8.0
12.0
8.0
8.0
8.0
8.0
12.0
8.0
12.0
12.0
12.0
12.0
12.0
16.0
12.0
12.0
12.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
D
D
PS
PW
D
TSSOP
SOIC
TSSOP
SOIC
SO
TLC27M2IPWR
TLC27M7CDR
TLC27M7CPSR
TLC27M7IDR
PW
D
PS
D
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC27M2ACDR
TLC27M2AIDR
TLC27M2BCDR
TLC27M2BIDR
TLC27M2CDR
TLC27M2CPSR
TLC27M2CPWR
TLC27M2IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SO
D
D
8
8
8
8
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2000
2000
2500
2000
2500
2000
2500
340.5
340.5
340.5
340.5
340.5
367.0
367.0
340.5
367.0
340.5
367.0
340.5
338.1
338.1
338.1
338.1
338.1
367.0
367.0
338.1
367.0
338.1
367.0
338.1
20.6
20.6
20.6
20.6
20.6
38.0
35.0
20.6
35.0
20.6
38.0
20.6
D
D
D
PS
PW
D
TSSOP
SOIC
TSSOP
SOIC
SO
TLC27M2IPWR
TLC27M7CDR
TLC27M7CPSR
TLC27M7IDR
PW
D
PS
D
SOIC
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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