TLC2932IPWR [TI]
HIGH-PERFORMANCE PHASE-LOCKED LOOP; 高性能锁相环
| 型号： | TLC2932IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-PERFORMANCE PHASE-LOCKED LOOP |
| 文件： | 总24页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
†
Voltage-Controlled Oscillator (VCO)
Section:
PW PACKAGE
(TOP VIEW)
– Complete Oscillator Using Only One
LOGIC V
1
2
3
4
5
6
7
VCO V
BIAS
VCO IN
VCO GND
VCO INHIBIT
PFD INHIBIT
NC
14
13
12
11
10
9
DD
DD
External Bias Resistor (R
– Lock Frequency:
)
BIAS
SELECT
VCO OUT
FIN–A
FIN–B
PFD OUT
LOGIC GND
22 MHz to 50 MHz (V
= 5 V ±5%,
DD
T = –20°C to 75°C, ×1 Output)
A
11 MHz to 25 MHz (V
= 5 V ±5%,
DD
T = –20°C to 75°C, ×1/2 Output)
A
8
– Output Frequency . . . ×1 and ×1/2
†
Selectable
Availablein tape and reel only and ordered as the
TLC2932IPWLE.
Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
NC – No internal connection
Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 terminal)
CMOS Technology
Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division
†
Application Report Available
CMOS Input Logic Level
description
The TLC2932 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R
). The VCO has a 1/2 frequency divider at the output stage.
BIAS
The high-speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. The TLC2932 is suitable for use as a high-performance PLL due
to the high speed and stable oscillation capability of the device.
functional block diagram
12
VCO IN
4
5
9
13
10
2
Voltage-
Controlled
Oscillator
Phase
Frequency
Detector
FIN–A
FIN–B
BIAS
VCO INHIBIT
SELECT
3
6
VCO OUT
PFD OUT
PFD INHIBIT
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
–20°C to 75°C
TLC2932IPWLE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
Terminal Functions
TERMINAL
NAME
FIN–A
I/O
DESCRIPTION
NO.
4
I
I
Input reference frequency f
(REF IN)
is applied to FIN–A.
FIN–B
5
Input for VCO external counter output frequency f . FIN–B is nominally provided from the external
(FIN–B)
counter.
LOGIC GND
7
1
GND for the internal logic.
LOGIC V
Power supply for the internal logic. This power supply should be separate from VCO V
cross-coupling between supplies.
to reduce
DD
DD
NC
8
9
No internal connection.
PFD INHIBIT
PFD OUT
BIAS
I
O
I
PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.
PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
6
13
Bias supply. An external resistor (R
oscillation frequency range.
) between VCO V and BIAS supplies bias for adjusting the
BIAS DD
SELECT
VCO IN
2
I
I
I
VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when low, the
output frequency is ×1, see Table 1.
12
VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
VCO INHIBIT
VCO GND
VCO OUT
10
11
3
VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
GND for VCO.
O
VCO output. When the VCO INHIBIT is high, VCO output is low.
VCO V
DD
14
Power supply for VCO. This power supply should be separated from LOGIC V
between supplies.
to reduce cross-coupling
DD
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (R
) connected between the VCO V
DD
BIAS
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3 kΩ with 3-V at the VCO V terminal and
DD
nominally 2.2 kΩ with 5-V at the VCO V
terminal. For the lock frequency range refer to the recommended
DD
operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (R
)
BIAS
1/2 V
DD
VCO Control Voltage (VCO IN)
Figure 1. VCO Oscillation Frequency
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
VCO output frequency 1/2 divider
The TLC2932 SELECT terminal sets the f
or 1/2 f
VCO output frequency as shown in Table 1. The 1/2
osc
osc
f
output should be used for minimum VCO output jitter.
osc
Table 1. VCO Output 1/2 Divider Function
SELECT
Low
VCO OUTPUT
f
osc
1/2 f
High
osc
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
Low
VCO OSCILLATOR
Active
VCO OUTPUT
Active
I
DD(VCO)
Normal
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN–A
FIN–B
V
OH
PFD OUT
Hi-Z
V
OL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT
Low
DETECTION
Active
PFD OUTPUT
Active
I
DD(PFD)
Normal
High
Stopped
Hi-Z
Power Down
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
schematics
VCO block schematic
R
BIAS
BIAS
1/2
M
U
X
VCO
Output
Bias
Control
VCO OUT
VCO IN
SELECT
VCO INHIBIT
PFD block schematic
Charge Pump
V
DD
FIN–A
PFD OUT
Detector
FIN–B
PFD INHIBIT
†
absolute maximum ratings
Supply voltage (each supply), V
Input voltage range (each input), V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
+ 0.5 V
I
DD
Input current (each input), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
Output current (each output), I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
O
Continuous total power dissipation, at (or below) T = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
recommended operating conditions
PARAMETER
MIN NOM
MAX
3.15
5.25
UNIT
V
= 3 V
= 5 V
2.85
4.75
0
3
5
DD
DD
Supply voltage, V
(each supply, see Note 3)
V
DD
V
Input voltage, V (inputs except VCO IN)
V
DD
V
mA
V
I
Output current, I (each output)
O
0
±2
VCO control voltage at VCO IN
0.9
14
22
7
V
DD
21
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
Lock frequency (×1 output)
MHz
MHz
kΩ
50
10.5
25
Lock frequency (×1/2 output)
11
2.2
1.5
3.3
2.2
4.3
3.3
Bias resistor, R
BIAS
NOTE 3: It is recommended that the logic supply terminal (LOGIC V ) and the VCO supply terminal (VCO V ) should be at the same voltage
DD DD
and separated from each other.
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 3 V
DD
VCO section
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
I
= –2 mA
= 2 mA
2.4
OH
OL
IT
OH
OL
Low-level output voltage
I
0.3
2.1
±1
V
Input threshold voltage at SELECT, VCO INHIBIT
Input current at SELECT, VCO INHIBIT
Input impedance
0.9
1.5
V
I
I
V = V or GND
I DD
µA
MΩ
µA
mA
Z
VCO IN = 1/2 V
See Note 4
10
0.01
5
i(VCO IN)
DD(INH)
DD
I
I
VCO supply current (inhibit)
VCO supply current
1
See Note 5
15
DD(VCO)
NOTES: 4. Current into VCO V , when VCO INHIBIT = V , PFD is inhibited.
DD DD
5. Current into VCO V , when VCO IN = 1/2 V , R
= 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
DD
DD BIAS
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
I
I
= –2 mA
= 2 mA
2.7
OH
OH
Low-level output voltage
0.2
V
OL
OL
PFD INHIBIT = high,
V = V or GND
I
High-impedance-state output current
±1
µA
OZ
I
DD
V
V
V
High-level input voltage at FIN–A, FIN–B
Low-level input voltage at FIN–A, FIN–B
Input threshold voltage at PFD INHIBIT
Input capacitance at FIN–A, FIN–B
Input impedance at FIN–A, FIN–B
High-impedance-state PFD supply current
PFD supply current
2.7
0.9
V
V
IH
IL
IT
0.5
2.1
1.5
5
V
C
pF
MΩ
µA
mA
i
Z
i
10
I
I
See Note 6
See Note 7
0.01
0.1
1
DD(Z)
1.5
DD(PFD)
NOTES: 6. Current into LOGIC V , when FIN–A, FIN–B = GND, PFD INHIBIT = V , no load, and VCO OUT is inhibited.
DD
DD
DD
= 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
7. Current into LOGIC V , when FIN–A, FIN–B = 1 MHz (V
I(PP)
inhibited.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
operating characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 3 V
DD
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
µs
f
t
Operating oscillation frequency
Time to stable oscillation (see Note 8)
R
= 3.3 kΩ, VCO IN = 1/2 V
15
19
23
10
14
osc
BIAS
DD
Measured from VCO INHIBIT↓
s(fosc)
C
C
C
C
R
R
= 15 pF,
= 50 pF,
= 15 pF,
= 50 pF,
See Figure 3
See Figure 3
See Figure 3
See Figure 3
7
14
L
t
Rise time
Fall time
ns
ns
r
f
L
6
12
L
t
10
L
Duty cycle at VCO OUT
= 3.3 kΩ, VCO IN = 1/2 V
= 3.3 kΩ, VCO IN = 1/2 V
,
,
45%
50%
55%
BIAS
BIAS
DD
DD
α
Temperature coefficient of oscillation frequency
0.04
%/°C
(fosc)
T
A
= –20°C to 75°C
R
= 3.3 kΩ, VCO IN = 1.5 V,
BIAS
= 2.85 V to 3.15 V
k
Supply voltage coefficient of oscillation frequency
Jitter absolute (see Note 9)
0.02
100
%/mV
ps
SVS(fosc)
V
DD
R
= 3.3 kΩ
BIAS
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent
on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no device
socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
20
MHz
max
PLZ
PHZ
PZL
PZH
r
21
23
50
50
30
30
10
10
ns
ns
See Figures 4 and 5 and Table 4
11
10
2.3
2.1
ns
ns
C
= 15 pF, See Figure 4
L
Fall time
f
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5 V
DD
VCO section
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
I
I
= –2 mA
= 2 mA
4
OH
OL
IT
OH
Low-level output voltage
0.5
3.5
±1
V
OL
Input threshold voltage at SELECT, VCO INHIBIT
Input current at SELECT, VCO INHIBIT
Input impedance
1.5
2.5
V
I
I
V = V or GND
I DD
µA
MΩ
µA
mA
Z
VCO IN = 1/2 V
See Note 4
10
0.01
15
i(VCO IN)
DD(INH)
DD
I
I
VCO supply current (inhibit)
VCO supply current
1
See Note 5
35
DD(VCO)
NOTES: 4. Current into VCO V , when VCO INHIBIT = V , and PFD is inhibited.
DD DD
5. Current into VCO V , when VCO IN = 1/2 V , R
= 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
DD
DD BIAS
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
I
I
= 2 mA
= 2 mA
4.5
OH
OH
Low-level output voltage
0.2
V
OL
OL
PFD INHIBIT = high,
V = V or GND
I
High-impedance-state output current
±1
µA
OZ
I
DD
V
V
V
High-level input voltage at FIN–A, FIN–B
Low-level input voltage at FIN–A, FIN–B
Input threshold voltage at PFD INHIBIT
Input capacitance at FIN–A, FIN–B
Input impedance at FIN–A, FIN–B
High-impedance-state PFD supply current
PFD supply current
4.5
1.5
V
V
IH
IL
IT
1
2.5
5
3.5
V
C
pF
MΩ
µA
mA
i
Z
i
10
I
See Note 6
See Note 7
0.01
0.15
1
3
DD(Z)
I
DD(PFD)
NOTES: 6. Current into LOGIC V , when FIN–A, FIN–B = GND, PFD INHIBIT = V , no load, and VCO OUT is inhibited.
DD
DD
= 5 V, rectangular wave), PFD INHIBIT = GND, no load, and
7. Current into LOGIC V , when FIN–A, FIN–B = 1 MHz (V
DD
I(PP)
VCO OUT is inhibited.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
operating characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5 V
DD
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
µs
f
t
Operating oscillation frequency
Time to stable oscillation (see Note 8)
R
= 2.2 kΩ, VCO IN = 1/2 V
30
41
52
10
10
osc
BIAS
DD
Measured from VCO INHIBIT↓
s(fosc)
C
C
C
C
R
R
= 15 pF,
= 50 pF,
= 15 pF,
= 50 pF,
See Figure 3
See Figure 3
See Figure 3
See Figure 3
5.5
8
L
t
Rise time
Fall time
ns
ns
r
f
L
5
10
L
t
6
L
Duty cycle at VCO OUT
= 2.2 kΩ, VCO IN = 1/2 V
= 2.2 kΩ, VCO IN = 1/2 V
,
,
45%
50%
55%
BIAS
BIAS
DD
DD
α
Temperature coefficient of oscillation frequency
0.06
%/°C
(fosc)
T
A
= –20°C to 75°C
R
= 2.2 kΩ, VCO IN = 2.5 V,
BIAS
= 4.75 V to 5.25 V
k
Supply voltage coefficient of oscillation frequency
Jitter absolute (see Note 9)
0.006
100
%/mV
ps
SVS(fosc)
V
DD
R
= 2.2 kΩ
BIAS
NOTES: 8: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
40
MHz
max
PLZ
PHZ
PZL
PZH
r
21
20
40
40
20
20
10
10
ns
ns
See Figures 4 and 5 and Table 4
7.3
6.5
2.3
1.7
ns
ns
C
= 15 pF, See Figure 4
L
Fall time
f
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
90%
10%
90%
10%
VCO OUT
t
t
f
r
Figure 3. VCO Output Voltage Waveform
V
DD
V
DD
†
FIN–A
GND
GND
V
DD
V
DD
†
FIN–B
GND
GND
V
V
DD
DD
PFD INHIBIT
PFD OUT
50%
50%
GND
GND
t
t
PHZ
PLZ
t
t
f
r
V
OH
V
DD
90%
50%
90%
50%
10%
50%
50%
10%
V
OL
GND
t
PZL
t
PZH
(a) OUTPUT PULLDOWN
(see Figure 5 and Table 4)
(b) OUTPUT PULLUP
(see Figure 5 and Table 4)
†
FIN–A and FIN–B are for reference phase only, not for timing.
Figure 4. PFD Output Voltage Waveform
Table 4. PFD Output Test Conditions
V
DD
Test Point
PARAMETER
R
C
S
1
S
2
L
L
t
t
t
t
t
t
PZH
PHZ
r
S1
Open
Close
Close
Open
R
L
PFD OUT
1 kΩ
15 pF
DUT
PZL
PLZ
f
S2
C
L
Figure 5. PFD Output Test Conditions
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
40
30
20
100
80
V
R
= 3 V
DD
V
R
= 5 V
DD
–20°C
= 2.2 kΩ
BIAS
= 1.5 kΩ
25°C
BIAS
–20°C
75°C
25°C
60
75°C
40
10
0
20
0
1
2
3
0
1
2
3
4
5
VCO IN – VCO Control Voltage – V
VCO IN – VCO Control Voltage – V
Figure 6
Figure 7
VCO OSCILLATION FREQUENCY
vs
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
40
30
20
80
60
40
20
0
V
R
= 5 V
DD
V
R
= 3 V
DD
= 2.2 kΩ
BIAS
= 3.3 kΩ
BIAS
–20°C
–20°C
75°C
75°C
25°C
25°C
10
0
0
1
2
3
0
1
2
3
4
5
VCO IN – VCO Control Voltage – V
VCO IN – VCO Control Voltage – V
Figure 8
Figure 9
10
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
40
30
20
80
60
40
20
0
V
R
= 3 V
DD
V
R
= 5 V
= 3.3 kΩ
BIAS
DD
= 4.3 kΩ
BIAS
75°C
25°C
–20°C
25°C
10
0
75°C
–20°C
0
1
2
3
0
1
2
3
4
5
VCO IN – VCO Control Voltage – V
VCO IN – VCO Control Voltage – V
Figure 10
Figure 11
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
vs
BIAS RESISTOR
BIAS RESISTOR
30
25
60
50
V
= 3 V
V
= 5 V
DD
DD
VCO IN = 1/2 V
T
A
VCO IN = 1/2 V
DD
T = 25°C
A
DD
= 25°C
20
15
10
40
30
20
2
2.5
3
3.5
4
4.5
1.5
2
2.5
3
3.5
R
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
BIAS
Figure 12
Figure 13
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
BIAS RESISTOR
0.4
0.4
0.3
0.2
0.1
0
V
= 3 V
DD
VCO IN = 1/2 V
V
= 5 V
DD
DD
= –20°C to 75°C
VCO IN = 1/2 V
DD
T = –20°C to 75°C
A
T
A
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
1.5
2
2.5
3
3.5
2.2
R
BIAS
3.3
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
Figure 14
Figure 15
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
vs
VCO SUPPLY VOLTAGE
VCO SUPPLY VOLTAGE
48
44
24
R
= 2.2 kΩ
R
= 3.3 kΩ
BIAS
BIAS
VCO IN = 1/2 V
T
A
VCO IN = 1.5 V
= 25°C
DD
= 25°C
T
A
22
40
36
32
20
18
16
4.75
5
5.25
3.05
3
3.15
V – VCO Supply Voltage – V
DD
V
DD
– VCO Supply Voltage – V
Figure 16
Figure 17
12
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE COEFFICIENT OF VCO
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
OSCILLATION FREQUENCY
vs
vs
BIAS RESISTOR
BIAS RESISTOR
0.05
0.04
0.03
V
= 2.85 V to 3.15 V
V
= 4.75 V to 5.25 V
DD
VCO IN = 1/2 V
DD
VCO IN = 1/2 V
DD
DD
T
A
= 25°C
T
A
= 25°C
0.01
0.02
0.01
0
0.005
0
1.5
2
2.5
3
3.5
2
2.5
3
3.5
4
4.5
R
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
BIAS
Figure 18
Figure 19
RECOMMENDED LOCK FREQUENCY
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
(×1 OUTPUT)
vs
BIAS RESISTOR
BIAS RESISTOR
60
50
40
30
V
T
A
= 2.85 V to 3.15 V
V
T
A
= 4.75 V to 5.25 V
= –20°C to 75°C
DD
= –20°C to 75°C
DD
25
20
15
30
20
10
10
2
2.5
3
3.5
4
4.5
1.5
2
2.5
3
3.5
R
– Bias Resistor – kΩ
BIAS
R
BIAS
– Bias Resistor – kΩ
Figure 20
Figure 21
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
RECOMMENDED LOCK FREQUENCY
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
(×1/2 OUTPUT)
vs
BIAS RESISTOR
30
25
20
V
= 4.75 V to 5.25 V
DD
= –20°C to 75°C
15
V
= 2.85 V to 3.15 V
DD
= –20°C to 75°C
T
A
T
A
SELECT = V
DD
SELECT = V
DD
12.5
10
15
10
5
7.5
5
1.5
2
2.5
3
3.5
2
2.5
3
3.5
4
4.5
R
– Bias Resistor – kΩ
BIAS
R
– Bias Resistor – kΩ
BIAS
Figure 22
Figure 23
14
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
gain of VCO and PFD
Divider
(K = 1/N)
N
Figure 24 is a block diagram of the PLL. The
countdown N value depends on the input
frequency and the desired VCO output frequency
according to thesystemapplicationrequirements.
The K and K values are obtained from the
PFD
(K )
p
VCO
(K )
V
f REF
p
V
operating characteristics of the device as shown
in Figure 24. K is defined from the phase detector
TLC2932
LPF
p
V
and V
specifications and the equation
OL
OH
shown in Figure 24(b). K is defined from
V
(K )
f
Figures 8, 9, 10, and 11 as shown in Figure 24(c).
V
OH
(a)
The parameters for the block diagram with the
units are as follows:
–2π –π
0
π
2π
f
MAX
K : VCO gain (rad/s/V)
V
V
OH
K : PFD gain (V/rad)
p
K : LPF gain (V/V)
f
f
K : count down divider gain (1/N)
N
MIN
V
OL
Range of
Comparison
external counter
V
V
IN MIN
IN MAX
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
V
– V
OL
2π(f
– f )
OH
4π
MAX MIN
– V
K
=
K
=
p
V
V
IN MAX
IN MIN
(b)
(c)
Figure 24. Example of a PLL Block Diagram
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V applied to the VCO IN terminal. However,
DD
for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply and a resistor value of 2.5
kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice
but a carbon-compositiion resistor can be used with excellent results also. A 0.22 µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
0.8 K
K
K ( )
p
H
V
f
Where
K (∞) = the filter transfer function value at ω = ∞
f
15
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consultedforadditionalinformation. Lag-leadfiltersoractivefiltersareoftenused. ExamplesofLPFsareshown
in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or less than one tenth the value of C1.
C2
R1
V
I
V
O
R1
C1
R2
–
V
I
V
O
C2
R2
C1
T1 = C1R1
T2 = C1R2
C1
T1 = C1R1
V
I
A
V
O
R1
T1 = C1R1
T2 = C1R2
(a) LAG FILTER
(b) LAG-LEAD FILTER
(c) ACTIVE FILTER
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;
V
O
1
s
s
T2
V
(
)
T1 T2
1
IN
Where
T1
R1 C1 and T2
R2 C1
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since the
integrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B
terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
1
s
R2 C1
R1 C1
F(s)
s
Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of this
system to a unit step are shown in Figure 27.
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
16
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
basic design example (continued)
Assume the loop has to have a 100 µs settling time (t ) with a countdown N = 8. Using the Type 1, second order
s
response curves of Figure 26, a value of 4.5 radians is selected for ω t with a damping factor of 0.7. This
n s
selection gives a good combination for settling time, accuracy, and loop gain margin. The initial parameters are
summarized in Table 5. The loop constants, K and K , are calculated from the data sheet specifications and
V
p
Table 6 shows these values.
The natural loop frequency is calculated as follows:
Since
t
4.5
n s
Then
4.5
100
45 k-radians sec
n
s
Table 5. Design Parameters
PARAMETER
SYMBOL
VALUE
UNITS
Division factor
N
t
8
Lockup time
100
4.5
0.7
µs
Radian value to selected lockup time
Damping factor
ω t
n
rad
ζ
Table 6. Device Specifications
PARAMETER
SYMBOL
VALUE
UNITS
Mrad/V/s
MHz
MHz
V
VCO gain
76.6
f
f
70
MAX
K
V
20
5
MIN
V
V
IN MAX
0.9
V
IN MIN
PFD gain
K
p
0.342357
V/rad
Table 7. Calculated Values
PARAMETER
SYMBOL
VALUE
UNITS
rad/sec
Natural angular frequency
ω
45000
3.277
n
K = (K • K )/N
Mrad/sec
V
p
Lag-lead filter
15870
16000
Calculated value
Nearest standard value
R1
Ω
Calculated value
Nearest standard value
308
300
R2
C1
Ω
Selected value
0.1
µF
17
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
Using the low-pass filter in Figure 25(b) and divider ratio N, the transfer function for phase and frequency are
shown in equations 1 and 2. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider value N. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is
K
K
2(s)
1(s)
p
(
V
1
s
T2
T2
(1)
)
N
T1 T2
K
K
K
K
p
p
V
V
2
s
s
1
N (T1 T2)
N (T1 T2)
and the transfer function for frequency is
F
F
K
K
OUT(s)
REF(s)
p
V
)
1
s
T2
T2
(2)
(
T1 T2
K
K
K
K
p
p
V
V
2
s
s
1
N (T1 T2)
N (T1 T2)
2
2
The standard two-pole denominator is D = s + 2 ζ ω s + ω and comparing the coefficients of the denominator
n
n
of equation 1 and 2 with the standard two-pole denominator gives the following results.
K
K
p
V
n
N
(T1 T2)
Solving for T1 + T2
K
K
p
V
2
(3)
T1 T2
N
n
and by using this value for T1 + T2 in equation 3 the damping factor is
n
2
N
T2
K
K
p
V
solving for T2
T2
2
N
–
K
K
p
V
then by substituting for T2 in equation 3
K
K
p
2
2
V
N
T1
–
K
K
n
N
p
V
n
18
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TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
2
N
1
C1
R2
R1
K
K
n
p
V
K
K
v
p
2
N
1
C1
2
K
p
K
n
N
V
n
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculated
values are listed in Table 7.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
1.9
1.8
1.7
1.6
= 0.1
= 0.2
= 0.3
= 0.4
= 0.5
1.5
1.4
1.3
= 0.6
= 0.7
1.2
1.1
1
= 0.8
0.9
0.8
= 1.0
= 1.5
0.7
0.6
0.5
= 2.0
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ω
ω t = 4.5
n s
nt
Figure 26. Type 1 Second-Order Step Response
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
ζ = 0.1
ζ = 0.2
ζ = 0.3
1.5
1.4
1.3
ζ = 0.4
ζ = 0.5
ζ = 0.6
ζ = 0.7
1.2
1.1
1
0.9
0.8
ζ = 0.8
ζ = 1.0
0.7
0.6
0.5
ζ = 2.0
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ω
nt
Figure 27. Type 2 Second-Order Step Response
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
APPLICATION INFORMATION
AV
DD
V
DD
VCO
1
2
3
4
5
6
7
14
13
12
11
10
9
LOGIC V
SELECT
(Digital)
VCO V
DD
DD
†
R1
1/2 f
BIAS
osc
0.22 µF
R3
C1
VCO OUT
FIN–A
VCO IN
REF IN
DGND
C2
R2
VCO GND
FIN–B
VCO INHIBIT
AGND
PFD OUT
PFD INHIBIT
NC
Phase
Comparator
8
LOGIC GND (Digital)
DGND
Divide
By
N
S3
S4
S5
R4
R5
R6
DGND
DV
DD
†
R
resistor
BIAS
Figure 28. Evaluation and Operation Schematic
PCB layout considerations
The TLC2932 contains a high frequency analog oscillator; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2932 user:
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC V
and VCO V
should be separate PCB traces and connected to the best filtered supply point
DD
DD
available in the system to minimize supply cross-coupling.
VCO V to GND and LOGIC V to GND should be decoupled with a 0.1-µF capacitor placed as close
DD
DD
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,17
0,65
M
0,13
14
8
0,15 NOM
4,70
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°–8°
0,70
A
0,40
Seating Plane
0,10
1,20 MAX
0,10 MIN
PINS **
8
14
16
20
24
28
DIM
3,30
2,90
5,30
4,90
5,30
4,90
6,80
6,40
8,10
7,70
10,00
9,60
A MAX
A MIN
4040064/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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