TLC2943IDB [TI]
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK; 高性能双锁相环积木
| 型号： | TLC2943IDB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK |
| 文件： | 总27页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
DB PACKAGE
(TOP VIEW)
Dual TLC2933 by Multichip Module
(MCM) Technology
Voltage-Controlled Oscillators (VCO)
Section
– Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
– Recommended Lock Frequency
Range
LOGIC_1 V
VCO_1 V
DD
1
DD
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
TEST_1
R
_1
2
BIAS
VCO_1 OUT
VCOIN_1
3
F
F
-A_1
-B_1
VCO_1 GND
4
IN
IN
VCO_1 INHIBIT
5
PFD_1 OUT
PFD_1 INHIBIT
6
– 37 MHz to 60 MHz
LOGIC_1 GND
NC
7
(V
to 75°C)
= 3.3 V ± 0.15 V, T = –20°C
DD
A
GND
NC
GND
NC
8
9
– 43 MHz to 100 MHz
NC
NC
10
11
12
13
14
15
(V
to 75°C)
= 5 V ± 0.25 V, T = –20°C
DD
A
NC
NC
GND
GND
Includes a High Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump
Independent VCO, PFD Power-Down
Mode
LOGIC_2 V
VCO_2 V
DD
DD
TEST_2
R
_2
BIAS
VCO_2 OUT
VCOIN_2
F
F
-A_2 16
-B_2 17
VCO_2 GND
VCO_2 INHIBIT
PFD_2 INHIBIT
NC
IN
IN
PFD_2 OUT 18
19
description
LOGIC_2 GND
The TLC2943 is a multichip module product that
uses two TLC2933 chips. The TLC2933 chip is
composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector
(PFD). The oscillation frequency range of the VCO is set by an external bias resistor (R BIAS ). The high-speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used
as a power-down mode. The high-speed and stable VCO characteristics of the TLC2933 make the TLC2943
suitable for use in dual high-performance phase-locked loop (PLL) systems.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE (DB)
TLC2943IDB
–20°C to 75°C
TLC2943IDBR (Tape and Reel)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
functional block diagram
VCO_1 OUT
VCO_2 OUT
VCO_1 INHIBIT
VCO_2 INHIBIT
VCO_1
PFD_1
VCO_2
PFD_2
VCOIN_2
VCOIN_1
F
F
-A_1
-B_1
F
F
-A_2
-B_2
IN
IN
IN
IN
PFD_1 INHIBIT
PFD_2 INHIBIT
PFD_1 OUT
PFD_2 OUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
8, 31
12, 27
Common GND for chip 1
GND
Common GND for chip 2
Reference frequency signal input and comparison frequency signal input for PFD_1. fREF–IN_1 inputs
F
F
–A_1,
–B_1
4
5
IN
IN
I
I
to F -A_1, and comparison frequency input from external counter logic to F –B_1, for a lag-lead filter
IN
IN
use as LPF.
Reference frequency signal input and comparison frequency signal input for PFD_2. fREF–IN_2 inputs
F
IN
F
IN
–A_2,
–B_2
16
17
toF -A_2, andcomparisonfrequencyinputfromexternalcounterlogictoF -B_2, foralag-leadfilteruse
IN
as LPF.
IN
LOGIC_1 GND
LOGIC_2 GND
7
Ground for the internal logic of chip 1
Ground for the internal logic of chip 2
19
Power supply for the internal logic of chip 1. This power supply should be separate from VCO V
reduce cross-coupling between supplies.
to
to
DD
LOGIC_1 V
LOGIC_2 V
1
DD
DD
Power supply for the internal logic of chip 2. This power supply should be separate from VCO V
reduce cross-coupling between supplies.
DD
13
9, 10,
11, 20,
28, 29,
30, 32
NC
No internal connection
PFD inhibit control for chip 1. When PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state,
see Table 2.
PFD_1 INHIBIT
PFD_2 INHIBIT
33
21
I
I
PFD inhibit control for chip 2. When PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state,
see Table 2.
PFD_1 OUT
PFD_2 OUT
6
O
O
PFD output of chip 1. When the PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state.
PFD output of chip 2. When the PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state.
18
Bias supply for VCO_1. An external resistor (R
) between VCO_1 V
and BIAS_1 supplies bias for
BIAS
adjusting the oscillation frequency range of VCO_1.
DD
R
R
_1
37
25
I
I
BIAS
BIAS
Bias supply for VCO_2. An external resistor (R
BIAS
adjusting the oscillation frequency range of VCO_2.
) between VCO_2 V
and BIAS_2 supplies bias for
DD
_2
TEST_1
2
Test terminal. TEST connects to LOGIC_1 GND for normal operation.
Test terminal. TEST connects to LOGIC_2 GND for normal operation.
GND for VCO_1
TEST_2
14
35
23
34
22
3
VCO_1 GND
VCO_2 GND
VCO_1 INHIBIT
VCO_2 INHIBIT
VCO_1 OUT
VCO_2 OUT
GND for VCO_2
I
VCO inhibit control for chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low (see Table 1).
VCO inhibit control for chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low (see Table 1).
VCO output of chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low.
I
O
O
15
VCO output of chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low.
Power supply for VCO_1. This power supply should be separate from LOGIC V
cross-coupling between supplies.
to reduce
to reduce
DD
VCO_1 V
VCO_2 V
VCOIN_1
VCOIN_2
38
26
36
24
DD
Power supply for VCO_2. This power supply should be separate from LOGIC V
cross-coupling between supplies.
DD
DD
VCO_1 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
I
I
VCO_2 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
detailed description
MCM (multichip module) technology for TLC2943
The TLC2943 is a multichip module (MCM) product that uses two TLC2933 chips. Inside the package, two chips
are completely isolated by a special formed lead-frame. Therefore,when using the TLC2943 in two
asynchronous PLL circuits, there is no performance degradation by electrical interference between chips inside
the package. So, the same performance as TLC2933 can be easily expected by using TLC2943.
The NC terminals in the middle on both sides of the package are to achieve complete isolation inside the
package. To get the best performance from this MCM technology, it is better to make a careful board layout of
the external power supply, ground, and signal lines.
voltage controlled oscillator (VCO)
VCO_1 and VCO_2 have the same typical characteristics. Each VCO oscillation frequency is determined by
anexternalresistor(R
)connectedbetweentheVCOV andtheBIASterminals.Theoscillationfrequency
BIAS
DD
and range depend on this resistor value. The bias resistor value for the minimum temperature coefficient is
nominally 2.2 kΩ with V = 3.3 V and nominally 2.4 kΩ with V = 5 V. For the lock frequency range, refer to
DD
DD
the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control
voltage.
VCO Oscillation Frequency (f
)
osc
VCO Oscillation Frequency Range
BIAS Resistor (R
BIAS)
VCO Control Voltage (V
COIN
)
Figure 1. VCO_1 and VCO_2 Oscillation Frequency
VCO inhibit function
Each VCO has an externally controlled inhibit function that inhibits the VCO output. The VCO oscillation is
stopped during a high level on VCOINHIBIT, so the high level can also be used as the power-down mode. The
VCO output maintains a low level during the power-down mode (see Table 1 and Table 2).
Table 1. VCO_1 Inhibit Function
VCO_1 INHIBIT
VCO_1 OSCILLATOR
VCO_1 OUT
Active
VCO_1 I
DD
Low
Active
Stop
Normal
High
Low
Power down
Table 2. VCO_2 Inhibit Function
VCO_2 INHIBIT
VCO_2 OSCILLATOR
VCO_2 OUT
Active
VCO_2 I
DD
Low
Active
Stop
Normal
High
Low
Power down
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
detailed description (continued)
phase frequency detector (PFD)
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to F -A and F -B as shown in Figure 2. Nominally the
IN
IN
reference is supplied to F -A, and the frequency from the external counter output is fed to F -B. For clock
IN
IN
recovery PLL systems, other types of phase detectors should be used.
F
-A_1, 2
-B_1, 2
IN
IN
F
VOH
HI-Z
VOL
PFD_1, 2 OUT
Figure 2. PFD Function Timing Chart
PFD output control
A high level on PFD INHIBIT places the PFD OUT in the high impedance state and the PFD stops phase
detectionasshowninTable 3 and Table4. AhighlevelonPFDinhibitalsocanbeusedasthepower-downmode
for the PFD.
Table 3. PFD_1 Inhibit Function
PFD_1 INHIBIT
PFD_1
Active
Stop
PFD_1 OUT
Active
PFD_1 I
DD
Low
Normal
High
Hi-Z
Power down
Table 4. PFD_2 Inhibit Function
PFD_2 INHIBIT
PFD_2
Active
Stop
PFD_2 OUT
Active
PFD_2 I
DD
Low
Normal
High
Hi-Z
Power down
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
internal function block diagram
BIAS
Resistor
VCO OUT
BIAS
Circuit
Output
Buffer
VCO Control
V
COIN
Figure 3. VCO Block Schematic (VCO_1, VCO_2)
Charge Pump
F
F
-A
-B
IN
PFD OUT
Detector
IN
Figure 4. PFD Block Schematic (PFD_1, PFD_2)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage (each supply), V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Input voltage range (each input), V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to V
+ 0.5 V
I
DD
Input current (each input), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
Output current (each output), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
O
Continuous total power dissipation at (or below) T = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1160 mW
A
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 9.3 mW/°C.
recommended operating conditions
MIN NOM
MAX
3.15
3.45
5.25
UNIT
V
DD
V
DD
V
DD
= 3 V
2.85
3.15
4.75
0
3
3.3
5
Supply voltage (each supply, see Notes 3 and 4 ), V
DD
= 3.3 V
= 5 V
V
Input voltage range (input except for VCOIN_1, 2), V
V
DD
V
mA
V
I
Output current (each output), I
Control voltage, VCOIN
0
±2
O
1
V
DD
55
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3 V
37
Clock frequency, f
= 3.3 V
= 5 V
37
60
MHz
43
100
2.7
3.0
3.0
75
= 3 V
1.8
1.8
2.2
–20
Oscillation frequency range set resistor (each RBIAS), R
Top operating temperature range
VCO
= 3.3 V
= 5 V
kΩ
BIAS
C
NOTES: 3. It is recommended that the logic supply terminal (LOGIC V ) and the VCO supply terminal (VCO V ) be at the same voltage and
DD DD
separated from each other.
4. Insert bypass capacitors locating the nearest point to each power supply terminal.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 3 V
DD
VCO section
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
V
V
V
I
I
= –2 mA
= 2 mA
2.4
OH
OH
Low-level output voltage
0.3
2.1
±1
V
OL
OL
Positive input threshold voltage
Input current
0.9
1.5
V
(TH+)
I
I
V = V or GND
I DD
µA
MΩ
µA
mA
Z
VCOIN input impedance
VCOIN = 1/2V
See Note 5
See Note 6
10
0.01
5.1
(VCOIN)
DD(INH)
DD(VCO)
DD
I
I
VCO supply current (inhibit) (for one chip)
VCO supply current (for one chip)
1
15
NOTES: 5. The current into VCO V
and LOGIC V
DD
when VCO INHIBIT = V
when VCO IN = 1/2 V
DD BIAS
and PFD INHIBIT is high.
DD
DD
DD
, R
6. The current into VCO V
is high.
and LOGIC V
= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
DD
PFD section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN NOM
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
2.7
OH
OH
= 2 mA
0.2
V
OL
OL
I
High-impedance state output current
PFD INHIBIT = high,
V
O
= V or GND
DD
±1
µA
V
OZ
V
High-level input voltage at F –A, F –B
2.1
IH
IL
IN IN
V
Low-level input voltage at F –A, F –B
IN IN
0.9
2.1
V
Positive input threshold voltage at PFD
INHIBIT
V
0.9
1.5
V
(TH+)
C
Input capacitance at F –A, F –B
IN IN
5
10
pF
MΩ
mA
I
Z
I
Input impedance at F –A, F –B
IN IN
I
PFD supply current
See Note 7
0.7
4
DD(PFD)
NOTE 7: Thecurrent into LOGIC V
when F –A and F –B = 30 MHz (V I(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open,
DD
and VCO OUT is inhibited.
IN
IN
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (continued)
= 3.3 V
DD
VCO section
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
V
V
V
I
I
= –2 mA
= 2 mA
2.7
OH
OH
Low-level output voltage
0.4
2.3
±1
V
OL
OL
Positive input threshold voltage
Input current
1
1.65
V
(TH+)
I
I
V = V or GND
I DD
µA
MΩ
µA
mA
Z
VCOIN input impedance
VCOIN = 1/2V
See Note 5
See Note 6
10
0.01
6.2
(VCOIN)
DD(INH)
DD(VCO)
DD
I
I
VCO supply current (inhibit) (for one chip)
VCO supply current (for one chip)
1
16
NOTES: 5. The current into VCO V
and LOGIC V
DD
when VCO INHIBIT = V
when VCO IN = 1/2 V
DD BIAS
and PFD INHIBIT is high.
DD
DD
DD
, R
6. The current into VCO V
is high.
and LOGIC V
= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
DD
PFD section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN NOM
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
3
OH
OH
= 2 mA
0.2
V
OL
OL
I
High-impedance state output current
PFD INHIBIT = high,
V
O
= V or GND
DD
±1
µA
V
OZ
V
High-level input voltage at F –A, F –B
2.3
IH
IL
IN IN
V
Low-level input voltage at F –A, F –B
IN IN
1
V
Positive input threshold voltage at PFD
INHIBIT
V
(TH+)
1
1.65
2.3
V
C
Input capacitance at F –A, F –B
IN IN
5
10
pF
MΩ
mA
I
Z
I
Input impedance at F –A, F –B
IN IN
I
PFD supply current
See Note 8
0.8
5
DD(PFD)
NOTE 8: The current into LOGIC V
when F –A and F –B = 30 MHz (V I(PP) = 3.3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT
IN IN
DD
open, and VCO OUT is inhibited.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (continued)
= 5 V
DD
VCO section
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
V
V
V
I
I
= –2 mA
= 2 mA
4.5
OH
OH
Low-level output voltage
0.5
3.5
±1
V
OL
OL
Positive input threshold voltage
Input current
1.5
2.5
V
(TH+)
I
I
V = V or GND
I DD
µA
MΩ
µA
mA
Z
VCOIN input impedance
VCOIN = 1/2V
See Note 5
See Note 6
10
0.01
14
(VCOIN)
DD(INH)
DD(VCO)
DD
I
I
VCO supply current (inhibit) (for one chip)
VCO supply current (for one chip)
1
35
NOTES: 5. The current into VCO V
and LOGIC V
DD
when VCO INHIBIT = V
when VCO IN = 1/2 V
DD BIAS
and PFD INHIBIT is high.
DD
DD
DD
, R
6. The current into VCO V
is high.
and LOGIC V
= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
DD
PFD section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN NOM
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
4.5
OH
OH
= 2 mA
0.2
V
OL
OL
I
High-impedance state output current
PFD INHIBIT = high,
V
O
= V or GND
DD
±1
µA
V
OZ
V
High-level input voltage at F –A, F –B
3.5
IH
IL
IN IN
V
Low-level input voltage at F –A, F –B
IN IN
1.5
3.5
V
Positive input threshold voltage at PFD
INHIBIT
V
1.5
2.5
V
(TH+)
C
Input capacitance at F –A, F –B
IN IN
7
10
pF
MΩ
mA
I
Z
I
Input impedance at F –A, F –B
IN IN
I
PFD supply current
See Note 9
2.6
8
DD(PFD)
NOTE 9: ThecurrentintoLOGICV
when F –AandF –B = 50 MHz (V I(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open,
IN IN
DD
and VCO OUT is inhibited.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
operating characteristics at V
= 3 V, T = 25°C (unless otherwise noted)
DD
A
VCO section
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
58
UNIT
MHz
µs
f
t
t
t
f
Oscillation frequency
Time to stable oscillation
Output rise time
Output fall time
R
= 2.4 kΩ,
BIAS
See Note 10
VCOIN = 1/2V
38
48
(OSC)
DD
10
(STB)
C
C
R
R
= 15 pF,
= 15 pF,
See Figure 5
See Figure 5
VCOIN = 1/2V
VCOIN = 1/2V
3.3
2
10
ns
r
L
L
8
ns
f
Duty cycle
= 2.4 kΩ,
45%
50%
55%
(DUTY)
BIAS
DD
DD
Temperature coefficient of oscillation
frequency
= 2.4 kΩ,
BIAS
f
0.03
0.04
%/°C
(TA)
Top = –20°C to 75°C
Supply voltage coefficient of oscillation
frequency supply
R
= 2.4 kΩ,
BIAS
= 2.85 V to 3.15 V
VCOIN = 1.5 V,
f
%/mV
(VDD)
V
DD
NOTE 10: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
PFD section
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
30
MHz
MAX
PLZ
PHZ
PZL
PZH
r
20
40
40
18
18
9
ns
ns
ns
18
See Figure 6 and Figure 7, and Table 5
4.1
4.8
3.1
1.5
C
= 15 pF,
See Figure 6
L
Fall time
9
f
11
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operating characteristics at V
= 3.3 V, T = 25°C (unless otherwise noted)
A
DD
VCO section
PARAMETER
TEST CONDITIONS
= 2.4 kΩ, VCOIN = 1/2V
MIN NOM
MAX
62
UNIT
MHz
µs
f
t
t
t
f
Oscillation frequency
Time to stable oscillation
Output rise time
Output fall time
R
42
52
(OSC)
BIAS
See Note 10
DD
10
(STB)
C
C
R
R
= 15 pF,
= 15 pF,
See Figure 5
See Figure 5
VCOIN = 1/2V
VCOIN = 1/2V
3
1.9
8
ns
r
L
L
7
ns
f
Duty cycle
= 2.4 kΩ,
45%
50%
55%
(DUTY)
BIAS
DD
DD
Temperature coefficient of oscillation
frequency
= 2.4 kΩ,
BIAS
f
0.03
0.04
%/°C
(TA)
Top = –20°C to 75°C
Supply voltage coefficient of oscillation
frequency supply
R
= 2.4 kΩ,
BIAS
= 3.15 V to 3.45 V
VCOIN = 1.65 V,
f
%/mV
(VDD)
V
DD
NOTE 10: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
PFD section
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
30
20
18
MHz
MAX
PLZ
PHZ
PZL
PZH
r
40
40
16
16
8
ns
ns
ns
See Figure 6 and Figure 7, and Table 5
C
= 15 pF,
See Figure 6
L
Fall time
8
f
12
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SLAS249 – NOVEMBER 1999
operating characteristics at V
= 5 V, T = 25°C (unless otherwise noted)
DD
A
VCO section
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
96
UNIT
MHz
µs
f
t
t
t
f
Oscillation frequency
Time to stable oscillation
Output rise time
Output fall time
R
= 2.4 kΩ,
BIAS
See Note 10
VCOIN = 1/2V
64
80
(OSC)
DD
10
(STB)
C
C
R
R
= 15 pF,
= 15 pF,
See Figure 5
See Figure 5
VCOIN = 1/2V
VCOIN = 1/2V
2.1
1.5
5
ns
r
L
L
4
ns
f
Duty cycle
= 2.4 kΩ,
45%
50%
55%
(DUTY)
BIAS
DD
DD
Temperature coefficient of oscillation
frequency
= 2.4 kΩ,
BIAS
f
0.03
0.02
%/°C
(TA)
Top = –20°C to 75°C
Supply voltage coefficient of oscillation
frequency supply
R
= 2.4 kΩ,
BIAS
= 4.75 V to 5.25 V
VCOIN = 2.5 V,
f
%/mV
(VDD)
V
DD
PFD section
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
50
MHz
MAX
PLZ
PHZ
PZL
PZH
r
20
40
40
10
10
5
ns
ns
ns
17
See Figure 6 and Figure 7, and Table 5
3.7
3.5
1.7
1.3
C
= 15 pF,
See Figure 6
L
Fall time
5
f
13
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
90%
90%
10%
10%
VCO OUT
t
t
f
r
Figure 5. VCO Output Voltage Waveform (Each VCO)
V
DD
V
DD
50%
F
F
-A
-B
IN
GND
GND
V
DD
V
DD
50%
IN
GND
GND
V
DD
V
DD
50%
50%
PFD INHIBIT
GND
GND
90%
50%
10%
V
V
90%
50%
10%
DD
DD
50%
50%
PFD OUT
GND
t
GND
t
t
t
PLZ
PZH
PHZ
PZL
t
t
f
r
Figure 6. PFD Output Voltage Waveform
14
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
Test Point
S1
R
L
DUT
C
L
S2
Figure 7. PFD Output Test Conditions
Table 5. PFD Output Test Conditions
PARAMETER
R
C
S1
S2
L
L
t
t
PZH
OPEN
CLOSE
PHZ
t
r
1 kΩ
15 pF
t
PZL
t
CLOSE
OPEN
PLZ
t
f
15
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HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATION FREQUENCY
OSCILLATION FREQUENCY
vs
vs
CONTROL VOLTAGE
CONTROL VOLTAGE
120
120
V
DD
R
= 3.3 V
V
DD
R
= 3.3 V
– 20°C
25°C
= 2.2 kΩ
= 1.8 kΩ
BIAS
BIAS
– 20°C
100
80
60
40
20
0
100
80
60
40
20
0
25°C
75°C
75°C
0.0
0.6
1.2
1.8
2.4
3.0
3.6
0.0
0.6
1.2
1.8
2.4
3.0
3.6
VCOIN – VCO Control Voltage – V
VCOIN – VCO Control Voltage – V
Figure 8
Figure 9
OSCILLATION FREQUENCY
vs
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
CONTROL VOLTAGE
120
120
V
DD
BIAS
= 3.3 V
= 2.7 kΩ
V
DD
BIAS
= 3.3 V
= 3.0 kΩ
R
R
100
80
60
40
20
0
100
80
60
40
20
0
75°C
25°C
75°C
25°C
– 20°C
– 20°C
0.0
0.6
1.2
1.8
2.4
3.0
3.6
0.0
0.6
1.2
1.8
2.4
3.0
3.6
VCOIN – VCO Control Voltage – V
VCOIN – VCO Control Voltage – V
Figure 10
Figure 11
16
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HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATION FREQUENCY
vs
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
CONTROL VOLTAGE
160
140
120
160
140
120
V
R
= 5 V
25°C
V
R
= 5 V
25°C
– 20°C
DD
DD
= 2.4 kΩ
= 2.2 kΩ
BIAS
BIAS
– 20°C
100
80
60
40
20
0
100
80
60
40
20
0
75°C
75°C
0.0
1
2
3
4
5
0.0
1
2
3
4
5
VCOIN – VCO Control Voltage – V
VCOIN – VCO Control Voltage – V
Figure 12
Figure 13
OSCILLATION FREQUENCY
vs
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
CONTROL VOLTAGE
160
140
120
160
140
120
25°C
V = 5 V
DD
V
R
= 5 V
DD
R = 3.0 kΩ
25°C
BIAS
= 2.7 kΩ
BIAS
– 20°C
100
80
60
40
20
0
100
80
60
40
20
0
75°C
75°C
– 20°C
0.0
1
2
3
4
5
0.0
1
2
3
4
5
VCOIN – VCO Control Voltage – V
VCOIN – VCO Control Voltage – V
Figure 14
Figure 15
17
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
TYPICAL CHARACTERISTICS
LOCK FREQUENCY RANGE
LOCK FREQUENCY RANGE
vs
vs
BIAS RESISTANCE
BIAS RESISTANCE
110
100
90
65
60
55
50
45
40
V
T
= 4.75 V – 5.25 V
= –20°C to 75°C
DD
A
V
T
A
= 3.15 V – 3.45 V
= –20°C to 75°C
DD
80
70
60
50
40
30
35
30
2.2 k
2.4 k
2.6 k
2.8 k
3 k
1.8 k
2.2 k
2.4 k
2.7 k
3 k
R
– BIAS Resistance – Ω
BIAS
R
– BIAS Resistance – Ω
BIAS
Figure 16
Figure 17
18
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
gain of VCO and PFD
Divider
(K = 1/N)
N
Figure 18 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The K
and K values are obtained from the operating
V
characteristics of the device as shown in
PFD
(K )
p
VCO
(K )
V
p
f REF
TLC2933
LPF
Figure 18. K is defined from the phase detector
p
OH
V
and V
specifications and the equation
OL
shown in Figure 18(b). K is defined from
Figures 8, 9, 10, and 11 as shown in Figure 18(c).
V
(K )
f
V
OH
(a)
The parameters for the block diagram with the
units are as follows:
–2π –π
0
π
2π
f
MAX
K : VCO gain (rad/s/V)
V
V
OH
K : PFD gain (V/rad)
p
K : LPF gain (V/V)
f
f
K : countdown divider gain (1/N)
N
MIN
V
OL
Range of
Comparison
external counter
V
V
IN MIN
IN MAX
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
V
– V
OL
2π(f
– f )
OH
4π
MAX MIN
– V
K
=
K
=
p
V
V
IN MAX
IN MIN
(b)
(c)
Figure 18. Example of a PLL Block Diagram
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V
applied to the VCO IN terminal. For the
DD
most accurate results, a metal-film resistor is the better choice, but a carbon-composition resistor can also be
used with excellent results. A 0.22 µF capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 17 is as follows:
0.8 K
K
K ( )
(1)
p
H
V
f
Where
K (∞) = the filter transfer function value at ω = ∞
f
19
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
References that include detailed design information about LPFs should be consulted for additional information.
Lag-lead filters or active filters are often used. Examples of LPFs are shown in Figure 19. When the active filter
of Figure 19(c) is used, the reference should be applied to F -B because of the amplifier inversion. Also, in
IN
practical filter implementations, C2 is used as additional filtering at the VCO input. The value of C2 should be
equal to or less than one tenth the value of C1.
C2
R1
V
I
V
O
R1
C1
R2
–
V
I
V
O
C2
R2
C1
T1 = C1R1
T2 = C1R2
C1
T1 = C1R1
V
I
A
V
O
R1
T1 = C1R1
T2 = C1R2
(a) LAG FILTER
(b) LAG-LEAD FILTER
(c) ACTIVE FILTER
Figure 19. LPF Examples for PLL
passive filter
The transfer function for the low-pass filter shown in Figure 17(b) is;
V
O
1
s
T2
(2)
V
(
)
T1 T2
1
s
IN
Where
T1
R1 C1 and T2
R2 C1
Using this filter makes the closed-loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 20.
active filter
When using the active filter shown in Figure 19(c), the phase detector inputs must be reversed, since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the F -B terminal
IN
and the output of the VCO divider should be applied to the input reference terminal, F -A.
IN
The transfer function for the active filter shown in Figure 19(c) is:
1
s
R2
R1 C1
C1
F(s)
(3)
s
Using this filter makes the closed-loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 21.
20
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
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APPLICATION INFORMATION
Using the lag-lead filter in Figure 19(b) and divider N value, the transfer function for phase and frequency are
shown in equations 4 and 5. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity,
while the feedback for frequency is 1/N.
Hence, the transfer function of Figure 19(a) for phase is
K
K
2(s)
1(s)
p
(
V
1
s
T2
T2
(4)
)
N
T1 T2
K
K
K
K
p
p
V
V
2
s
s
1
N
(T1 T2)
N
(T1 T2)
and the transfer function for frequency is
F
F
K
K
OUT(s)
p
V
)
1
s
T2
T2
(5)
(
T1 T2
K
K
K
K
V
REF(s)
p
N
p
V
2
s
s
1
(T1 T2)
N
(T1 T2)
2
2
The standard 2-pole denominator is D = s + 2 ζ ω s + ω and comparing the coefficients of the denominator
n
n
of equation (4) and (5) with the standard 2-pole denominator gives the following results.
K
K
(6)
p
V
n
N
(T1 T2)
Solving for T1 + T2
K
K
p
V
2
T1 T2
N
n
and by using this value for T1 + T2 in equation (6) the damping factor is
n
N
(7)
(8)
(9)
T2
2
K
K
p
V
solving for T2
T2
2
N
–
K
K
p
V
then by substituting for T2 in equation (6)
K
K
p
2
V
N
N
T1
–
2
K
K
n
p
V
n
21
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HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
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APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
2
N
1
C1
R2
R1
(10)
(11)
K
K
n
p
V
K
K
v
p
2
N
1
C1
2
K
p
K
n
N
V
n
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size.
22
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APPLICATION INFORMATION
1.9
1.8
1.7
1.6
= 0.1
= 0.2
= 0.3
= 0.4
= 0.5
1.5
1.4
1.3
= 0.6
= 0.7
1.2
1.1
1
= 0.8
0.9
0.8
= 1.0
= 1.5
0.7
0.6
0.5
= 2.0
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ω
ω t = 4.5
n s
nt
Figure 20. Type 1 Second-Order Step Response
23
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APPLICATION INFORMATION
1.9
1.8
1.7
1.6
ζ = 0.1
ζ = 0.2
ζ = 0.3
1.5
1.4
1.3
ζ = 0.4
ζ = 0.5
ζ = 0.6
ζ = 0.7
1.2
1.1
1
0.9
0.8
ζ = 0.8
ζ = 1.0
0.7
0.6
0.5
ζ = 2.0
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ω
nt
Figure 21. Type 2 Second-Order Step Response
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
PCB layout considerations
The TLC2943 contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2943 user:
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC V
and VCO V
should be separate PCB traces and connected to the best filtered supply point
DD
DD
available in the system to minimize supply cross-coupling.
VCO V to GND and LOGIC V to GND should be decoupled with a 0.1-µF capacitor placed as close
DD
DD
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
The evaluation and operation schematic for the TLC2943 is shown in Figure 22.
AV
DD
V
DD
PLL1
(digital)
VCO
VCO V
1
2
3
4
5
6
7
38
37
36
35
34
33
31
LOGIC V
TEST
DD
DD
†
R1
BIAS
0.22 µF
R3
C1
VCO OUT
VCOIN
REF IN
DGND
F
–A
–B
IN
IN
C2
R2
VCO GND
F
VCOINHIBIT
AGND
PFD OUT
PFD INHIBIT
GND
Phase
Comparator
LOGIC GND (Digital)
DGND
Divide
By
N
S1
S2
PLL2
DGND
R5
R6
DV
DD
†
R
resistor
BIAS
Figure 22. Evaluation and Operation Schematic
25
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
DIM
3,30
2,70
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /C 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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