TLC32044CFN [TI]
VOICE-BAND ANALOG INTERFACE CIRCUITS; 话带模拟接口电路
| 型号： | TLC32044CFN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | VOICE-BAND ANALOG INTERFACE CIRCUITS |
| 文件： | 总39页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
†
J
14-Bit Dynamic Range ADC and DAC
2’s Complement Format
OR N PACKAGE
(TOP VIEW)
Variable ADC and DAC Sampling Rate Up
to 19,200 Samples per Second
NU
RESET
EODR
NU
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NU
2
Switched-Capacitor Antialiasing Input Filter
and Output-Reconstruction Filter
IN+
3
FSR
IN–
4
DR
AUX IN+
AUX IN–
OUT+
OUT–
Serial Port for Direct Interface to
TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25,
5
MSTR CLK
6
7
V
DD
and TMS320C30 Digital Signal Processors
8
REF
DGTL GND
SHIFT CLK
EODX
9
V
Synchronous or Asynchronous ADC and
DAC Conversion Rates With Programmable
Incremental ADC and DAC Conversion
Timing Adjustments
CC+
10
11
12
13
14
V
CC–
ANLG GND
ANLG GND
NU
DX
WORD/BYTE
FSX
Serial Port Interface to SN74(54)299
Serial-to-Parallel Shift Register for Parallel
Interface to TMS(SMJ)32010,
TMS(SMJ)320C15, or Other Digital
Processors
NU
†
Refer to the mechanical data for the JT package.
FK OR FN PACKAGE
(TOP VIEW)
Internal Reference for Normal Operation
and External Purposes, or Can Be
Overridden by External Reference
CMOS Technology
4
3
2
1 28 27 26
DR
5
25
IN–
24 AUX IN+
description
MSTR CLK
6
V
7
23
22
21
20
19
AUX IN–
OUT+
The TLC32044 and TLC32045 are complete
analog-to-digital and digital-to-analog input and
output systems on single monolithic CMOS chips.
The TLC32044 and TLC32045 integrate a
bandpass switched-capacitor antialiasing input
filter, a 14-bit-resolution A/D converter, four
microprocessor-compatible serial port modes, a
14-bit-resolution D/A converter, and a low-pass
switched-capacitor output-reconstruction filter.
The devices offer numerous combinations of
master clock input frequencies and conversion/
sampling rates, which can be changed via digital
processor control.
DD
REF
DGTL GND
SHIFT CLK
EODX
8
9
OUT–
10
V
V
CC+
CC–
11
12 13 14 15 16 17 18
NU – Nonusable; no external connection should be made to
these terminals (see Table 2).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
AVAILABLE OPTIONS
PACKAGE
PLASTIC CHIP
CARRIER
(FN)
T
A
PLASTIC DIP
(N)
CERAMIC DIP
(J)
CHIP CARRIER
(FK)
TLC32044CFN
TLC32045CFN
TLC32044EFN
TLC32044CN
TLC32045CN
0°C to 70°C
–20°C to 85°C
–40°C to 85°C
–55°C to 125°C
TLC32044IN
TLC32045IN
TLC32044MJ
TLC32044MFK
description (continued)
Typical applications for the TLC32044 and TLC32045 include speech encryption for digital transmission,
speech recognition/ storage systems, speech synthesis, modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling
rate), analog interface for digital signal processors (DSPs), industrial process control, biomedical
instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation
recorders. Four serial modes, which allow direct interface to the TMS(SMJ)320C17, TMS(SMJ)32020,
TMS(SMJ)320C25, and TMS(SMJ)320C30 digital signal processors, are provided. Also, when the transmit and
receive sections of the analog interface circuit (AIC) are operating synchronously, it will interface to two
SN74(54)299 serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in
parallel to the TMS(SMJ)32010, TMS(SMJ)320C15, and other digital signal processors, or external FIFO
circuitry. Output data pulses are emitted to inform the processor that data transmission is complete or to allow
the DSP to differentiate between two transmitted bytes. A flexible control scheme is provided so that the
functions of the TLC32044 or TLC32045 can be selected and adjusted coincidentally with signal processing via
software control.
The antialiasing input filter comprises eighth-order and fourth-order CC-type (Chebyshev/elliptic transitional)
low-pass and high-pass filters, respectively. The input filter is implemented in switched-capacitor technology
and is preceded by a continuous time filter to eliminate any possibility of aliasing caused by sampled data
filtering. When only low-pass filtering is desired, the high-pass filter can be switched out of the signal path. A
selectable, auxiliary, differential analog input is provided for applications where more than one analog input is
required.
TheA/DandD/Aarchitecturesensurenomissingcodesandmonotonicoperation. Aninternalvoltagereference
is provided to ease the design task and to provide complete control over the performance of the TLC32044 or
TLC32045. The internal voltage reference is brought out to a terminal and is available to the designer. Separate
analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic
range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum.
The only exception is the DAC sample and hold, which utilizes pseudo-differential circuitry.
The output-reconstruction filter is an eighth-order CC-type (Chebyshev/elliptic transitional low-pass filter)
followed by a second-order (sin x)/x correction filter and is implemented in switched-capacitor technology. This
filter is followed by a continuous-time filter to eliminate images of the digitally encoded signal. The on-board
(sin x)/x correction filter can be switched out of the signal path using digital signal processor control, if desired.
The TLC32044C and TLC32045C are characterized for operation from 0°C to 70°C. The TLC32044E is
characterized for operation from –20°C to 85°C. The TLC32044I and TLC32045I are characterized for
operation from –40°C to 85°C. The TLC32044M is characterized for operation from –55°C to 125°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
functional block diagram
Filter
IN+
IN–
M
U
X
M
U
X
SERIAL
PORT
FSR
A/D
AUX IN +
AUX IN –
DR
Receive Section
EODR
MSTER CLK
SHIFT CLK
WORD/BYTE
DX
Internal
Voltage
Reference
Filter
FSX
OUT+
OUT–
EODX
sin x/x
Correction
M
U
X
D/A
Transmit Section
V
V
ANLG DTGL
V
CC+ CC–
DD
GND GND (Digital)
REF
RESET
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
ANLG GND
AUX IN+
NO.
17,18
24
Analog ground return for all internal analog circuits. Not internally connected to DGTL GND.
I
Noninverting auxiliary analog input stage. AUX IN+ can be switched into the bandpass filter and A/D
converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs
will replace the IN+ and IN– inputs. If the bit is a 0, the IN+ and IN– inputs will be used (see the AIC DX
data word format section).
AUX IN–
DGTL GND
DR
23
9
I
Inverting auxiliary analog input (see the above AUX IN+ description).
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
5
O
Data receive. DR is used to transmit the ADC output bits from the AIC to the TMS320 (SMJ320) serial port.
This transmission of bits from the AIC to the TMS320 (SMJ320) serial port is synchronized with the SHIFT
CLK signal.
DX
12
3
I
Data transmit. DX is used to receive the DAC input bits and timing and control information from the TMS320
(SMJ320). This serial transmission from the TMS320 (SMJ320) serial port to the AIC is synchronized with
the SHIFT CLK signal.
EODR
O
End of data receive. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODR is a low-going pulse that occurs immediately after the 16 bits of A/D information
have been transmitted from the AIC to the TMS320 (SMJ320) serial port. EODR can be used to interrupt
amicroprocessoruponcompletionofserialcommunications. Also, EODRcanbeusedtostrobeandenable
external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus
communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing,
EODR goes low after the first byte has been transmitted from the AIC to the TMS320 (SMJ320) serial port
and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to
differentiate between the two bytes as to which is first and which is second. EODR does not occur after
secondary communication.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
EODX
NO.
11
O
End of data transmit. (See the WORD/BYTE description and Serial Port Timing diagram.) During the
word-mode timing, EODX is a low-going pulse that occurs immediately after the 16 bits of D/A converter
and control or register information have been transmitted from the TMS320 (SMJ320) serial port to the AIC.
EODX can be used to interrupt a microprocessor upon the completion of serial communications. Also,
EODX can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external
FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel
shift registers. During the byte-mode timing, EODX goes low after the first byte has been transmitted from
the TMS320 (SMJ320) serial port to the AIC and is kept low until the second byte has been transmitted. The
DSP can use this low-going signal to differentiate between the two bytes as to which is first and which is
second.
4
O
O
Framesyncreceive. Intheserialtransmissionmodes, whicharedescribedintheWORD/BYTEdescription,
FSR is held low during bit transmission. When FSR goes low, the TMS320 (SMJ320) serial port begins
receiving bits from the AIC via DR of the AIC. The most significant DR bit is present on DR before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after
secondary communications.
FSR
FSX
14
Frame sync transmit. When FSX goes low, the TMS320 (SMJ320) serial port begins transmitting bits to the
AICviaDXoftheAIC.Inallserialtransmissionmodes,whicharedescribedintheWORD/BYTEdescription,
FSX is heldlowduringbittransmission(seeSerialPortTimingandInternalTimingConfigurationdiagrams).
IN+
26
25
6
I
I
I
Noninverting input to analog input amplifier stage
Inverting input to analog input amplifier stage
IN–
MSTR CLK
Master clock. MSTR CLK is used to derive all the key logic signals of the AIC, such as the shift clock, the
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration
diagram shows how these key signals are derived. The frequencies of these key signals are synchronous
submultiplesofthemasterclockfrequencytoeliminateunwantedaliasingwhenthesampledanalogsignals
are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal
Timing Configuration diagram).
OUT+
OUT–
REF
22
21
8
O
O
Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended configuration.
Inverting output of analog output power amplifier. OUT– is functionally identical with and complementary
to OUT+.
I/O
I
Internal voltage reference. An internal reference voltage is brought out on REF. An external voltage
reference can also be applied to REF.
RESET
2
Reset function. RESET is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. A reset
initiates serial communications between the AIC and DSP. A reset initializes all AIC registers including the
control register. After a negative-going pulse on RESET, the AIC registers are initialized to provide an 8-khz
data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA’
and RA’, are reset to 1. The control register bits are reset as follows (see AIC DX data word format section):
d9 = 1, d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1.
This initialization allows normal serial-port communication to occur between the AIC and DSP.
SHIFT CLK
10
O
Shiftclock. SHIFT CLK is obtained by dividing the master clock signal frequency by four. SHIFT CLK is used
to clock the serial data transfers of the AIC, described in the WORD/BYTE description below (see the Serial
Port Timing and Internal Timing Configuration diagrams).
V
V
V
7
Digital supply voltage, 5 V ±5%
DD
20
19
Positive analog supply voltage, 5 V ±5%
Negative analog supply voltage, –5 V ±5%
CC+
CC–
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
Terminal Functions (continued)
TERMINAL
NAME
WORD/BYTE
I/O
DESCRIPTION
NO.
13
I
Used in conjunction with a bit in the control register, WORD/BYTE is used to establish one of four serial
modes. These four serial modes are described below.
AIC transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive
sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format section),
the transmit and receive sections are asynchronous.
L
Serial port directly interfaces with the serial port of the DSP and communicates in two
8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).
1. FSX or FSR is brought low.
2. One 8-bit byte is transmitted or one 8-bit byte is received.
3. EODX or EODR is brought low.
4. FSX or FSR emits a positive frame-sync pulse that is four shift clock cycles wide.
5. One 8-bit byte is transmitted or one 8-bit byte is received.
6. EODX or EODR is brought high.
7. FSX or FSR is brought high.
H
Serial port directly interfaces with the serial ports of the TMS(SMJ)32020, TMS(SMJ)320C25, or
TMS(SMJ)320C30, and communicates in one 16-bit word. The operation sequence is as follows
(see Serial Port Timing diagrams):
1. FSX or FSR is brought low.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. FSX or FSR is brought high.
4. EODX or EODR emits a low-going pulse.
AIC transmit and receive sections are operated synchronously.
If the appropriate data bit in the control register is 1, the transmit and receive sections are configured to be
synchronous. Inthiscase, thebandpassswitched-capacitorfilterandtheA/Dconversiontimingarederived
fromtheTXcounterA,TXcounterB,andTA, TA’,andTBregisters,ratherthantheRXcounterA,RXcounter
B, and RA, RA’, and RB registers. In this case, the AIC FSX and FSR timing are identical during primary
data communication; however, FSR is not asserted during secondary data communication since there is
nonewA/Dconversionresult. Thesynchronousoperationsequencesareasfollows(seeSerialPortTiming
diagrams).
L
Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit
bytes. The operation sequence is as follows (see Serial Port Timing diagrams):
1. FSX and FSR are brought low.
2. One 8-bit byte is transmitted and one 8-bit byte is received.
3. EODX and EODR are brought low.
4. FSX and FSR emit positive frame-sync pulses that are four shift clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. EODX and EODR are brought high.
7. FSX and FSR are brought high.
H
Serial port directly interfaces with the serial port of the TMS(SJM)32020, TMS(SMJ)320C25, or
TMS320C30, and communicates in one 16-bit word. The operation sequence is as follows (see
Serial Port Timing diagrams):
1. FSX and FSR are brought low.
2. One 16-bit word is transmitted and one 16-bit word is received.
3. FSX and FSR are brought high.
4. EODX or EODR emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port with additional
NOR and AND gates interface to two SN74(54)299 serial-to-parallel shift registers. Interfacing the AIC to
the SN74(54)299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel,
data bus communications between the AIC and the digital signal processor. The operation sequence is the
same as the above sequence (see Serial Port Timing diagrams).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN+ and IN– input set is used; however, the auxiliary input
set, AUX IN + and AUX IN–, can be used if a second input is required. Each input set can be operated in either
differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain
for the IN +, IN–, AUX IN +, and AUX IN– inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either
input circuit can be selected via software control. It is important to note that a wide dynamic range is assured
by the differential internal analog architecture and by the separate analog and digital voltage supplies and
grounds.
A/D bandpass filter, A/D bandpass filter clocking, and A/D conversion timing
The A/D high-pass filter can be selected or bypassed via software control. The frequency response of this filter
is presented in the following pages. This response results when the switched-capacitor filter clock frequency
is 288 kHz and the A/D sample rate is 8 kHz. Several possible options can be used to attain a 288-kHz
switched-capacitorfilterclock. Whenthefilterclockfrequencyisnot288kHz, thelow-passfiltertransferfunction
is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The ripple bandwidth and 3-dB
low-frequency roll-off points of the high-pass section are 150 Hz and 100 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency scaled by the ratio of the A/D sample rate to 8 kHz.
The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many
options for attaining a 288-kHz bandpass switched-capacitor filter clock. These sections indicate that the RX
counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock for several master
clock input frequencies.
The A/D conversion rate is then attained by frequency dividing the 288-kHz bandpass switched-capacitor filter
clock with the RX counter B. Unwanted aliasing is prevented because the A/D conversion rate is an integral
submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.
A/D converter performance specifications
Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter
operating characteristics section of this data sheet. The realization of the A/D converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.
analog output
Theanalogoutputcircuitryisananalogoutputpoweramplifier. Bothnoninvertingandinvertingamplifieroutputs
are brought out. This amplifier can drive transformer hybrids or low-impedance loads directly in either a
differential or single-ended configuration.
D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter
is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output
of the (sin x)/xcorrectionfiltertoeliminatetheperiodicsampledatasignalinformation, whichoccursatmultiples
of the 288-kHz switched-capacitor filter clock. The continuous time filter also greatly attenuates any
switched-capacitor clock feedthrough.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
PRINCIPLES OF OPERATION
D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing (continued)
The D/A conversion rate is attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX
Counter B. Unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the
switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC) are
operatedasynchronously, thelow-passandbandpassfilterclocksareindependentlygeneratedfromthemaster
clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and receive
sections are operated synchronously, the low-pass filter clock drives both low-pass and bandpass filters. In
synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion timing
(see description of the WORD/BYTE in the Terminal Functions table.)
D/A converter performance specifications
Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The D/A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.
system frequency response correction
The (sin x)/x correction for the D/A converter zero-order sample-and-hold output can be provided by an
on-board second-order (sin x)/x correction filter. This (sin x)/x correction filter can be inserted into or deleted
from the signal path by digital signal processor control. When inserted, the (sin x)/x correction filter follows the
switched-capacitor low-pass filter. When the TB register (see Internal Timing Configuration section) equals 36,
the correction results of Figures 11 and 12 can be obtained.
The (sin x)/x correction can also be accomplished by deleting the on-board second-order correction filter and
performing the (sin x)/x correction in digital signal processor software. The system frequency response can be
correctedviaDSPsoftwareto±0.1-dBaccuracytoabandedgeof3000Hzforallsamplingrates. Thiscorrection
is accomplished with a first-order digital correction filter, which requires only seven TMS320 (SMJ320)
instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1%
and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the (sin x)/x correction section for more details).
serial port
The serial port has four possible modes that are described in detail in the Terminal Functions table. These
modes are briefly described below and in the functional description for WORD/BYTE.
•
•
•
•
The transmit and receive sections are operated asynchronously, and the serial port interfaces directly
with the DSP.
The transmit and receive sections are operated asynchronously, and the serial port interfaces directly
with the TMS(SMJ)32020, TMS(SMJ)320C25, and the TMS(SMJ)320C30.
The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the DSP.
The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS(SMJ)32020, TMS(SMJ)320C25, TMS(SMJ)320C30, or two SN74(54)299 serial-to-
parallel shift registers, which can then interface in parallel to the TMS(SMJ)32010, TMS(SMJ)320C15,
and SMJ320E15 to any other digital signal processor or to external FIFO circuitry.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
PRINCIPLES OF OPERATION
operation of TLC32044 or TLC32045 with internal voltage reference
The internal reference eliminates the need for an external voltage reference and provides overall circuit cost
reduction. Thus, the internal reference eases the design task and provides complete control over device
performance. The internal reference is brought out to a terminal and is available to the designer. To keep the
amount of noise on the reference signal to a minimum, an external capacitor can be connected between REF
and ANLG GND.
operation of TLC32044 or TLC32045 with external voltage reference
REF can be driven from an external reference circuit. This external circuit must be capable of supplying
250 µA and must be adequately protected from noise such as crosstalk from the analog input.
reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function initializes all AIC registers, including the control
register. After a negative-going pulse onRESET, the AIC is initialized. This initialization allows normal serial port
communications activity to occur between AIC and DSP (see AIC DX data word format section).
loopback
This feature allows the user to test the circuit remotely. In loopback, OUT+ and OUT– are internally connected
to the IN+ and IN–. Thus, the DAC bits (d15 to d2), which are transmitted to DX, can be compared with the ADC
bits (d15 to d2), which are received from DR. An ideal comparison would be that the bits on DR equal the bits
on DX. However, there are some difference in these bits due to the ADC and DAC output offsets. The loopback
feature is implemented with digital signal processor control by transmitting the appropriate serial port bit to the
control register (see AIC DX data word format section).
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
INTERNAL TIMING CONFIGURATION
MSTR CLK
5.184 MHz (1)
10.368 MHz (2)
SHIFT CLK
1.296 MHz (1)
2.592 MHz (2)
Divide by 4
20.736 MHz (1)
41.472 MHz (2)
TA’ Register
(6 bits)
(2’s compl)
XTAL
OSC
TMS(SMJ)320
DSP
TA Register
(5 bits)
Low-Pass/
(sin x/x
Correction
Switched
Capacitor Filter
CLK = 288-kHz
Square Wave
Optional External Circuitry
for Full Duplex Modems
Divide by 2
Adder/
Subtractor
(6 bits)
153.6-kHz
Clock (1)
TB Register
(6 bits)
Commercial
Divide
by 135
External
Front-End
Full-Duplex
Split-Band
d , d = 0,0
d , d = 0,1
0 1
0
1
TX Counter B
‡
‡
†
d , d = 1,1
d , d = 1,0
Filters
0
1
0 1
[TB = 40; 7.2 kHz]
[TB = 36; 8.0 kHz]
[TB = 30; 9.6 kHz]
[TB = 20; 14.4 kHz]
[TB = 15; 19.2 kHz]
D/A
Conversion
Frequency
TX Counter A
[TA = 9 (1)]
[TA = 18 (2)]
(6 bits)
576-kHz
Pulses
RA’ Register
(6 bits)
(2’s compl)
RA Register
(5 bits)
Low-Pass
Switched
Divide by 2
Capacitor Filter
CLK = 288-kHz
Square Wave
Adder/
Subtractor
(6 bits)
RB Register
(6 bits)
A/D
d , d = 0,0
d , d = 0,1
d , d = 1,0
0 1
0
1
0
1
RX Counter B
‡
‡
Conversion
Frequency/
High-Pass
Switched
Capacitor
Filter CLK
d , d = 1,1
0
1
[RB = 40; 7.2 kHz]
[RB = 36; 8.0 kHz]
[RB = 30; 9.6 kHz]
[RB = 20; 14.4 kHz]
[RB = 15; 19.2 kHz]
RX Counter A
[RA = 9 (1)]
[RA = 18 (2)]
(6 bits)
576-kHz
Pulses
†
‡
Split-band filtering can alternatively be performed after the analog input function via software in the TMS(SMJ)320.
These control bits are described in the AIC DX data word format section.
NOTE: Frequency 1 (20.736 MHz) is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular speech
and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as
submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal frequency,
aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages.
Frequency 2 (41.472 MHz) is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital signal
processors.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock
input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing
the master clock input signal frequency by four.
Low-pass:
Master Clock Frequency
SCF Clock Frequency (D A or A D path)
2
Contents of Counter A
SCF Clock Frequency (D A or A D path)
Contents of Counter B
Conversion Frequency
High-pass:
SCF Clock Frequency (A D Path)
Master Clock Frequency
A D Conversion Frequency
Shift Clock Frequency
4
TX counter A and TX counter B, which are driven by the master clock, determine the D/A conversion timing.
Similarly, RX counter A and RX counter B determine the A/D conversion timing. In order for the low-pass
switched-capacitor filter in the D/A path to meet its transfer function specifications, the frequency of its clock
input must be 288 kHz. If the clock frequency is not 288 kHz, the filter transfer function frequencies are
frequency-scaled by the ratios of the clock frequency to 288 kHz. Thus, to obtain the specified filter response,
the combination of master clock frequency and TX counter A and RX counter A values must yield a 288-kHz
switched-capacitor clock signal. This 288-kHz clock signal can then be divided by the TX counter B to establish
the D/A conversion timing.
The transfer function of the bandpass switched-capacitor filter in the A/D path is a composite of its high-pass
and low-pass section transfer functions. The high-frequency roll-off of the low-pass section meets the bandpass
filter transfer function specification when the low-pass section SCF is 288 kHz. Otherwise, the high-frequency
roll-off will be frequency-scaled by the ratio of the high-pass section’s SCF clock to 288 kHz. The low-frequency
roll-off of the high-pass section meets the bandpass filter transfer function specification when the A/D
conversion rate is 8 kHz. Otherwise, the low-frequency roll-off of the high-pass section is frequency-scaled by
the ratio of the A/D conversion rate to 8 kHz.
TX counter A and TX counter B are reloaded every D/A conversion period, while RX counter A and RX counter
B are reloaded every A/D conversion period. The TX counter B and RX counter B are loaded with the values
in the TB and RB registers, respectively. Via software control, the TX counter A can be loaded with either the
TA register, the TA register less the TA’ register, or the TA register plus the TA’ register. By selecting the TA
register less the TA’ register option, the upcoming conversion timing occurs earlier by an amount of time that
equals TA’ times the signal period of the master clock. By selecting the TA register plus the TA’ register option,
the upcoming conversion timing occurs later by an amount of time that equals TA’ times the signal period of the
master clock. The D/A conversion timing can be advanced or retarded. An identical ability to alter the A/D
conversion timing is provided. In this case, however, the RX counter A can be programmed via software control
with the RA register, the RA register less the RA’ register, or the RA register plus the RA’ register.
The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
explanation of internal timing configuration (continued)
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE description), then both
the low-pass and bandpass switched-capacitor filter clocks are derived from TX counter A. Also, both the D/A
and A/D conversion timing are derived from the TX counter A and TX counter B. When the transmit and receive
sections are configured to be synchronous, the RX counter A, RX counter B, RA register, RA’ register, and RB
registers are not used.
AIC DR or DX word bit pattern
A/D or D/A MSB,
1st bit sent
1st bit sent of 2nd byte
d8 d7 d6 d5
A/D or D/A LSB
d3 d2 d1
d15 d14 d13 d12 d11 d10 d9
d4
d0
AIC DX data word format section
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
primary DX serial communication protocol
Comments
←d15 (MSB) through d2 go to the D/A converter register
→
0
0
The TX and RX counter As are loaded with the TA
and RA register values. The TX and RX counter Bs
are loaded with TB and RB register values.
←d15 (MSB) through d2 go to the D/A converter register
→
0
1
The TX and RX counter As are loaded with the TA +
TA’ and RA + RA’ register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. LSBs d1 = 0 and d0 =1 cause the next D/A
and A/D conversion periods to be changed by the
addition of TA’ and RA’ master clock cycles, in which
TA’ and RA’ can be positive or negative or zero (refer
to Table 1).
←d15 (MSB) through d2 go to the D/A converter register
→
1
0
The TX and RX counter As are loaded with the TA –
TA’ and RA – RA’ register values. The TX and RX
counter Bs are loaded with the TB and RB register
values. LSBs d1 = 1 and d0 = 0 cause the next D/A
and A/D conversion periods to be changed by the
subtraction of TA’ and RA’ master clock cycles, in
which TA’ and RA’ can be positive or negative or zero
(refer to Table 1).
←d15 (MSB) through d2 go to the D/A converter register
→
1
1
The TX and RX counter As are loaded with the TA
and RA register converter register values. The TX
and RX counter Bs are loaded with the TB and RB
register values. After a delay of four shift clock
cycles,
a secondary transmission immediately
follows to program the AIC to operate in the desired
configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (primary communications) to the AIC initiates
secondary communications upon completion of the primary communications. Upon completion of the primary communication, FSX
remains high for four shift clock cycles and then goes low and initiates the secondary communication. The timing specifications for the
primary and secondary communications are identical. In this manner, the secondary communication, if initiated, is interleaved between
successive primary communications. This interleaving prevents the secondary communication from interfering with the primary
communications and DAC timing, thus preventing the AIC from skipping a DAC output. In the synchronous mode, FSR is not asserted
during secondary communications.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
secondary DX serial communication protocol
x x | ← to TA register → | x x | ← to RA register → |
x | ← to TA’ register → | x | ← to RA’ register → |
x | ← to TB register → | x | ← to RB register → |
0
0
1
1
0
1
0
1
d13 and d6 are MSBs (unsigned binary)
d14 and d7 are 2’s complement sign bits
d14 and d7 are MSBs (unsigned binary)
x
x
x
x
x
x
d9
x
d7 d6 d5 d4 d3 d2
Control
d2 = 0/1 deletes/inserts the A/D high-pass filter
Register
d3 = 0/1 disables/enables the loopback function
d4 = 0/1 disables/enables the AUX IN+ and AUX IN–
d5 = 0/1 asynchronous/synchronous transmit and receive sections
d6 = 0/1 gain control bits (see gain control section)
d7 = 0/1 gain control bits (see gain control section)
d9 = 0/1 delete/insert on-board second-order (sin x)/x correction filter
reset function
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
initializes all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on RESET initializes the AIC registers to provide an 8-kHz A/D and D/A conversion rate
for a 5.184 MHz master clock input signal. The AIC, except the control register, is initialized as follows (see AIC
DX data word format section):
INITIALIZED
REGISTER
REGISTER
VALUE (HEX)
TA
9
1
TA’
TB
RA
RA’
RB
24
9
1
24
The control register bits are reset as follows (see AIC DX data word format section):
d9 = 1, d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1
This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit and
receive sections are configured to operate synchronously and the user wishes to program different conversion
rates, only the TA, TA’, and TB register need to be programmed, since both transmit and receive timing are
synchronously derived from these registers (see the terminal functions table and AIC DX word format sections).
The circuit shown in Figure 1 provides a reset on power up when power is applied in the sequence given under
power-upsequence. Thecircuitdependsonthepowersuppliesreachingtheirrecommendedvaluesaminimum
of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC32044/TLC32045
5 V
V
CC+
200 kΩ
RESET
0.5 µF
V
CC–
–5 V
Figure 1. Power-Up Reset
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
power-up sequence
To ensure proper operation of the AIC and as a safeguard against latch-up, it is recommended that Schottky
diodes with forward voltages less than or equal to 0.4 V be connected from V to ANLG GND and from V
CC–
CC–
to DGTL GND (see Figure 21). In the absence of such diodes, power should be applied in the following
sequence:ANLGGNDandDGTLGND, V
after power up.
, thenV
andV . Also, noinputsignalshouldbeapplieduntil
CC–
CC+ DD
AIC responses to improper conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response of
the AIC to these conditions are presented in Table 1 below.
AIC register constraints
The following constraints are placed on the contents of the AIC registers:
1. TA register must be ≥ 4 in word mode (WORD/BYTE = high).
2. TA register must be ≥ 5 in byte mode (WORD/BYTE = low).
3. TA’ register can be either positive, negative, or zero.
4. RA register must be ≥ 4 in word mode (WORD/BYTE = high).
5. RA register must be ≥ 5 in byte mode (WORD/BYTE = low).
6. RA’ register can be either positive, negative, or zero.
7. (TA register ± TA’ register) must be > 1.
8. (RA register ± RA’ register) must be > 1.
9. TB register must be > 1.
Table 1. AIC Responses to Improper Conditions
IMPROPER CONDITION
AIC RESPONSE
Reprogram TX counter A with TA register value
TA register + TA’ register = 0 or 1
TA register – TA’ register = 0 or 1
TA register + TA’ register < 0
MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX counter A, i.e., TA
register + TA’ register + 40 hex is loaded into TX counter A.
RA register + RA’ register = 0 or 1
RA register – RA’ register = 0 or 1
Reprogram RX counter A with RA register value
RA register + RA’ register = 0 or 1
MODULO 64 arithmetic is used to ensure that a positive value is loaded into RX counter A, i.e., RA
register + RA’ register + 40 hex is loaded into RX counter A.
TA register = 0 or 1
RA register = 0 or 1
AIC is shut down.
TA register < 4 in word mode
TA register < 5 in byte mode
RA register < 4 in word mode
RA register < 5 in byte mode
The AIC serial port no longer operates.
TB register = 0 or 1
Reprogram TB register with 24 hex
Reprogram RB register with 24 hex
Hold last DAC output
RB register = 0 or 1
AIC and DSP cannot communicate
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
improper operation due to conversion times being too close together
If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the AIC operates
improperly. In this situation, the second D/A conversion frame sync occurs too quickly and there is not enough
time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly
programmed or if the A + A’ register or A – A’ register result is too small. When incrementally adjusting the
conversion period via the A + A’ register options, the designer should be careful not to violate this requirement
(see following diagram).
t
1
t
2
Frame Sync FSX
or
FSR
Ongoing
Conversion
t
2
– t
1/19.2 kHz
1
asynchronous operation — more than one receive frame sync occurring between two transmit
frame syncs
When incrementally adjusting the conversion period via the A + A’ or A – A’ register options, a specific protocol
is followed. The command to use the incremental conversion period adjust option is sent to the AIC during a
FSX frame sync. The ongoing conversion period is then adjusted. However, either receive conversion period
A or B can be adjusted. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between
t and t , the receive conversion period adjustment is performed during receive conversion period A. Otherwise,
1
2
the adjustment is performed during receive conversion period B. The adjustment command only adjusts one
transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive
conversion periods, another command must be issued during a subsequent FSX frame (see figure below).
t
1
FSX
FSR
Transmit Conversion Period
t
2
Receive Conv.
Period A
Receive Conv.
Period B
Figure 2. Adjusted Transmit and Receive Conversion Periods
asynchronous operation — more than one transmit frame sync occurring between two receive
frame syncs
When incrementally adjusting the conversion period via the A + A’ or A – A’ register options, a specific protocol
is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment
is performed near the end of the conversion period. The command to use the incremental conversion period
adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion period is then
adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as
shown in the following figure. If the adjustment command is issued during transmit conversion period A, receive
conversion period A is adjusted if there is sufficient time between t and t . If there is not sufficient time between
1
2
t and t , receive conversion period B is adjusted. The receive portion of an adjustment command can be
1
2
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
ignored if the adjustment command is sent during a receive conversion period, which is already being or will
be adjusted due to a prior adjustment command. For example, if adjustment commands are issued during
transmit conversion periods A, B, and C, the first two commands can cause receive conversion periods A and
B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is
ignored since it was issued during receive conversion period B, which already is adjusted via the transmit
conversion period B adjustment command.
t
1
FSX
FSR
Transmit
Conversion
Period A
Transmit
Conversion
Period B
Transmit
Conversion
Period C
t
2
Receive Conversion Period A
Receive Conversion Period B
Figure 3. Receive and Transmit Conversion Period Adjustments
asynchronous operation — more than one set of primary and secondary DX serial communication
occurring between two receive frame sync (see AIC DX data word format section)
The TA, TA’, TB, and control register information that is transmitted in the secondary communications is always
accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t and
1
t , the TA, RA’, and RB register information, which is sent during transmit conversion period A, is applied to
2
receive conversion period A. Otherwise, this information is applied during receive conversion period B. If RA,
RA’, and RB register information has already been received and is being applied during an ongoing conversion
period, any subsequent RA, RA’, or RB information that is received during this receive conversion period is
disregarded (see Figure 4).
t
1
Primary
Secondary
Primary
Secondary
Primary
Secondary
FSX
FSR
Transmit
Conversion
Period A
Transmit
Conversion
Period B
Transmit
Conversion
Period C
t
2
Receive Conversion
Period A
Receive Conversion Period B
Figure 4. Receive and Transmit Periods for Primary and Secondary Data
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
†
test modes
The TLC32044 or TLC32045 can be operated in special test modes. These test modes are used by Texas
Instruments to facilitate testing of the device during manufacturing. They are not intended to be used in real
applications; however, they allow the filters in the A/D and D/A paths to be used without using the A/D and D/A
converters.
In normal operation, the nonusable (NU) terminals are left unconnected. These NU terminals are used by the
factory to speed up testing of the TLC32044 or TLC32045 analog interface circuits (AIC). When the device is
used in normal (non-test mode) operation, the NU terminal (terminal 1) has an internal pulldown to –5 V.
Externally connecting 0 V or 5 V to terminal 1 puts the device in test-mode operation. Selecting one of the
possible test modes is accomplished by placing a particular voltage on certain terminals. A description of these
modes is provided in Table 2 and Figures 5 and 6.
Table 2. List of Test Modes
D/A PATH TEST (TERMINAL 1 to 5 V)
TEST FUNCTION
A/D PATH TEST (TERMINAL 1 to 0)
TEST FUNCTION
TEST
TERMINALS
5
The low-pass switched-capacitor filter clock is brought out to The bandpass switched-capacitor filter clock is brought out to
DR. This clock signal is normally internal. DR. This clock signal is normally internal.
11
3
No change from normal operation. The EODX signal is Thepulse that initiates the A/D conversion is brought out here.
brought out to EODX. This signal is normally internal.
Thepulse that initiates the D/A conversion is brought out here. No change from normal operation. The EODR signal is
brought out.
27 and 28
There are no test output signals provided on these terminals. The outputs of the A/D path low-pass or bandpass filter
(dependingupon control bit d2 – see AIC DX data word format
section) are brought out to these terminals. If the high-pass
section is inserted, the output will have a (sin x)/x droop. The
slope of the droop is determined by the ADC sampling
frequency, which is the high-pass section clock frequency
(see diagram of bandpass or low-pass filter test for receive
section). These outputs drive small (30-pF) loads.
15 and 16
D/A PATH LOW-PASS FILTER TEST: (WORD/BYTE) to –5 V
TEST FUNCTION
TheinputsoftheD/Apathlow-passfilterarebroughtouttoterminals15and16.TheD/Ainputtothisfilterisremoved.If(sin x)/x
correctionfilterisinserted, theOUT+andOUT–signalshaveaflatresponse(seeFigure2). Thecommon-moderangeofthese
inputs must not exceed ±0.5 V.
†
In the test mode, the AIC responds to the setting of WORD/BYTE to –5 V, as if WORD/BYTE were set to 0 V. Thus, the byte mode is selected
for communicating between DSP and AIC. Either of the path tests (D/A or A/D) can be performed simultaneously with the D/A low-pass filter test.
In this situation, WORD/BYTE must be connected to –5 V, which initiates byte-mode communications.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
Terminal 27 (positive)
†
Terminal 28 (negative)
Test Control
(terminal 1 at 0 V)
Test
Filter
M
U
X
A/D
†
All analog signal paths have differential architecture and hence have positive and negative
components.
Figure 5. Bandpass or Low-Pass Filter Test for Receiver Section
Filter
M
U
X
(sin x)/x
Correction
M
U
X
D/A
Test Control
(terminal 13 at –5 V)
Test
Terminal 16 (positive)
†
Terminal 15 (negative)
†
All analog signal paths have differential architecture and hence have positive and negative components.
Figure 6. Low-Pass Filter Test for Transmit Section
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
CC+
DD
Output voltage range, V
O
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
I
Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Operating free-air temperature range: TLC32044C, TLC32045C . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC32044E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 85°C
TLC32044I, TLC32045I . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC32044M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range: TLC32044C, I, TLC32045C, I . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
TLC32044M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 10 seconds: FN or FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . 260°C
J package . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to V
.
CC–
recommended operating conditions
MIN NOM
MAX
5.25
UNIT
V
Supply voltage, V
Supply voltage, V
(see Note 2)
(see Note 2)
4.75
–4.75
4.75
5
CC+
CC–
–5
–5.25
5.25
V
Digital supply voltage, V
(see Note 2)
5
V
DD
Digital ground voltage with respect to ANLG GND, DGTL GND
0
V
Reference input voltage, V
(see Note 2)
2
2
4
V
ref(ext)
High-level input voltage, V
V
+0.3
DD
0.8
V
IH
Low-level input voltage, V (see Note 3)
IL
–0.3
300
V
Load resistance at OUT+ and/or OUT–, R
Ω
L
Load capacitance at OUT+ and/or OUT–, C
100
pF
MHz
V
L
MSTR CLK frequency (see Note 4)
0.075
5
10.368
±1.5
20
Analog input amplifier common mode input voltage (see Note 5)
A/D or D/A conversion rate
kHz
TLC32044C, TLC32045C
0
–20
–40
–55
70
TLC32044E
85
Operating free-air temperature, T
°C
A
TLC32044I, TLC32045I
TLC32044M
85
125
NOTES: 2. Voltagesatanaloginputsandoutputs, REF, V
, and V
are with respect to the ANLG GND terminal. Voltagesatdigitalinputs
CC+ CC–,
and outputs and V
are with respect to the DGTL GND terminal.
DD
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
logic voltage levels and temperature only.
4. The bandpass switched-capacitor filter (SCF) specifications apply only when the low-pass section SCF clock is 288 kHz and the
high-pass section SCF clock is 8 kHz. If the low-pass SCF clock is shifted from 288 kHz, the low-pass roll-off frequency will shift
by the ratio of the low-pass SCF clock to 288 kHz. If the high-pass SCF is shifted from 8 kHZ, the high-pass roll-off frequency will
shift by the ratio of the high-pass SCF clock to 8 kHz. Similarly, the low-pass switched-capacitor filter (SCF) specifications apply only
when the SCF clock is 288 kHz. If the SCF clock is shifted from 288 kHz, the low-pass roll-off frequency will shift by the ratio of the
SCF clock to 288 kHz.
5. This range applies when (IN+ – IN–) or (AUX IN+ – AUX IN–) equals ± 6 V.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
electrical characteristics over recommended operating free-air temperature range, V
= 5 V,
CC+
V
= –5 V, V
= 5 V (unless otherwise noted)
CC–
DD
total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded
†
TYP
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN
MAX
UNIT
V
I
= 4.75 V,
= –300 µA
DD
OH
V
V
2.4
OH
V
V
= 4.75 V,
= 2 mA
DD
I
OL
Low-level output voltage
0.4
35
OL
TLC32044C, TLC32045C
I
Supply current from V
TLC32044I, TLC32045I,
TLC32044E, TLC32044M
CC+
CC+
40
TLC32044C, TLC32045C
–35
–40
mA
I
I
Supply current from V
Supply current from V
TLC32044I, TLC32045I,
TLC32044E, TLC32044M
CC–
CC–
DD
TLC3204xC, E, I
TLC32044M
7
8
f
MSTR CLK
= 5.184 MHz
DD
TLC3204xC, E, I
TLC32044M
3
3.3
3.3
V
ref
Internal reference output voltage
V
2.9
Temperature coefficient of internal reference voltage
Output resistance at REF
200
100
ppm/°C
kΩ
Vref
r
o
receive amplifier input
†
PARAMETER
TEST CONDITIONS
MIN
MAX
70
UNIT
TYP
TLC32044C, E, I
TLC32044M
10
10
A/D converter offset error (filters in)
85
mV
TLC32045C, I
TLC3204xC, E, I
TLC32044M
10
75
55
Common-mode rejection ratio at IN+, IN–, or
AUX IN+, AUX IN–
CMRR
See Note 6
dB
35
55
r
i
Input resistance at IN+, IN–, or AUX IN+, AUX IN–, REF
100
kΩ
transmit filter output
†
PARAMETER
TEST CONDITIONS
MIN
MAX
80
UNIT
TYP
TLC3204xC, E, I
TLC32044M
15
15
Output offset voltage at OUT+ OUT–
(single-ended relative to ANLG GND)
V
OO
mV
75
Maximum peak output voltage swing across R at OUT+ or OUT–
L
R ≥ 300 Ω,
L
V
±3
±6
OM
OM
(single ended)
Offset voltage = 0
V
Maximum peak output voltage swing between OUT+ and OUT–
(differential output)
V
R
≥ 600 Ω
L
†
All typical values are at T = 25°C.
A
NOTE 6: The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
system distortion specifications, SCF clock frequency = 288 kHz (see Note 7)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TLC3204xC, E, I
TLC32044M
70
70
70
70
65
65
65
65
70
70
70
65
65
65
V = –0.5 dB to –24 dB referred to V
,
I
ref
Single ended
Attenuation of second
harmonic of A/D input
signal
T
A
= 25°C
62
62
55
TLC32044C, E, I
TLC32045C, I
TLC3204xC, E, I
TLC32044M
Differential
V = –0.5 dB to –24 dB referred to V
I
ref
V = –0.5 dB to –24 dB referred to V
,
I
ref
Single ended
Attenuation of third and
higher harmonics of A/D
input signal
T
= 25°C
57
57
55
A
TLC32044C, E, I
TLC32045C, I
TLC3204xC, I, M
Differential
Single ended
Differential
Single ended
Differential
V = –0.5 dB to –24 dB referred to V
dB
I
ref
Attenuation of second
harmonic of D/A input
signal
TLC32044C, E, I V = –0 dB to –24 dB referred to V
I
62
55
ref
TLC32045C, I
TLC3204xC, I, M
Attenuation of third and
higher harmonics of D/A
input signal
TLC32044C, E, I
TLC32045C, I
V = –0 dB to –24 dB referred to V
I ref
57
55
†
All typical values are at T = 25°C.
A
NOTE 7: The test condition V is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V ). The load impedance for the DAC is
I
ref
600 Ω (300 Ω for TLC32044M).
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
A/D channel signal-to-distortion ratio (see Note 7)
†
†
†
= 4
A
= 1
A
= 2
A
v
v
v
PARAMETER
TEST CONDITIONS
V = –6 dB to –0.1 dB
UNIT
MIN
58
58
56
50
44
38
32
26
20
58
58
56
50
44
38
32
26
20
55
55
53
47
41
35
29
23
17
MAX
MIN
MAX
MIN
MAX
‡
>58
‡
>58
>58
I
‡
V = –12 dB to –6 dB
I
58
58
56
50
44
38
32
26
V = –18 dB to –12 dB
I
58
58
56
50
44
38
32
V = –24 dB to –18 dB
I
A/D channel signal-to-distortion ratio, TLC32044C,
TLC32044I, TLC32044E
V = –30 dB to –24 dB
I
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
‡
>58
‡
V = –6 dB to –0.5 dB
I
>58
>58
‡
V = –12 dB to –6 dB
I
58
58
56
50
44
38
32
26
V = –18 dB to –12 dB
I
58
58
56
50
44
38
32
V = –24 dB to –18 dB
I
A/D channel signal-to-distortion ratio, TLC32044M
V = –30 dB to –24 dB
I
dB
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
‡
>55
‡
V = –6 dB to –0.1 dB
I
>55
>55
‡
V = –12 dB to –6 dB
I
55
55
53
47
41
35
29
23
V = –18 dB to –12 dB
I
55
55
53
47
41
35
29
V = –24 dB to –18 dB
I
A/D channel signal-to-distortion ratio, TLC32045C,
TLC32045I
V = –30 dB to –24 dB
I
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
†
‡
A is the programmable gain of the input amplifier.
v
A value >60 is over range and signal clipping occurs.
NOTE 7: The test condition V is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V ). The load impedance for the DAC is
I
ref
600 Ω (300 Ω for TLC32044M).
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
D/A channel signal-to-distortion ratio (see Note 7)
PARAMETER
TEST CONDITIONS
V = –6 dB to 0 dB
MIN
58
58
56
50
44
38
32
26
20
55
55
53
47
41
35
29
23
17
MAX
UNIT
I
V = –12 dB to –6 dB
I
V = –18 dB to –12 dB
I
V = –24 dB to –18 dB
I
D/A channel signal-to-distortion ratio, TLC32044C, TLC32044E, TLC32044I,
TLC32044M
V = –30 dB to –24 dB
I
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
dB
V = –6 dB to 0 dB
I
V = –12 dB to –6 dB
I
V = –18 dB to –12 dB
I
V = –24 dB to –18 dB
I
D/A channel signal-to-distortion ratio, TLC32045C, TLC32045I
V = –30 dB to –24 dB
I
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
V = –54 dB to –48 dB
I
NOTE 7: The test condition V is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V ). The load impedance for the DAC is
I
ref
600 Ω (300 Ω for TLC32044M).
gain and dynamic range
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Absolute transmit gain tracking error while transmitting
into 600 Ω
–48-dB to 0-dB signal range, See Note 8
±0.05 ±0.15
±0.05 ±0.25
dB
Absolute transmit gain tracking error while transmitting –48-dB to 0-dB signal range,
into 300 Ω, TLC32044M See Note 8
T = 25°C,
A
dB
Absolute transmit gain tracking error while transmitting –48-dB to 0-dB signal range,
±0.4
±0.05 ±0.15
±0.05 ±0.25
dB
dB
dB
into 300 Ω, TLC32044M
T
A
= –55°C to 125°C,
See Note 8
Absolute receive gain tracking error
–48-dB to 0-dB signal range, See Note 8
–48-dB to 0-dB signal range,
See Note 8
T = 25°C,
A
Absolute receive gain tracking error, TLC32044M
Absolute receive gain tracking error, TLC32044M
–48-dB to 0-dB signal range,
±0.4
dB
dB
T
A
= –55°C to 125°C,
See Note 8
Absolute gain of the A/D channel
Absolute gain of the D/A channel
Signal input is a –0.5-dB,
Signal input is a 0-dB,
1-kHz sinewave
1-kHz sinewave
0.2
–0.3
†
All typical values are at T = 25°C.
A
NOTE 8: Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 dB relative to V ).
ref
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
power supply rejection and crosstalk attenuation
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
f = 0 to 30 kHz
30
45
30
45
80
80
V
or V
supply voltage rejection
CC–
Idle channel, supply signal at 200 mV
p-p measured at DR (ADC output)
CC+
ratio, receive channel
f = 30 kHz to 50 kHz
f = 0 to 30 kHz
V
CC+
or V supply voltage rejection
Idle channel, supply signal at 200 mV
p-p measured at OUT+
CC–
ratio, transmit channel (single ended)
f = 30 kHz to 50 kHz
TLC3204xC, E, I
TLC32044M
dB
Crosstalk attenuation, transmit-to-receive
(single ended)
65
65
Crosstalk attenuation, receive-to-transmit, TLC32044M
Inputs grounded, Gain = 1, 2, 4
†
All typical values are at T = 25°C.
A
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
delay distortion
†
bandpass filter transfer function, SCF f
= 288 kHz IN+ – IN– is a ±3 V sinewave (see Note 9)
clock
‡
§
PARAMETER
TEST CONDITIONS
FREQUENCY RANGE ADJUSTMENT ADDEND
MIN
–33
MAX
–25
–1
UNIT
TYP
f ≤ 50 Hz
K1 × 0 dB
–29
–2
0
f = 100 Hz
K1 × –0.26 dB
K1 × 0 dB
–4
f = 150 Hz to 3100 Hz
f = 3100 Hz to 3300 Hz
f = 3300 Hz to 3650 Hz
f = 3800 Hz
–0.25
–0.3
–0.5
0.25
0.3
Filter gain,
K1 × 0 dB
0
TLC32044C,
TLC32044E,
TLC32044I
Input signal reference to 0 dB
K1 × 0 dB
0
0.5
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
–3
–17
–1
f = 4000 Hz
–16
–40
–65
–25
–1
f ≥ 4400 Hz
f ≥ 5000 Hz
f ≤ 50 Hz
K1 × 0 dB
–33
–4
–29
–2
0
f = 100 Hz
K1 × –0.26 dB
K1 × 0 dB
f = 150 Hz to 3100 Hz
f = 3100 Hz to 3300 Hz
f = 3300 Hz to 3500 Hz
f = 3800 Hz
–0.25
–0.3
–0.5
0.25
0.3
K1 × 0 dB
0
Filter gain,
TLC32044M
Input signal reference to 0 dB
K1 × 0 dB
0
0.5
dB
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
–3
–17
–0.5
–16
–40
–65
–25
–1
f = 4000 Hz
f ≥ 4400 Hz
f ≥ 5000 Hz
f ≤ 50 Hz
K1 × 0 dB
–33
–4
–29
–2
0
f = 100 Hz
K1 × –0.26 dB
K1 × 0 dB
f = 150 Hz to 3100 Hz
f = 3100 Hz to 3300 Hz
f = 3300 Hz to 3650 Hz
f = 3800 Hz
–0.25
–0.3
–0.5
0.25
0.3
K1 × 0 dB
0
Filter gain,
TLC32045C,
TLC32045I
Input signal reference to 0 dB
K1 × 0 dB
0
0.5
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
–3
–17
–1
f = 4000 Hz
–16
–40
–65
f ≥ 4400 Hz
f ≥ 5000 Hz
†
‡
See filter curves in typical characteristics
The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF may result from
inaccuracies in the MSTR CLK frequency, resulting from crystal frequency tolerances. If this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where K1 = 100 [(SCF frequency – 288 kHz) / 288 kHz].
For errors greater than 0.25%, see Note 8.
§
All typical values are at T = 25°C.
A
NOTE 9: The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz for the bandpass and
low-pass filters respectively. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the
ratio of switched-capacitor filter clock frequency to 288 kHz.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
†
low-pass filter transfer function , SCF f
= 288 kHz (see Note 9)
clock
‡
§
PARAMETER
TEST CONDITIONS
FREQUENCY RANGE ADJUSTMENT ADDEND
MIN
–0.25
–0.3
MAX
0.25
0.3
UNIT
TYP
f = 0 Hz to 3100 Hz
f = 3100 Hz to 3300 Hz
f = 3300 Hz to 3650 Hz
f = 3800 Hz
K1 × 0 dB
K1 × 0 dB
K1 × 0 dB
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
K1 × 0 dB
K1 × 0 dB
K1 × 0 dB
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
K1 × 0 dB
K1 × 0 dB
K1 × 0 dB
K1 × 2.3 dB
K1 × 2.7 dB
K1 × 3.2 dB
K1 × 0 dB
0
0
0
Filter gain,
–0.5
0.5
TLC32044C,
TLC32044E,
TLC32044I
Input signal reference is 0 dB
–3
–1
f = 4000 Hz
–17
–16
–40
–65
0.25
0.3
f ≥ 4400 Hz
f ≥ 5000 Hz
f = 0 Hz to 3100 Hz
f = 3100 Hz to 3300 Hz
f = 3300 Hz to 3500 Hz
f = 3800 Hz
–0.25
–0.3
–0.5
0
0
0
0.5
Filter gain,
TLC32044M
Input signal reference is 0 dB
–3
–17
–0.5
–16
–40
–65
0.25
0.3
dB
f = 4000 Hz
f ≥ 4400 Hz
f ≥ 5000 Hz
f = 0 Hz to 3100 Hz
f = 3100 Hz to 3300 Hz
f = 3300 Hz to 3650 Hz
f = 3800 Hz
–0.25
–0.3
–0.5
0
0
0
0.5
Filter gain,
TLC32045C,
TLC32045I
Input signal reference is 0 dB
–3
–17
–1
f = 4000 Hz
–16
–40
–65
f ≥ 4400 Hz
f ≥ 5000 Hz
†
‡
See filter curves in typical characteristics
The MIN, TYP, and MAX specifications are given for a 288-kHz SCF clock frequency. A slight error in the 288-kHz SCF may result from
inaccuracies in the MSTR CLK frequency, resulting from crystal frequency tolerances. If this frequency error is less than 0.25%, the
ADJUSTMENT ADDEND should be added to the MIN, TYP, and MAX specifications, where K1 = 100 [(SCF frequency – 288 kHz) / 288 kHz].
For errors greater than 0.25%, see Note 8.
§
All typical values are at T = 25°C.
A
NOTE 9: The filter gain outside of the passband is measured with respect to the gain at 1 kHz. The filter gain within the passband is measured
with respect to the average gain within the passband. The passbands are 150 to 3600 Hz and 0 to 3600 Hz for the bandpass and
low-pass filters respectively. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the
ratio of switched-capacitor filter clock frequency to 288 kHz.
serial port
†
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN
MAX
UNIT
V
TYP
V
V
I
I
= –300 µA
2.4
OH
OH
Low-level output voltage
Input current
= 2 mA
0.4
V
OL
OL
I
I
±10
µA
pF
pF
C
C
Input capacitance
Output capacitance
15
15
i
o
†
All typical values are at T = 25°C.
A
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
operating characteristics over recommended operating free-air temperature range, V
= 5 V,
CC+
V
= –5 V, V
= 5 V
CC–
DD
noise (measurement includes low-pass and bandpass switched-capacitor filters)
†
PARAMETER
TLC32044C, E, I
TEST CONDITIONS
MIN
MAX
UNIT
TYP
550 µV rms
575 µV rms
600 µV rms
425 µV rms
450 µV rms
450 µV rms
dBrncO
TLC32044M
With sin x/x correction
TLC32045C, I
TLC32044C, E, I
TLC32044M
325
325
DX input = 00000000000000,
constant input code
Transmit noise
TLC32045C, I
TLC32044C, E, I
TLC32045C, I
TLC32044C, E, I, M
TLC32045C, I
TLC32044C, E, I, M
TLC32045C, I
Without sin x/x correction
18
24
dBrncO
300
500 µV rms
530 µV rms
dBrncO
Receive noise
(see Note 10)
Inputs grounded, gain = 1
18
24
dBrncO
†
All typical values are at T = 25°C.
A
NOTE 10: The noise is computed by statistically evaluating the digital output of the A/D converter.
timing requirements
serial port recommended input signals
MIN
MAX
UNIT
ns
Master clock cycle time
95
t
c(MCLK)
Master clock cycle time, TLC32044M
Master clock rise time
100
192
10
ns
t
t
ns
r(MCLK)
Master clock fall time
10
ns
f(MCLK)
Master clock duty cycle
25%
42%
800
20
75%
58%
Master clock duty cycle, TLC32044M
RESET pulse duration (see Note 11)
DX setup time before SCLK↓
DX setup time before SCLK↓, TLC32044M
DX hold time after SCLK↓
ns
ns
ns
ns
t
t
su(DX)
28
t
h(DX)
c(SCLK)/4
NOTE 11: RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached their
recommended values.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
serial port — AIC output signals
†
TEST CONDITIONS
MIN TYP
MAX
UNIT
ns
ns
ns
%
t
t
t
Shift clock (SCLK) cycle time
380
c(SCLK)
f(SCLK)
r(SCLK)
Shift clock (SCLK) fall time
50
50
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
45
55
t
t
t
t
t
t
t
t
t
t
t
Delay from SCLK↑ to FSR/FSX↓
Delay from SCLK↑ to FSR/FSX↑
DR valid after SCLK↑
C
C
= 50 pF
= 50 pF
52
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CH-FL)
d(CH-FH)
d(CH-DR)
d(CH-EL)
d(CH-EH)
f(EODX)
L
L
52
90
Delay from SCLK↑ to EODX/EODR↓ in word mode
Delay from SCLK↑ to EODX/EODR↑ in word mode
EODX fall time
90
90
15
EODR fall time
15
f(EODR)
Delay from SCLK↑ to EODX/EODR↓ in byte mode
Delay from SCLK↑ to EODX/EODR↑ in byte mode
Delay from MSTR CLK↑ to SCLK↓
Delay from MSTR CLK↑ to SCLK↑
100
100
d(CH-EL)
d(CH-EH)
d(MH-SL)
d(MH-SH)
65
65
serial port — AIC output signals, TLC32044M
†
MIN TYP
MAX
UNIT
ns
ns
ns
%
t
t
t
Shift clock (SCLK) cycle time
400
c(SCLK)
f(SCLK)
r(SCLK)
Shift clock (SCLK) fall time
50
50
50
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
t
t
t
t
t
t
t
t
t
t
t
Delay from SCLK↑ to FSR/FSX↓
Delay from SCLK↑ to FSR/FSX↑
DR valid after SCLK↑
260
260
316
280
280
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CH-FL)
d(CH-FH)
d(CH-DR)
d(CH-EL)
d(CH-EH)
f(EODX)
Delay from SCLK↑ to EODX/EODR↓ in word mode
Delay from SCLK↑ to EODX/EODR↑ in word mode
EODX fall time
15
15
EODR fall time
f(EODR)
Delay from SCLK↑ to EODX/EODR↓ in byte mode
Delay from SCLK↑ to EODX/EODR↑ in byte mode
Delay from MSTR CLK↑ to SCLK↓
Delay from MSTR CLK↑ to SCLK↑
100
100
65
d(CH-EL)
d(CH-EH)
d(MH-SL)
d(MH-SH)
65
†
Typical values are at T = 25°C.
A
27
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VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
Table 3. Gain Control Table (Analog Input Signal Required for Full-Scale A/D Conversion)
CONTROL REGISTER
BITS
A/D
CONVERSION
RESULT
‡
ANALOG INPUT
INPUT CONFIGURATIONS
d6
1
d7
1
±6 V
Full-scale
Differential configuration
Analog input = IN+ – IN–
= AUX IN+ – AUX IN–
0
0
1
0
±3 V
Full-scale
Full-scale
0
1
±1.5 V
1
1
±3 V
Half-scale
Single-ended configuration
Analog input = IN+ – ANLG GND
= AUX IN+ – ANLG GND
0
0
1
0
±3 V
Full-sale
Full-scale
0
1
±1.5 V
‡
In this example, V is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog
ref
input not exceed 0.1 dB below full scale.
R
fb
R
fb
R
R
R
R
–
+
IN+
IN–
–
+
+
–
AUX IN+
AUX IN–
+
–
To Multiplexer
To Multiplexer
R
fb
R
fb
R
= R for d6 = 1, d7 = 1
d6 = 0, d7 = 0
= 2R for d6 = 1, d7 = 0
= 4R for d6 = 0, d7 = 1
fb
R
= R for d6 = 1, d7 = 1
d6 = 0, d7 = 0
= 2R for d6 = 1, d7 = 0
= 4R for d6 = 0, d7 = 1
fb
R
R
fb
fb
R
R
fb
fb
Figure 8. AUX IN+ and AUX IN–
Gain Control Circuitry
Figure 7. IN+ and IN– Gain Control Circuitry
(sin x)/x correction
The AIC does not have (sin x)/x correction circuitry after the digital-to-analog converter. (Sin x)/x correction can
be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy
can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are
shown in Table 4, are typical of the numerical correction accuracy that can be achieved for sample rates of
interest. The filter requires only seven instruction cycles per sample on the TMS(SMJ)320 DSPs. With a 200-ns
instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling
rates of 8000 Hz and 9600 Hz, respectively. This correction adds a slight amount of group delay at the upper
edge of the 300–3000-Hz band.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
(sin x)/x roll-off for a zero-order hold function
The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the
various sampling rates is shown in the table below.
Table 4. (sin x)/x Roll-Off
sin π f/f
π f/f
(f = 3000 Hz)
20 log
s
s
f
s
(Hz)
(dB)
7200
8000
9600
–2.64
–2.11
–1.44
–0.63
–0.35
14400
19200
The actual AIC (sin x)/x roll-off will be slightly less than the above figures because the AIC has less than a 100%
duty cycle hold interval.
correction filter
To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter (shown below) is recommended.
+
u
y
(i + 1)
(i + 1)
+
z – 1
(1 – p1)P2
p1
The difference equation for this correction filter is:
yi + 1 = p2(1 –p1) (u ) + p1 yi
i + 1
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
2
2
p2 (1–p1)
1 – 2p1 cos(2 f f )
2
|H(f)|
2
p1
s
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
correction results
Table 5 shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz
sampling rates.
Table 5. Optimum P Values
ERROR (dB)
= 8000 Hz
p1 = –0.14813
p2 = 0.9888
ERROR (dB)
= 9600 Hz
p1 = –0.1307
p2 = 0.9951
f
s
f
s
f (Hz)
300
600
–0.099
–0.089
–0.054
–0.002
0.041
–0.043
–0.043
0
900
1200
1500
1800
2100
2400
2700
3000
0
0
0.079
0.043
0.043
0.043
0
0.100
0.091
–0.043
–0.102
–0.043
TMS(SMJ)320 software requirements
The digital correction filter equation can be written in state variable form as follows:
Y = k1 × Y + k2 × U
where
k1 = p1
k2 = (1 – p1) × p2
Y = filter state
U = next I/O sample
The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift)
yields the correct result. With the assumption that the TMS(SMJ)320 processor page pointer and memory
configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with
the following program:
ZAC
LT K2
MPY U
LTA K1
MPY Y
APAC
SACH (dma), (shift)
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
t
t
t
c(SCLK)
f(SCLK)
2 V
r(SCLK)
2 V
2 V
2 V
2 V
2 V
2 V
SHIFT CLK
0.8 V
0.8 V
0.8 V
t
t
d(CH-FL)
d(CH-FL)
t
t
d(CH-FH)
d(CH-FH)
2 V
2 V
FSR, FSX
0.8 V
t
d(CH-DR)
2 V
D13
D15
D14
D14
D9
D8
D7
D7
D6
D6
D2
D2
D1
D1
D0
DR
DX
t
su(DX)
Don’t Care
D15
D13
D9
D8
D0
t
h(DX)
t
d(CH-EL)
t
d(CH-EH)
0.8 V
2 V
EODR, EODX
(a) BYTE-MODE TIMING
t
c(SCLK)
2 V
2 V
2 V
2 V
2 V
SHIFT CLK
0.8 V
0.8 V 0.8 V
t
d(CH-FH)
t
d(CH-FL)
FSR, FSX
DR
0.8 V
t
d(CH-DR)
D15
D14
D13
D13
D12
D11
D2
D2
D1
D0
t
su(DX)
Don’t Care
D15
D14
D12
D11
D1
D0
DX
t
t
t
d(CH-EH)
h(DX)
d(CH-EL)
2 V
EODX, EODR
0.8 V
(b) WORD-MODE TIMING
MSTR CLK
t
t
d(MH-SL)
d(MH-SH)
SHIFT CLK
(c) SHIFT-CLOCK TIMING
Figure 9. Serial-Port Timing
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
FSX
DX
Q
2D
C2
TMS32010/
SMJ32010
SN74(54)LS299
S1
Q
H
G2
S0
G1
DEN
TLC32044/
TLC32045
CLK
G1
A
Y1
Y0
A0/PA0
A1/PA1
A2/PA2
D8–D15
B
A-H SR
C
SHIFT CLK
SN74(54)LS299
S1
SN74(54)LS138
Q
H
G2
S0
G1
CLK
SN74LS74
C1
D0–D7
D0–D15
A-H
D0–D15
WE
SR
Q
1D
DR
MSTR CLK
EODX
CLKOUT
INT
Figure 10. TMS(SMJ)32010/TMS(SMJ)320C15/(SMJ320E15)-TLC32044/45 Interface Circuit
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
CLK OUT
DEN
S0, G1
D0–D15
Valid
(a) IN INSTRUCTION TIMING
CLK OUT
WE
SN74(54)LS138
Y1
SN74(54)LS299
CLK
D0–D15
Valid
(b) OUT INSTRUCTION TIMING
Figure 11. TMS(SMJ)32010/TMS(SMJ)320C15-TLC32044/TLC32045 Interface Timing
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
AIC TRANSMIT AND RECEIVE
LOW-PASS FILTER
AIC TRANSMIT AND RECEIVE
LOW-PASS FILTER
3
20
10
SCF Clock f = 288 kHz
= 25°C
Input = ±3-V Sine wave
T
A
2.5
0
–10
–20
–30
–40
–50
–60
–70
–80
2
1.5
1
SCF Clock f = 288 kHz
0.5
T
A
= 25°C
Input = ±3-V Sine wave
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5 1.5 2.5
1
2
3
3.5
4
4.5
5
SCF Clock Frequency
288 kHz
SCF Clock Frequency
288 kHz
Normalized Frequency – kHz ×
Normalized Frequency – kHz ×
Figure 12
Figure 13
AIC RECEIVE-CHANNEL
HIGH-PASS FILTER
AIC RECEIVE-CHANNEL
BANDPASS FILTER
20
10
20
10
SCF Clock f = 8 kHz
= 25°C
Input = ±3-V Sine wave
T
A
0
0
–10
–20
–30
–40
–50
–60
–10
–20
–30
–40
Low-Pass SCF Clock f = 288 kHz
High-Pass SCF Clock f = 8 kHz
–50
–60
T
= 25°C
A
–70
–80
Input = ±3-V Sine wave
0
50 100 150 200 250 300 350 400 450 500
A/D Conversion Rate
0
0.5 1.5 2.5
1
2
3
3.5
4
4.5
5
Frequency – kHz
Normalized Frequency – kHz ×
8 k samples/s
Figure 14
Figure 15
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL
AIC (sin x)/x CORRECTION FILTER
BANDPASS FILTER
5
SCF Clock f = 288 kHz
Low-Pass SCF Clock f = 288 kHz
4.5
4
T
= 25°C
A
High-Pass SCF Clock f = 8 kHz
= 25°C
2.5
Input = ±3-V Sine wave
T
A
Input = ±3-V Sine wave
3.5
3
2.0
1.5
2.5
2
1.0
0.5
0.0
1.5
1
0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
SCF Clock Frequency
288 kHz
Frequency – kHz
Normalized Frequency – kHz ×
Figure 16
Figure 17
A/D SIGNAL-TO-DISTORTION RATIO
vs
INPUT-SIGNAL LEVEL
AIC (sin x)/x CORRECTION FILTER
100
90
80
70
60
50
40
30
6
1-kHz Input Signal
8-kHz Conversion Rate
(sin x)/x
Correction
Filter
4
Gain = 1x
Gain = 4x
2
0
Error
–2
20
10
0
D/A Converter (sin x)/x
Distortion for TB Register = 36
–4
–6
–50
–40
–30
–20
–10
0
10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Input Signal Relative to V – dB
ref
SCF Clock Frequency
288 kHz
Normalized Frequency – kHz ×
Figure 18
Figure 19
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
A/D GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0-dB INPUT-SIGNAL LEVEL)
D/A CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT-SIGNAL LEVEL
0.5
0.4
100
1-kHz Input Signal
8-kHz Conversion Rate
1-kHz Input Signal into 600 Ω
8-kHz Conversion Rate
90
80
70
60
50
40
30
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
20
10
0
–50
–40
–30
–20
–10
0
10
–50
–40
–30
–20
–10
0
10
Input Signal Relative to V – dB
ref
Input Signal Relative to V – dB
ref
Figure 20
Figure 21
D/A GAIN TRACKING
A/D SECOND HARMONIC DISTORTION
(GAIN RELATIVE TO GAIN
vs
AT 0-dB INPUT-SIGNAL LEVEL)
INPUT-SIGNAL LEVEL
0.5
0.4
–100
–90
1-kHz Input Signal into 600 Ω
8-kHz Conversion Rate
1-kHz Input Signal
8-kHz Conversion Rate
–80
–70
–60
–50
–40
–30
–20
–10
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–50
–40
–30
–20
–10
0
10
–50
–40
–30
–20
–10
0
10
Input Signal Relative to V – dB
ref
Input Signal Relative to V – dB
ref
Figure 22
Figure 23
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
D/A SECOND HARMONIC DISTORTION
A/D THIRD HARMONIC DISTORTION
vs
vs
INPUT-SIGNAL LEVEL
INPUT-SIGNAL LEVEL
–100
–90
–100
–90
1-kHz Input Signal
8-kHz Conversion Rate
1-kHz Input Signal Into 600 Ω
8-kHz Conversion Rate
–80
–70
–60
–50
–40
–30
–20
–10
0
–80
–70
–60
–50
–40
–30
–20
–10
0
–50
–40
–30
–20
–10
0
10
–50
–40
–30
–20
–10
0
10
Input Signal Relative to V – dB
ref
Input Signal Relative to V – dB
ref
Figure 24
Figure 25
D/A THIRD HARMONIC DISTORTION
vs
INPUT-SIGNAL LEVEL
–100
–90
1-kHz Input Signal into 600 Ω
8-kHz Conversion Rate
–80
–70
–60
–50
–40
–30
–20
–10
0
–50
–40
–30
–20
–10
0
10
Input Signal Relative to V – dB
ref
Figure 26
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC32044C, TLC32044E, TLC32044I, TLC32044M, TLC32045C, TLC32045I
VOICE-BAND ANALOG INTERFACE CIRCUITS
SLAS017F – MARCH 1988 – REVISED MAY 1995
APPLICATION INFORMATION
TMS(SMJ)32020/C25
TLC32044/TLC32045
CLKOUT
FSX
MSTR CLK
V
5 V
CC+
REF
FSX
C
C
DX
DX
ANLG GND
†
BAT 42
FSR
FSR
C
DR
DR
V
CC–
–5 V
CLKR
CLKX
SHIFT CLK
V
5 V
DD
0.1 µF
DGTL GND
D
A
C = 0.2 µF, Ceramic
†
Figure 27. AIC Interface to the TMS(SMJ)32020/C25 Showing Decoupling Capacitors and Schottky Diode
†
Thomson Semiconductors
V
CC
R
3-V Output
500 Ω
TL431
0.01 µF
2500 Ω
D
For:
V
CC
V
CC
V
CC
= 12 V, R = 7200 Ω
= 10 V, R = 5600 Ω
= 5 V, R = 1600 Ω
Figure 28. External Reference Circuit For TLC32044/TLC32045
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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