TLC320AC02 [TI]
Single-Supply Analog Interface Circuit; 单电源模拟接口电路型号: | TLC320AC02 |
厂家: | TEXAS INSTRUMENTS |
描述: | Single-Supply Analog Interface Circuit |
文件: | 总84页 (文件大小:431K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLC320AC02C, TLC320AC02I
Data Manual
Single-Supply Analog Interface Circuit
SLAS084C
October 1997
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TIwarrantsperformanceofitssemiconductorproductsandrelatedsoftwaretothespecifications
applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
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Copyright 1997, Texas Instruments Incorporated
Contents
Section
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
1.5 Register Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
2
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.1 Definitions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
2.2 Reset and Power-Down Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.2.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.2.2 Conditions of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.2.3 Software and Hardware Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.2.4 Register Default Values After POR, Software Reset,
or RESET Is Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2.3 Master-Slave Terminal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.4 ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.5 DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2.7 Number of Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2.8 Required Minimum Number of MCLK Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.8.1 TLC320AC02 AIC Master-Slave Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2.8.2 Notes on TLC320AC01/02 AIC Master-Slave Operation . . . . . . . . . . . . . . . 2–7
2.9 Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.9.1 Master and Stand-Alone Operating Frequencies . . . . . . . . . . . . . . . . . . . . . 2–9
2.9.2 Slave and Codec Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.10 Switched-Capacitor Filter Frequency (FCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.11 Filter Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.12 Master and Stand-Alone Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.12.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
2.12.2 Master and Stand-Alone Functional Sequence . . . . . . . . . . . . . . . . . . . . . . 2–10
2.13 Slave and Codec Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10
2.13.1 Slave and Codec Functional Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.13.2 Slave Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.14 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.14.1 Frame-Sync Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
2.14.2 Data Out (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2.14.3 Data In (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
2.14.4 Hardware Program Terminals (FC1 and FC0) . . . . . . . . . . . . . . . . . . . . . . . 2–12
2.14.5 Midpoint Voltages (ADC V
and DAC V
) . . . . . . . . . . . . . . . . . . . . . . 2–13
MID
MID
iii
2.15 Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
2.15.1 Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
2.15.2 Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.15.3 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.15.4 Free-Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.15.5 Force Secondary Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
2.15.6 Enable Analog Input Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2.15.7 DAC Channel (sin x)/x Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2.16 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content
During Primary and Secondary Communications . . . . . . . . . . . . . . . . . . . . 2–15
2.16.2 Slave and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
2.17 Request for Secondary Serial Communication and Phase Shift . . . . . . . . . . . . . 2–17
2.17.1 Initiating a Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2.17.2 Normal Combinations of Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2.17.3 Additional Control Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
2.18 Primary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
2.18.1 Primary Serial Communications Data Format . . . . . . . . . . . . . . . . . . . . . . . 2–19
2.18.2 Data Format From DOUT During Primary Serial Communications . . . . . 2–19
2.19 Secondary Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
2.19.1 Data Format to DIN During Secondary Serial Communications . . . . . . . . 2–19
2.19.2 Control Data-Bit Function in Secondary Serial Communication . . . . . . . . 2–19
2.20 Internal Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
2.20.1 Pseudo-Register 0 (No-Op Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
2.20.2 Register 1 (A Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
2.20.3 Register 2 (B Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
2.20.4 Register 3 (A′ Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
2.20.5 Register 4 (Amplifier Gain-Select Register) . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2.20.6 Register 5 (Analog Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
2.20.7 Register 6 (Digital Configuration Register) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
2.20.8 Register 7 (Frame-Sync Delay Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
2.20.9 Register 8 (Frame-Sync Number Register) . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . 3–1
3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
3.3 Electrical Characteristics Over Recommended Range of Operating Free-Air
Temperature, MCLK = 5.184 MHz, V
= 5 V, Outputs Unloaded,
DD
Total Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.4 Electrical Characteristics Over Recommended Range of Operating Free-Air
Temperature, V
= 5 V, Digital I/O Terminals (DIN, DOUT, EOC,
DD
FC0, FC1, FS, FSD, MCLK, M/S, SCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
3.5 Electrical Characteristics Over Recommended Range of Operating Free-Air
Temperature, V
= 5 V, ADC and DAC Channels . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
DD
3.5.1 ADC Channel Filter Transfer Function, FCLK = 144 kHz, f = 8 kHz . . . . 3–2
3.5.2 ADC Channel Input, V
3.5.3 ADC Channel Signal-to-Distortion Ratio, V
s
= 5 V, Input Amplifier Gain = 0 dB . . . . . . . . . . . 3–3
DD
= 5 V, f = 8 kHz . . . . . . . . 3–3
DD
s
iv
3.5.4 DAC Channel Filter Transfer Function, FCLK = 144 kHz, f = 9.6 kHz,
s
V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
DD
3.5.5 DAC Channel Signal-to-Distortion Ratio, V
3.5.6 System Distortion, V
= 5 V, f = 8 kHz . . . . . . . . 3–4
= 5 V, f = 8 kHz, FCLK = 144 kHz . . . . . . . . . . . . 3–4
DD
s
DD
s
3.5.7 Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
V
DD
3.5.8 Absolute Gain Error, V
3.5.9 Relative Gain and Dynamic Range, V
3.5.10 Power-Supply Rejection, V
3.5.11 Crosstalk Attenuation, V
= 5 V, f = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
DD
s
= 5 V, f = 8 kHz . . . . . . . . . . . . . 3–5
s
DD
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
DD
DD
3.5.12 Monitor Output Characteristics, V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
DD
3.6 Timing Requirements and Specifications in Master Mode . . . . . . . . . . . . . . . . . . . 3–8
3.6.1 Recommended Input Timing Requirements for Master Mode,
V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
DD
3.6.2 Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
DD
3.7 Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
3.7.1 Recommended Input Timing Requirements for Slave Mode,
V
= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
DD
3.7.2 Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
DD
4
5
6
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
v
List of Illustrations
Figure
Title
Page
1–1 Control Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
2–1 Functional Sequence for Primary and Secondary Communication . . . . . . . . . . . . . 2–5
2–2 Timing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
2–3 Master and Stand-Alone Functional Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
2–4 Slave and Codec Functional Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
4–1 IN+ and IN– Gain-Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–2 AIC Stand-Alone and Master-Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–3 AIC Slave and Codec Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–4 Master or Stand-Alone FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–5 Slave FS to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4– 6 Slave SCLK to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
4–7 DOUT Enable Timing From Hi-Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–8 DOUT Delay Timing to Hi-Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–9 EOC Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
4–10 Master-Slave Frame-Sync Timing After a Delay Has Been Programmed
Into the FSD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
4–11 Master and Slave Frame-Sync Sequence with One Slave . . . . . . . . . . . . . . . . . . . . 4–5
5–1 ADC Low-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
5–2 ADC Low-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5–3 ADC Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
5–4 ADC Band-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
5–5 ADC Band-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
5–6 ADC High-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
5–7 ADC Band-Pass Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
5–8 DAC Low-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5–9 DAC Low-Pass Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5–10 DAC Low-PASS Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
5–11 DAC (sin x)/x Correction Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5–12 DAC (sin x)/x Correction Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
5–13 DAC (sin x)/x Correction Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
vi
List of Tables
Table
Title
Page
1–1 Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
2–1 Master-Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
2–2 Sampling Variation With A′ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
2–3 Software and Hardware Requests for Secondary Serial-Communication and
Phase-Shift Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
4–1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
vii
1
Introduction
†
The TLC320AC02 analog interface circuit (AIC) is an audio-band processor that provides an
analog-to-digitaland digital-to-analog input/output interface system on a single monolithic CMOS chip. This
device integrates
a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution
analog-to-digital converter (ADC), a 14-bit-resolution digital-to-analog converter (DAC), a low-pass
switched-capacitor output-reconstruction filter, (sin x)/x compensation, and a serial port for data and control
transfers.
The internal circuit configuration and performance parameters are determined by reading control
information into the eight available data registers. The register data sets up the device for a given mode of
operation and application.
The major functions of the TLC320AC02 are:
1. To convert audio-signal data to digital format by the ADC channel
2. To provide the interface and control logic to transfer data between its serial input and output
terminals and a digital signal processor (DSP) or microprocessor
3. To convert received digital data back to an audio signal through the DAC channel
Theantialiasinginputlow-passfilterisaswitched-capacitorfilterwithasixth-orderellipticcharacteristic. The
high-pass filter is a single-pole filter to preserve low-frequency response as the low-pass filter cutoff is
adjusted. Thereisathree-polecontinuous-timefilterthatprecedesthisfiltertoeliminateanyaliasingcaused
by the filter clock signal.
Theoutput-reconstructionswitched-capacitorfilterisasixth-orderelliptictransitionallow-passfilterfollowed
by a second-order (sin x)/x correction filter. This filter is followed by a three-pole continuous-time filter to
eliminate images of the filter clock signal.
The TLC320AC02 consists of two signal-processing channels, an ADC channel and a DAC channel, and
the associated digital control. The two channels operate synchronously; data reception at the DAC channel
and data transmission from the ADC channel occur during the same time interval. The data transfer is in
2s-complement format.
There are three basic modes of operation available: the stand-alone analog-interface mode, the
master-slave mode, and the linear-codec mode. In the stand-alone mode, the TLC320AC02 generates the
shiftclockandframesynchronizationforthedatatransfersandistheonlyAICused. Themaster-slavemode
has one TLC320AC02 as the master that generates the master-shift clock and frame synchronization; the
remaining AICs are slaves to these signals. In the linear-codec mode, the shift clock and the frame-
synchronization signals are externally generated and the timing can be any of the standard codec-timing
patterns.
Typical applications for this device include modems, speech processing, analog interface for DSPs,
industrial-process control, acoustical-signal processing, spectral analysis, data acquisition, and
instrumentation recorders.
The TLC320AC02C is characterized for operation from 0°C to 70°C and the TLC320AC02I is characterized
for operation from –40°C to 85°C.
†
The TLC320AC02 is functionally equivalent to the TLC320AC01 and differs in the electrical specifications as shown
in Appendix C.
1–1
1.1 Features
•
•
•
•
•
•
•
•
•
General-Purpose Signal-Processing Analog Front End (AFE)
Single 5-V Power Supply
Power Dissipation . . . 100 mW Typ
Signal-to-Distortion Ratio . . . 70 dB Typ
Programmable Filter Bandwidths (Up to 10.8 kHz) and Synchronous ADC and DAC Sampling
Serial-Port Interface
Monitor Output With Programmable Gains of 0 dB, –8 dB, –18 dB, and Squelch
Two Sets of Differential Inputs With Programmable Gains of 0 dB, 6 dB, 12 dB, and Squelch
Differential or Single-Ended Analog Output With Programmable Gains of 0 dB, –6 dB, –12 dB,
and Squelch
•
•
•
•
•
Differential Outputs Drive 3-V Peak Into a 600-Ω Differential Load
Differential Architecture Throughout
1-µm Advanced LinEPIC Process
14-Bit Dynamic-Range ADC and DAC
2s-Complement Data Format
LinEPIC is a trademark of Texas Instruments Incorporated.
1–2
1.2 Functional Block Diagram
26
25
28
27
Filter
IN+
M
U
X
M
U
X
IN–
AUX IN+
AUX IN–
11
12
Serial
Port
DOUT
FS
ADC
1
MON OUT
M/S
14
13
MCLK
SCLK
18
ADC Channel
DAC Channel
Internal
Voltage
Reference
15
16
FC0
FC1
10
17
19
DIN
Filter
FSD
EOC
3
4
OUT+
OUT–
(sin x)/x
DAC
21
Correction
2
5
7
20
DGTL DGTL
GND
9
23
24
22
6
8
PWR
DWN
DAC
DAC
GND
ADC ADC
ADC SUBS DAC
RESET
V
V
V
V
GND
V
DD
DD
MID
DD
MID
Terminal numbers shown are for the FN package.
1.3 Terminal Assignments
FN PACKAGE
(TOP VIEW)
4
3
2 1 28 27 26
DAC V
DAC V
IN–
5
25
24
DD
6
ADC V
MID
DD
7
DAC GND
23 ADC V
MID
8
22
21
20
19
RESET
ADC GND
9
DGTL V
SUBS
DD
10
11
DIN
DGTL GND
EOC
DOUT
12 13 14 15 16 17 18
1–3
1.3 Terminal Assignments (Continued)
PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DIN
NC
1
48 NC
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
DOUT
FS
3
OUT–
NC
4
NC
5
NC
NC
6
OUT+
PWR DWN
NC
NC
7
SCLK
NC
8
9
MON OUT
NC
10
11
12
13
14
15
16
MCLK
FC0
FC1
NC
AUXIN+
AUXIN–
IN+
FSD
NC
IN–
NC
M/S
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC – No internal connection
1–4
1.4 Terminal Functions
TERMINAL
I/O
DESCRIPTION
Analog supply voltage for the ADC channel
†
‡
NAME
NO.
NO.
ADC V
24
32
I
DD
ADC V
23
30
O
MidsupplyfortheADCchannel(requiresabypasscapacitor). ADCV
buffered when used as an external reference.
mustbe
MID
MID
MID
ADC GND
AUX IN+
AUX IN–
22
28
27
5
27
38
37
49
51
I
I
Analog ground for the ADC channel
Noninverting input to auxiliary analog input amplifier
Inverting input to auxiliary analog input amplifier
Digital supply voltage for the DAC channel
I
DAC V
DAC V
I
DD
6
O
MidsupplyfortheDACchannel(requiresabypasscapacitor). DACV
buffered when used as an external reference.
mustbe
MID
DAC GND
DIN
7
54
1
I
I
Analog ground for the DAC channel
10
Data input. DIN receives the DAC input data and command information and is
synchronized with SCLK.
DOUT
11
3
O
Data output. DOUT outputs the ADC data results and register read contents.
DOUT is synchronized with SCLK.
DGTL V
9
20
19
59
22
17
I
I
Digital supply voltage for control logic
Digital ground for control logic
DD
DGTL GND
EOC
O
End-of-conversion output. EOC goes high at the start of the ADC conversion
periodandlowwhenconversioniscomplete. EOCremainslowuntilthenextADC
conversion period begins and indicates the internal device conversion period.
FC0
FC1
FS
15
16
12
11
12
4
I
I
Hardwarecontrolinput. FC0isusedinconjunctionwithFC1torequestsecondary
communication and phase adjustments. FC0 should be tied low if it is not used.
Hardwarecontrolinput. FC1isusedinconjunctionwithFC0torequestsecondary
communication and phase adjustments. FC1 should be tied low if it is not used.
I/O Frame synchronization. When FS goes low, DIN begins receiving data bits and
DOUT begins transmitting data bits. In master mode, FS is low during the
simultaneous 16-bit transmission to DIN and from DOUT. In slave mode, FS is
externallygeneratedandmustbelowforoneshift-clockperiodminimumtoinitiate
the data transfer.
FSD
17
14
O
Frame-synchronization delayed output. This active-low output synchronizes a
slave device to the frame synchronization timing of the master device. FSD is
applied to the slave FS input and is the same duration as the master FS signal but
delayed in time by the number of shift clocks programmed in the FSD register.
IN+
26
25
14
1
36
35
10
40
I
I
Noninverting input to analog input amplifier
IN–
Inverting input to analog input amplifier
MCLK
MON OUT
I
The master-clock input drives all the key logic signals of the AIC.
O
The monitor output allows monitoring of analog input and is a high-impedance
output.
M/S
18
16
I
Master/slave select input. When M/S is high, the device is the master and when
low, it is a slave.
†
‡
Terminal numbers shown are for the FN package.
Terminal numbers shown are for the PM package.
1–5
1.4 Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
†
‡
NAME
NO.
NO.
OUT+
3
43
O
Noninvertingoutputofanalogoutputpoweramplifier. OUT+candrivetransformer
hybrids or high-impedance loads directly in a differential connection or a
single-ended configuration with a buffered V
MID
.
OUT–
4
2
46
42
O
I
Inverting output of analog output power amplifier. OUT– is functionally identical
with and complementary to OUT+.
PWR DWN
Power-down input. When PWR DWN is taken low, the device is powered down
such that the existing internally programmed state is maintained. When PWR
DWN is brought high, full operation resumes.
RESET
SCLK
8
13
21
57
I
Reset input that initializes the internal counters and control registers. RESET
initiates the serial data communications, initializes all of the registers to their
default values, and puts the device in a preprogrammed state. After a low-going
pulse on RESET, the device registers are initialized to provide a 16-kHz
data-conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock
input signal.
8
I/O Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the
frame-synchronization interval. When configured as an output (M/S high), SCLK
isgeneratedinternallybydividingthemasterclocksignalfrequencybyfour.When
configured as an input (M/S low), SCLK is generated externally and
synchronously to the master clock. This signal clocks the serial data into and out
of the device.
SUBS
24
I
Substrate connection. SUBS should be tied to ADC GND.
†
‡
Terminal numbers shown are for the FN package.
Terminal numbers shown are for the PM package.
1–6
Processor
5.184 MHz
10.368 MHz
MCLK
SCLK
Divide by 4
1.296 MHz
2.592 MHz
A Register + A′ Register
(8 bits)
A Register
(8 bits)
2s Complement
FCLK [low-pass filter and
(sin x)/x filter clock]
Control
Normal
Phase Shift
B Register
(8 bits)
Single, A-Counter
Period
One-Shot
Conversion
Rate
Program Divide
A Counter
(8 bits)
Divide by 2
B Counter
576 kHz
288 kHz
Figure 1–1. Control Flow Diagram
Table 1–1. Operating Frequencies
LOW-PASS FILTER
B REGISTER CONTENTS
(Program No. of Filter Clocks)
(Decimal)
CONVERSION
RATE
HIGH-PASS
POLE FREQUENCY
(Hz)
FCLK
(kHz)
BANDWIDTH
(kHz)
(kHz)
144
288
432
3.6
20 (see Note 1)
18
15
7.2
8
9.6
14.4
36
40
48
72
10 (see Note 2)
7.2
20 (see Note 1)
18
15
14.4
16
19.2
28.8
72
80
96
10 (see Notes 2 and 3)
144
10.8
20 (see Note 1)
18
15 (see Note 3)
10 (see Notes 2 and 3)
21.6
24
28.8
43.2
108
120
144
216
NOTES: 1. The B register can be programmed for values greater than 20; however, since the sample rate is lower than
7.2 kHz and the internal filter remains at 3.6 kHz, an external antialiasing filter is required.
2. When the B register is programmed for a value less than 10, the ADC and the DAC conversions are not
completed before the next frame-sync signal and the results are in error.
3. The maximum sampling rate for the ADC channel is 43.2 kHz. The maximum rate for the DAC channel is
25 kHz.
1–7
1.5 Register Functional Summary
There are nine data registers that are used as follows:
Register 0
The No-op register. The 0 address allows phase adjustments to be made without
reprogramming a data register.
Register 1
Register 2
Register 3
The A register controls the count of the A counter.
The B register controls the count of the B counter.
The A′ register controls the phase adjustment of the sampling period. The adjustment is
equal to the register value multiplied by the input master period.
Register 4
Register 5
The amplifier gain register controls the gains of the input, output, and monitor amplifiers.
The analog configuration register controls:
•
•
•
•
The addition/deletion of the high-pass filter to the ADC signal path
The enable/disable of the analog loopback
The selection of the regular inputs or auxiliary inputs
The function that allows processing of signals that are the sum of the regular inputs and
the auxiliary inputs (V + V
)
IN
AUX IN
Register 6
The digital configuration register controls:
•
•
•
•
•
•
Selection of the free-run function
FSD [frame-synchronization (sync) delay] output enable/disable
Selection of 16-bit function
Forcing secondary communications
Software reset
Software power down
Register 7
Register 8
The frame-sync delay register controls the time delay between the master-device frame
sync and slave-device frame sync. Register 7 must be the last register programmed when
using slave devices since all register data is latched and valid on the sixteenth falling edge
of SCLK. On the sixteenth falling edge of SCLK, all delayed frame-sync intervals are shifted
by this programmed amount.
The frame-sync number register informs the master device of the number of slaves that are
connected in the chain. The frame-sync number is equal to the number of slaves plus one.
1–8
2
Detailed Description
2.1 Definitions and Terminology
ADC Channel
Codec Mode
d
All signal processing circuits between the analog input and the digital conversion
results at DOUT
The operating mode under which the device receives shift clock and frame-sync
signals from a host processor. The device has no slaves.
The d represents valid programmed or default data in the control register format
(see Section 2.19) when discussing other data-bit portions of the register.
Dxx
Bit position in the primary data word (xx is the bit number)
DAC Channel
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT+ and OUT–
Data Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is 16
shiftclocksregardlessofwhethertheshiftclockisinternallyorexternallygenerated.
The data transfer is initiated by the falling edge of the frame-sync signal.
DSxx
FCLK
Bit position in the secondary data word (xx is the bit number)
An internal clock frequency that is a division of MCLK that controls the low-pass filter
and (sinx)/x filter clock (see Figure 1–1 and Table 1-1).
f
The analog input frequency of interest
i
Frame Sync
The falling edge of the signal that initiates the data-transfer interval. The primary
framesyncstartstheprimarycommunications, andthesecondaryframesyncstarts
the secondary communications.
Frame Sync and
Sampling Period
The time between falling edges of successive primary frame-sync signals
Frame-Sync Interval The time period occupied by 16 shift clocks. Regardless of the mode of operation,
there is always an internal frame-sync interval signal that goes low on the rising
edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of
the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK.
f
The sampling frequency that is the reciprocal of the sampling period.
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
s
Host
Master Mode
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal and generates all delayed frame-sync signals necessary to
support slave devices.
Phase Adjustment
The programmed time variation from the falling edge of one frame-sync signal to the
falling edge of the next frame sync signal. The time variation is determined by the
contents of the A′ register. Since the time between falling edges of successive
frame-sync signals is the the sampling period, the sampling period is adjusted.
Primary (Serial)
Communications
The digital data-transfer interval. Since the device is synchronous, the signal data
words from the ADC channel and to the DAC channel occur simultaneously.
Secondary (Serial)
Communications
The digital control and configuration data-transfer interval into DIN and the register
read-data cycle from DOUT. The data-transfer interval occurs when requested by
hardware or software.
Signal Data
Slave Mode
The input signal and all of the converted representations through the ADC channel
and return through the DAC channel to the analog output. This is contrasted with
the purely digital software-control data.
The operating mode under which the device receives shift clock and frame-sync
signals from a master device.
2–1
Stand-Alone Mode
X
The operating mode under which the device generates and uses its own shift clock
and frame-sync signal. The device has no slave devices.
The X represents a don’t-care bit position within the control register format.
2.2 Reset and Power-Down Functions
2.2.1
Reset
The TLC320AC02 resets both the internal counters and registers, including the programmed registers, by
any of the following:
•
•
•
Applying power to the device, causing a power-on reset (POR)
Applying a low reset pulse to RESET
Reading in the programmable software reset bit (DS01 in register 6)
PWR DWN resets the counters only and preserves the programmed register contents.
2.2.2
Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are as follows:
1. Counter reset: This signal resets all flip-flops and latches that are not externally programmed with
the exception of those generating the reset pulse itself. In addition, this signal resets the software
power-down bit.
Counter reset = power-on reset + RESET + RESET bit + PWR DWN
2. Register reset: This signal resets all flip-flops and latches that are not reset by the counter reset
except those generating the reset pulse itself.
Register reset = power-on reset + RESET + RESET bit
Both reset signals are at least one master-clock period long and release on the falling edge of the master
clock.
2.2.3
Software and Hardware Power-Down
Given the definitions and conditions of RESET, the software-programmed power-down condition is cleared
by resetting the software bit (DS00 in register 6) to zero. It is also cleared by either cycling the power to the
device, bringing PWR DWN low, or bringing RESET low.
PWR DWN powers down the entire chip ( < 1 mA ). The software-programmable power-down bit only
powers down the analog section of the chip ( < 3 mA ), which allows a software power-up function. Cycling
PWR DWN high to low and back to high resets all flip-flops and latches that are not externally programmed,
thereby preserving the register contents.
When PWR DWN is not used, it should be tied high.
2.2.4
Register Default Values After POR, Software Reset, or RESET Is Applied
Register 1 – The A Register
The default value of the A-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
1
0
0
1
0
2–2
Register 2 – The B Register
The default value of the B-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
1
0
0
1
0
Register 3 – The A′ Register
The default value of the A′-register data is decimal 0 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
Register 4 – The Amplifier Gain-Select Register
The default value of the amplifier gain-select register data is shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
1
0
1
Register 5 – The Analog Control-Configuration Register
The power-up and reset conditions are as shown below. In the read mode, 8 bits are read but the 4 LSBs
are repeated as the 4 MSBs.
DS03 DS02 DS01 DS00
0
0
0
1
Register 6 – The Digital Configuration Register
The default value of DS07 – DS00 is 0 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
Register 7 – The Frame-Sync Delay Register
The default value of DS07 – DS00 is 0 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
Register 8 – The Frame-Sync Number Register
The default value of DS07 – DS00 is 1 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
1
2–3
2.3 Master-Slave Terminal Function
Table 2–1 describes the function of the master/slave (M/S) input. The only difference between master and
slave operations in the TLC320AC02 is that SCLK and FS are outputs when M/S is high and inputs when
M/S is low.
Table 2–1. Master-Slave Selection
†
MODE
M/S
H
FS
SCLK
Output
Input
Master and Stand Alone
Slave and Codec Emulation
Output
Input
L
†
When the stand-alone mode is desired or when the device is
permanently in the master mode, M/S must be high.
2.4 ADC Signal Channel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed
differentially until it is converted to digital data. The signal is amplified by the input amplifier at one of three
software-selectable gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the
input amplifier.
The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discretedigital
words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit
digital words, representing sampled values of the analog input signal, are clocked out of the serial port
(DOUT), one word for each primary communication interval. During secondary communications, the data
previously programmed into the registers can be read out with the appropriate register address and with the
read bit set to 1. When a register read is not requested, all 16 bits are 0.
2.5 DAC Signal Channel
DIN receives the 16-bit serial data word (2s complement) from the host during the primary communications
interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog
voltage by the DAC with a sample and hold and then through a (sin x)/x correction circuit and a smoothing
filter. An output buffer with three software-programmable gains (0 dB, –6 dB, and –12 dB), as shown in
register 4, drives the differential outputs OUT+ and OUT–. A squelch mode can also be programmed for
the output buffer. During secondary communications, the configuration program data are read into the
device control registers.
2.6 Serial Interface
The digital serial interface consists of the shift clock, the frame-synchronization signal, the ADC-channel
data output, and the DAC-channel data input. During the primary 16-bit frame-synchronization interval, the
SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.
During the secondary frame-synchronization interval, the SCLK transfers the register read data from DOUT
when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into
DIN. The functional sequence is shown in Figure 2–1.
2–4
†
[ (B register)/2] FCLK Periods
Frame-Sync Interval
(primary communication)
Frame-Sync Interval
(secondary
communication)
SCLK
FS
16 SCLKs
16 SCLKs
ADC Conversion Result
DAC Input Data
Register Read Data or All 0s
DOUT
DIN
Control and Device Parameter
Data
†
The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods.
Figure 2–1. Functional Sequence for Primary and Secondary Communication
2.7 Number of Slaves
The maximum number of slaves is determined by the sum of the individual device delays from the
frame-sync (FS) input low to the frame-sync delayed (FSD) low for all slaves according to equation 1:
(1)
(n) / tp(FS–FSD) < 1/2 shift-clock period
Where:
n is the number of slave devices.
Example:
From equation 1 above, the number of slaves is given by equation 2:
1
2
1
(2)
(n)
x (SCLK period) x
(
)
FSD
tp FS
assuming the master clock is 10.368 MHz and the shift clock is 2.5965 MHz and tp(FS – FSD) is 40 ns, then
according to equation 3, the number of slaves is:
1000
192
1
1
2
1
(3)
n
x
x
4.8
40 ns
2.5965 MHz
The maximum number of slaves under these conditions is four.
2–5
2.8 Required Minimum Number of MCLK Periods
Master with slave operation is summarized in the following sections.
2.8.1
TLC320AC02 AIC Master-Slave Summary
After initial setup and the master and slave frame syncs are separated, when secondary communication is
needed for a slave device, a 11 must be placed in the 2 LSBs of each primary data word for all devices in
the system, master and slave, by the host processor. In other words, all AICs must receive secondary frame
requests.
The host processor must issue the command by setting D01 and D00 to a 1 in the primary frame sync data
word of all devices. Then the master generates the master primary frame sync and, after the number of shift
clocks set by the FSD register value, the slave primary frame sync intervals. Then, after (B register value/2)
FCLK periods, the master secondary frame sync occurs first, and then the slave secondary frame sync
occurs. These are also rippled through the slave devices.
In other words, when a secondary communications interval is requested by the host processor as described
above:
1. The master outputs the master primary frame sync interval, and then the slave primary frame
sync intervals after the FSD register value number of shift clocks.
2. After (B register value/2) FCLK periods, the master then outputs the master secondary frame
sync interval, and after the FSD register value number of shift clocks, the slave secondary frame
sync intervals.
This sequence is shown in Figure 2–2.
The host must keep track of whether the master or a slave is then being addressed and also the number
of slave devices. The master always outputs a 00 in the last 2 bits of the DOUT word, and a slave always
outputs a 1 in the LSB of the DOUT word. This information allows the system to recognize a starting point
by interrogating the least significant bit of the DOUT word. If the LSB is 0, then that device is the master,
and the system is at the starting point.
Note: This identification always happens except in 16-bit mode when the 2 LSBs are not available
for identification purposes.
(B Register Value/2) FCLK Periods
Sampling Period
FSD Value
in SCLKs
Frame Sync
Sequence
MP
SP1
SP2
SPn
MS
SS1
SS2
SSn
MP
Period Symbol
Periods shown: Each period must be a minimum of 16 SCLKs plus 2 additional SCLKs
MP
= Master Primary Period
= 1st Slave Primary Period
= 2nd Slave Primary Period
= nth Slave Primary Period
MS
= Master Secondary Period
SP1
SP2
SPn
SS1
SS2
SSn
= 1st Slave Secondary Period
= 2nd Slave Secondary Period
= nth Slave Secondary Period
Figure 2–2. Timing Sequence
2–6
2.8.2
Notes on TLC320AC01/02 AIC Master-Slave Operation
Master/slave operational detail is summarized in the following notes:
1. The slave devices can be programmed independently of the master as long as the clock divide
register numbers are not changed. The gain settings, for example, can be changed
independently.
2. The method that is used to program a slave independently is to request a secondary
communicationofthemasterandallslavesandripplethedelayedframesynctothedesiredslave
device to be programmed.
3. Secondary frame syncs must be requested for all devices in the system or none. This is required
so that the master generates secondary frames for the slaves and allows the slaves to know that
the second frame syncs they receive are secondary frame syncs. Each device in the system must
receive a secondary frame request in its corresponding primary frame sync period (11 in the last
2 LSBs).
4. Calculation of the sampling frequency in terms of the master clock and the shift clock and the
respective register ratios is (see equations 4–6):
FCLK
B register value
Sampling frequency
f
s
(
)
f MCLK
(4)
(5)
(
)
B register value
2 (A register value)
Therefore,
(
)
f MCLK
(
)
(
)
B register value
2
A register value
f
s
and in terms of the shift clock frequency, since
f(MCLK)
4
f(SCLK)
then
(
)
B register value
f(SCLK)
(A register value)
2
f
s
Number of SCLK periods
Sampling period
(6)
5. The minimum number of shift clocks between falling edges of any two frame syncs is 18 because
the frame sync delay register minimum number is 18.
When a secondary communication is requested by the host, the master secondary frame sync
begins at the middle of the sampling period (followed by the slave secondary frame syncs), so all
primary frame sync intervals (master and slave) must occur within one-half the sampling time.
2–7
The first secondary frame-sync falling edge, therefore, occurs at the following time (see
equation 7):
B register value
(
)
FCLK periods
Time to first secondary frame sync
2
A register value
A register value
B register value (number of MCLK periods)
B register value
(number of SCLK periods)
(7)
4
6. Number of frame sync intervals using equation 8.
All master and slave primary frame sync intervals must occur within the time of equation 7.
Since 18 shift clocks are required for each frame sync interval, then the number of frame sync
intervals from equation 8 is:
A register value
B register value
Number of frame sync intervals
4
18 (SCLKs frame sync interval)
A register value
B register value
(8)
72
7. Number of devices, master and slave, in terms of f(MCLK) and f .
s
Substituting the value from equation 5 for the A × B register value product gives the total number
of devices, including the master and all slaves that can be used, for a given master clock and
sampling frequency. Therefore, using equation 9:
f(MCLK)
Number of devices
(9)
144
f
s
8. Number of devices, master and slave, if slave devices are reprogrammed.
Equation 9 does not include reprogramming the slave devices after the frame sync delay occurs.
So if programming is required after shifting the slave frame syncs by the FSD register, then the
total number of devices is given by equation 10 is:
f(MCLK)
Number of devices
(10)
288
f
s
9. Example of the maximum number of devices if the slave devices are reprogrammed assuming
the following values:
f(MCLK)
10.368 MHz, f
8 kHz
s
then from equation 10,
Maximum number of devices
10.368 MHz
288 (8 kHz)
4.5
therefore, one master and three slaves can be used.
2–8
2.9 Operating Frequencies
2.9.1
Master and Stand-Alone Operating Frequencies
The sampling (conversion) frequency is derived from the master-clock (MCLK) input by equation 11:
MCLK
f
s
Sampling (conversion) frequency
(11)
(A register value)
(B register value)
2
The inverse is the time between the falling edges of two successive primary frame-synchronization signals.
The input and output data clock (SCLK) frequency is given in equation 12:
MCLK frequency
(12)
SCLK frequency
4
2.9.2
Slave and Codec Operating Frequencies
The slave operating frequencies are either the default values or programmed by the control data word from
the master and codec conversion and the data frequencies are determined by the externally applied SCLK
and FS signals.
2.10 Switched-Capacitor Filter Frequency (FCLK)
The filter clock (FCLK) is an internal clock signal that determines the filter band-pass frequency and is the
B counter clock. The frequency of the filter clock is derived by equation 13:
MCLK
(A register value)
(13)
FCLK
2
2.11 Filter Bandwidths
The low-pass (LP) filter –3 dB corner is derived in equation 14:
FCLK
40
MCLK
(A register value)
(14)
(15)
f (LP)
40
2
The high-pass (HP) filter –3 dB corner is derived in equation 15:
Sampling frequency
f (HP)
MCLK
200
200
2
(A register value)
(B register value)
2.12 Master and Stand-Alone Modes
The difference between the master and stand-alone modes is that in the stand-alone mode there are no
slave devices. Functionally these two modes are the same. In both, the AIC internally generates the shift
clock and frame-sync signal for the serial communications. These signals and the filter clock (FCLK) are
derived from the input master clock.The master clock applied at the MCLK input determines the internal
device timing. The shift clock frequency is a divide-by-four of the master clock frequency and shifts both the
input and output data at DIN and DOUT, respectively, during the frame-sync interval (16 shift clocks long).
To begin the communication sequence, the device is reset (see Section 2.2.1), and the first frame sync
occurs approximately 648 master clocks after the reset condition disappears.
2.12.1 Register Programming
All register programming occurs during secondary communications, and data is latched and valid on the
sixteenth falling edge of SCLK. After a reset condition, eight primary and secondary communications cycles
are required to set up the eight programmable registers. Registers 1 through 8 are programmed in
secondary communications intervals 1 through 8, respectively. If the default value for a particular register
is desired, that register does not need to be addressed during the secondary communications. The no-op
command addresses the pseudo-register (register 0), and no register programming takes place during this
communications. The no-op command allows phase shifts of the sampling period without reprogramming
any register.
During the eight register programming cycles, DOUT is in the high-impedance state. DOUT is released on
the rising edge of the eighth primary internal frame-sync interval. In addition, each register can be read back
2–9
during DOUT secondary communications by setting the read bit to 1 in the appropriate register. Since the
register is in the read mode, no data can be written to the register during this cycle. To return this register
to the write mode requires a subsequent secondary communication (see Section 2.19 for detailed register
description).
2.12.2 Master and Stand-Alone Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the filter clock (FCLK). The B counter is clocked by FCLK with the following functional
sequence:
1. The B counter starts counting down from the B register value minus one. Each count remains in
the counter for one FCLK period including the zero count. This total counter time is referred to
as the B cycle. The end of the zero count is called the end of B cycle.
2. When the B counter gets to a count of nine, the analog-to-digital (A-to-D) conversion starts.
3. The A-to-D conversion is complete ten FCLK periods later.
4. FS goes low on a rising edge of SCLK after the A-to-D conversion is complete. That rising edge
of SCLK must be preceded by a falling edge of SCLK, which is the first falling edge to occur after
the end of B cycle.
5. The D-to-A conversion cycle begins on the rising edge of the internal frame-sync interval and is
complete ten FCLK periods later.
2.13 Slave and Codec Modes
The only difference between the slave and codec modes is that the codec mode is controlled directly by the
host and does not use a delayed frame-sync signal. In both modes, the shift clock and the frame sync are
bothexternallygeneratedandmustbesynchronouswithMCLK. Theconversionfrequencyissetbythetime
interval of externally applied frame-sync falling edges except when the free-run function is selected by bit 5
of register 6 (see Section 2.15.4). The slave device or devices share the shift clock generated by the master
device but receive the frame sync from the previous slave in the chain. The Nth slave FS receives the
(N–1)st slave FSD output and so on. The first slave device in the chain receives FSD from the master.
2–10
2.13.1 Slave and Codec Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through
3 of the B cycle description in the master mode but differs as follows:
1. Same as master
2. Same as master
3. Same as master
4. All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle.
5. All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes
low. This operation provides the synchronization necessary when using an external FS signal.
6. The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.
In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC if the free-run function has not been
selected (see Subsection 2.15.4). In the codec mode, there is usually no need for phase adjustments;
however, any required phase adjustments must be made by adjusting the external frame-sync timing
(sampling time).
2.13.2 Slave Register Programming
When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary frame-
sync interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that
frame- sync interval. After the FSD register programming is completed for the master and slave, the slave
primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host
serial port for data transfers for itself and all slave devices.
The number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync
intervals generated by the master is equal to the number of slaves plus one (see Section 2.7). These master
frame-sync intervalsareseparatedintimebythedelaytimespecifiedbytheFSDregister(register7). These
master-generated intervals are the only frame-sync interval signals applied to the host serial port to provide
the data-transfer time slot for the slave devices.
2.14 Terminal Functions
2.14.1 Frame-Sync Function
The frame-sync signal indicates that the device is ready to send and receive data for both master and slave
modes. The data transfer begins on the falling edge of the frame-sync signal.
2.14.1.1 Frame Sync (FS), Master Mode
The frame sync is generated internally. FS goes low on the rising edge of SCLK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
sync for each slave that is being used.
2–11
2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1. When the FSD register data is 0, then FSD goes low on the falling edge of SCLK prior to the rising
edge of SCLK when FS goes low (see Figure 4–4).
2. When the FSD register data is greater than 17, then FSD goes low on a rising edge of SCLK that
is the FSD register number of SCLKs after the falling edge of FS.
Register data values from 1 to 17 should not be used.
2.14.1.3 Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see
Subsection 2.15.4). The external frame-sync width must be a minimum of one shift clock to be recognized
and can remain low until the next data frame is required.
2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1. When the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4–5).
2. When the FSD register data is greater than 17, FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.
Data values from 1 to 17 should not be used.
2.14.2 Data Out (DOUT)
DOUT is placed in the high-impedance state on the seventeenth rising edge of SCLK (internal or external)
after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to 0 (see Section 2.16). If no register read is requested, the
secondary word is all zeroes.
2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.
2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4–7). The falling edge of
frame sync can occur ±1/4 SCLK period around the SCLK rising edge (see Figure 4–3). The most
significant data bit then appears on DOUT.
2.14.3 Data In (DIN)
In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16).
2.14.4 Hardware Program Terminals (FC1 and FC0)
These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits D01 and D00 of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FC0 are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17 and Table 2–3).
2–12
2.14.5 Midpoint Voltages (ADC V
and DAC V
)
MID
MID
Since the device operates at a single-supply voltage, two midpoint voltages are generated for internal signal
processing. ADC V is used for the ADC channel reference, and DAC V is used for the DAC channel
MID
MID
reference. Two references minimize channel-to-channel noise and crosstalk. ADC V
and DAC V
MID
MID
must be buffered when used as a reference for external signal processing.
2.15 Device Functions
2.15.1 Phase Adjustment
In some applications, such as modems, the device sampling period may require an adjustment to
synchronize with the incoming bit stream to improve the signal-to-noise ratio. The TLC320AC02 can adjust
the sampling period through the use of the A′ register and the control bits.
2.15.1.1 Phase-Adjustment Control
A phase adjustment is a programmed variation in the sampling period. A sampling period is adjusted
according to the data value in the A′ register, and the phase adjustment is that number of master clocks
(MCLK). An adjustment is made during device operation with data bits D01 and D00 in the primary
communication, with data bits DS15 and DS14 in the secondary word or in combination with the hardware
terminals FC1 and FC0 (see Table 2–3). This adjustment request is latched on the rising edge of the next
internal frame-sync interval and is only valid for the next sampling period. To repeat the phase adjustment,
another phase request must be initiated.
2.15.1.2 Use of the A′ Register for Phase Adjustment
The A′ register value makes slight timing adjustments to the sampling period. The sampling period
increases or decreases according to the sign of the programmed A′ register value and the state of data bits
D01 and D00 in the primary data word.
The general equation for the conversion frequency is given in equation 16:
MCLK
f = conversion frequency
(16)
s
(2
A register value
B register value)
(A register value)
Therefore, if A′ = 0, the device conversion (sampling) frequency and period is constant.
If a nonzero A′ value is programmed, the sampling frequency and period responds as shown in Table 2–2.
Table 2–2. Sampling Variation With A′
SIGN OF THE A′ REGISTER VALUE
D01
D00
PLUS VALUE
(+)
NEGATIVE VALUE
(–)
1
Frequency decreases,
period increases
Frequency increases,
period decreases
0
1
(increase command)
0
Frequency increases,
period decreases
Frequency decreases,
period increases
(decrease command)
An adjustment to the sampling period, which must be requested through D01 and D00 of the primary data
word to DIN, is valid for the following sampling period only. When the adjustment is required for the
subsequent sampling period, it must be requested again through D01 and D00 of the primary data word.
For each request, only the sampling period occurring immediately after the primary data word request is
affected.
2–13
The amount of time shift in the entire sampling period (1/f ) is as follows:
s
When the sampling period is set to 125 µs (8 kHz), the A′ register is loaded with decimal 10 and the
TLC320AC02masterclockfrequencyis10.386MHz. Theamountoftimeeachsamplingperiodisincreased
or decreased, when requested, is given in equation 17:
Time shift = (A′ register value) × (MCLK period)
(17)
The device changes the entire sampling period by only the MCLK period times the A′ register value as given
in equation 18:
Change in sampling period = contents of A′ register × master clock period
= 10 × 96.45 ns = 964 ns (less than 1% of the sampling period)
(18)
The sampling period changes by 964.5 ns each time the phase adjustment is requested by the primary data
word (i.e., once per sampling period).
It is evident then that the change in sampling period is very small compared to the sampling period. To
observe this effect over a long period of time (> sampling period), this change must be continuously
requested by the primary data word. If the adjustment is not requested again, the sampling period changes
onlyonceanditmayappearthattherewasnoexecutionofthecommand. Thisisespeciallytruewhenbench
testing the device. Automatic test equipment can test for results within a single sampling period.
Internally, the A′ register value only affects one cycle (period) of the A counter. The A and A′ values are
additive, but only for one A-counter period. The A counter begins the first count at the default or programmed
A-register value and counts down to the A′-register value. As the A′ value increases or decreases, the first
clock cycle from the A counter is lengthened or shortened. The initial A-counter period is the only counter
period affected by the A′ register such that only this single period is increased or decreased.
2.15.2 Analog Loopback
This function allows the circuit to be tested remotely. In loopback, OUT+ and OUT– are internally connected
to IN+ and IN–. The DAC data bits D15 to D02 that are applied to DIN can be compared with the ADC output
data bits D15 to D02 at DOUT. There are some differences due to the ADC and DAC channel offset. The
loopback function is implemented by setting DS01 and DS00 to zero in control register 5 (see Section 2.19).
When analog loopback is enabled, the external inputs to IN+ and IN– are disconnected, but the signals at
OUT+ and OUT– may still be read.
2.15.3 16-Bit Mode
In the 16-bit mode, the device ignores the last two control bits (D01 and D00) of the primary word and
requests continual secondary communications to occur. By ignoring the last two primary communication
bits, compatibility with existing 16-bit software can be maintained. This function is implemented by setting
bit DS03 to 1 in register 6. To return to normal operation, DS03 must be reprogrammed to 0.
2.15.4 Free-Run Mode
With the free-run bit set in register 6, the external shift clock and frame sync control only the data transfer.
The ADC and DAC timing are controlled by the A and B register values, and the phase-shift adjustment must
be done as if the device is in stand-alone mode (by the software or the state of FC1 and FC0).
Phase adjustment cannot be made by adjustment of the frame-sync timing. The external frame sync must
occur within 1/2 FCLK period of the internal frame sync (FCLK as determined by the values of the A and
B registers).
When the external frame sync occurs simultaneously with the internal load, the data-transfer request by the
external frame sync takes precedence over an internal load command. The latching of the ADC conversion
data in the output register is inhibited until the current 16 bits are shifted out of the register by the shift clock.
2.15.5 Force Secondary Communication
With bit 2 in register 6 set to 1, secondary communication is requested continuously. It overrides all software
and hardware requests concerning secondary communication. Phase shifting, however, can still be
performed with the software and hardware.
2–14
2.15.6 Enable Analog Input Summing
By setting bits DS01 and DS00 to 11 in register 5, the normal analog input voltage is summed with the
auxiliaryinputvoltage. ThegainfortheanaloginputamplifierissetbydatabitsDS03andDS02inregister 4.
2.15.7 DAC Channel (sin x)/x Error Correction
The (sin x)/x compensation filter is designed for zero (sin x)/x error using a B-register value of 15. Since the
filter cannot be removed from the signal path, operation using another B-register value results in an error
in the reconstructed analog output. The error is given by equation 19. Any error compensation needed by
a given application can be performed in the software.
2
f
A
B
sin
sin
f
MCLK
15
B
DAC channel frequency response error
20
log
(19)
10
30
f
A
f
MCLK
where:
f
= the frequency of interest
f
= the TLC320AC02 master-clock frequency
= the A-register value
MCLK
A
B
= the B-register value
and the arguments of the sin functions are in radians.
2.16 Serial Communications
2.16.1 Stand-Alone and Master-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the stand-alone and master modes, the sequence in Figure 2–2 shows the relationship between the
primary and secondary communications interval, the data content into DIN, and the data content from
DOUT.
The TLC320AC02 can provide a phase-shift command or the next secondary communications interval by
decoding 1) the programmed state of the FC1 and FC0 inputs and the D01 and D00 data bits in the primary
data word, or 2) the state of the FC1 and FC0 inputs and the DS15 and DS14 data bits in the secondary
data word (see Table 2–3). When DS13 (the R/W bit) is the default value of 0, all 16 bits from DOUT are
0 during secondary communication. However, when the R/W bit is set to 1 in the secondary communication
control word, the secondary transmission from DOUT still contains 0s in the eight MSBs. The lower order
8 bits contain the data of the register currently being addressed. This function provides register status
information for the host.
2–15
†
[ (B register)/2] FCLK Periods
Primary Frame Sync
(16 SCLKs long)
Secondary Frame Sync
(16 SCLKs long)
FS
DOUT
DIN
2s-Complement ADC Output
(14 bits plus 00 for the two LSBs)
16 Bits All 0s, Except When in
Read Mode (then least significant
8 bits are register data)
Input Data for the Internal Registers
(16 bits containing control,
address, and data information)
2s-Complement Input for the DAC
Channel (14 bits plus two
function bits). If the 2 LSBs Are
Set to 1, Secondary Frame Sync Is
Generated by the TLC320AC02
†
The time between the primary and secondary frame sync is the time equal to filter clock (FCLK) period multiplied by the
B-register contents divided by two. The time interval is rounded to the nearest shift clock. The secondary frame-sync
signal goes from high to low on the next shift clock low-to-high transition after (B register/2) filter clock periods.
Figure 2–3. Master and Stand-Alone Functional Sequence
2.16.2 Slave and Codec-Mode Word Sequence and Information Content During
Primary and Secondary Communications
For the slave and codec modes, the sequence is basically the same as the stand-alone and master modes
with the exception that the frame sync and the shift clock are generated and controlled externally as shown
in Figure 2–3. For the codec mode, the frame-sync pulse width needs to be a minimum of one shift clock
long. The timing relationship between the frame sync and shift clock is shown in the timing diagrams. Phase
shifting is usually not required in the slave or codec mode because the frame-sync timing can be adjusted
externally if required.
1 SCLK Minimum
1 SCLK Minimum
FS
Primary Frame Sync
Secondary Frame Sync
2s-Complement ADC Output
(14 bits plus 00 for the 2 LSBs in
master and stand-alone mode and
01 in slave mode)
16 Bits, All 0s, Except When in
Read Mode (then least significant
8 bits are register data)
DOUT
Input Data for the Internal
Registers (16 bits containing
control, address, and data
information)
DIN
2s-Complement Input for the DAC
Channel (14 bits plus two
function bits)
NOTE A: The time between the primary and secondary frame syncs is determined by the application; however, enough
time must be provided so that the host can execute the required number of software instructions in the time
between the end of the primary data transfer (rising edge of the primary frame-sync interval) and the falling
edge of the secondary frame sync (start of secondary communications).
Figure 2–4. Slave and Codec Functional Sequence
2–16
2.17 Request for Secondary Serial Communication and Phase Shift
The following paragraphs describe a request for secondary serial communication and phase shift using
hardware control inputs FC1 and FC0, primary data bits D01 and D00, and secondary data bits DS15 and
DS14.
2.17.1 Initiating a Request
Combinations of FC1 and FC0 input conditions, bits D01 and D00 in the primary serial data word, FC1 and
FC0, and bits DS15 and DS14 in the secondary serial data word can initiate a secondary serial
communication or request a phase shift according to the following rules (see Table 2–3).
1. Primary word phase shifts can be requested by either the hardware or software when the other
set of signals are 11 or 00. If both hardware and software request phase shifts, the software
request is performed.
2. Secondary words can be requested by either the software or hardware at the same time that the
other set of signals is requesting a phase shift.
3. Hardware inputs FC1 and FC0 are ignored during the secondary word unless DS15 and DS14
are 11. When DS15 and DS14 are 01 or 10, the corresponding phase shift is performed. When
DS15 and DS14 are 00, no phase shift is performed even when the hardware requests a phase
shift.
2.17.2 Normal Combinations of Control
The normal combinations of control are as follows:
1. Use D01 and D00 and DS15 and DS14 to request phase shifts and secondary words by holding
FC1 and FC0 to 00.
2. Use FC1 and FC0 exclusively to request phase shifts and secondary words by holding D01 and
D00 to 00 and DS15 and DS14 to 11.
3. Use D01 and D00 only to request secondary words and FC1 and FC0 to perform phase shifts
once per period by holding DS15 and DS14 to 00.
2.17.3 Additional Control Options
Additional control options are unusual and are rarely needed or used; however, they are as follows:
1. Use D01 and D00 only to request secondary words and FC1 and FC0 to perform phase shifts
twice per period by holding DS15 and DS14 to 11.
2. UseFC1andFC0exclusivelytorequestsecondarywordsandD01andD00andDS15andDS14
to perform phase shifts twice per period.
3. Use FC1 and FC0 to perform the phase shift after the primary word and DS15 and DS14 to
perform a phase shift after the secondary word by holding D01 and D00 to 11.
2–17
Table 2–3. Software and Hardware Requests for
Secondary Serial-Communication and Phase-Shift Truth Table
PHASE-SHIFT
CONTROL
BITS
HARDWARE
TERMINALS
ADJUSTMENT
WITHIN PRIMARY
OR SECONDARY
DATA WORD
SECONDARY
REQUEST
(see Note 1)
(see Section 2.15.1)
D01
D00
FC1
FC0
EARLIER
LATER
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
Primary
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
1
1
1
1
DS15 DS14
FC1
FC0
EARLIER
LATER
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
No request can be made for
secondary communication
within the secondary word.
Secondary
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
1
0
0
1
0
0
NOTE 1: The 0 state indicates that a secondary communication is not being requested. The 1 state indicates that a
secondary communication is being requested.
2.18 Primary Serial Communications
Primary serial communications transfer the 14-bit DAC input plus two control bits (D01 and D00) to DIN of
the TLC320AC02.They simultaneously transfer the 14-bit ADC conversion result from DOUT to the
processor. The 2 LSBs are set to 0 in the ADC result.
2–18
2.18.1 Primary Serial Communications Data Format
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
14-bit DAC Conversion Result
2s-Complement Format
Control Bits
†
†
Sincethesupplyvoltageissingleended,thereferencefor2s-complementformatisADCV
this reference have a 0 as the MSB, and voltages below this reference have a 1 as the MSB.
. Voltagesabove
MID
During primary serial communications, when D01 and D00 are both high in the DAC data word to DIN, a
subsequent 16 bits of control information is received by the device at DIN during a secondary
serial-communication interval. This secondary serial-communication interval begins at 1/2 theprogrammed
conversion time when the B register data value is even or 1/2 the programmed value minus one FCLK when
the B register data value is odd. The time between primary and secondary serial communication is
measured from the falling edge of the primary frame sync to the falling edge of the secondary frame sync
(see Section 2.19 for function and format of control words).
2.18.2 Data Format From DOUT During Primary Serial Communications
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
14-Bit ADC Conversion Result
2s-Complement Format
D15 is the Sign Bit
D01
D00
0
0
Master Mode
Slave Mode
D01
D00
0
1
2.19 Secondary Serial Communications
2.19.1 Data Format to DIN During Secondary Serial Communications
There are nine 16-bit configuration and control registers numbered from zero to eight. All register data
contents are represented in 2s-complement format. The general format of the commands during secondary
serial communications is as follows.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
(2 bits) Bit
Register Address
(5 bits)
Register Data Value
(8 bits)
All control register words are latched in the register and valid on the sixteenth falling edge of SCLK.
2.19.2 Control Data-Bit Function in Secondary Serial Communication
2.19.2.1 DS15 and DS14
In the secondary data word, bits DS15 and DS14 perform the same control function as the primary control
bits D01 and D00 do in the primary data word.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
Register Address
Register Data
Hardware terminals FC1 and FC0 are valid inputs when DS15 and DS14 are both high, and they are ignored
for all other conditions.
2–19
2.19.2.2 DS13 (R/W Bit)
Reset and power-up procedures set this bit to a 0, placing the device in the write mode. When this bit is set
to 1, however, the previous data content of the register being addressed is read out to the host from DOUT
as the least significant 8 bits of the 16-bit secondary word. The first 8 bits remain set to 0. Reading the data
out is nondestructive, and the contents of the register remain unchanged.
A. Write Mode (DS13 = 0)
Data In. The data word to DIN has the following general format in the write mode.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits
0
Register Address
Register Data
Data Out. The shift clock shifts out all 0s as the pattern to the host from DOUT.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B. Read Mode (DS13 = 1)
Data In. The data word to DIN has the following format to allow a register read. Phase shifts can
also be done in the read mode.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits
1
Register Address
Ignored
Data Out. The shift clock clocks out the data of the register addressed from DOUT in the read mode in
the 8 LSBs.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
Register Data
2.20 Internal Register Format
2.20.1 Pseudo-Register 0 (No-Op Address)
This address represents a no-operation command. No register I/O operation takes place, so the device can
receive secondary commands for phase adjustment without reprogramming any register. A read of the
no-op is 0. The format of the command word is as follows:
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits
X
0
0
0
0
0
X
X
X
X
X
X
X
X
2.20.2 Register 1 (A Register)
The following command loads DS07 (MSB) – DS00 into the A register.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W Register Data
0
0
0
0
1
The data in DS07 – DS00 determines the division of the master clock to produce the internal FCLK.
FCLK frequency = MCLK/(A register contents × 2)
2–20
The default value of the A-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
1
0
0
1
0
2.20.3 Register 2 (B Register)
The following command loads DS07 (MSB) – DS00 into the B register.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W Register Data
0
0
0
1
0
The data in DS07 – DS00 controls the division of FCLK to generate the conversion clock as given in
equation 20:
Conversion frequency
FCLK (B register contents)
MCLK
A register contents
(20)
2
B register contents
The default value of the B-register data is decimal 18 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
1
0
0
1
0
2.20.4 Register 3 (A′ Register)
The following command contains the A′-register address and loads DS07(MSB) – DS00 into the A′ register.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
0
0
0
1
1
Register Data
The data in DS07 – DS00 is in 2s-complement format and controls the number of master-clock periods that
the sampling time is shifted.
The default value of the A′-register data is 0 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
2–21
2.20.5 Register 4 (Amplifier Gain-Select Register)
The following command contains the amplifier gain-select register address with selection code for the
monitor output (DS05–DS04), analog input (DS03–DS02), and analog output (DS01–DS00)
programmable gains.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
0
0
1
0
0
X
X
*
*
*
*
*
*
Monitor output gain = squelch
Monitor output gain = 0 dB
Monitor output gain = –8 dB
Monitor output gain = –18 dB
0
0
0
1
1
1
0
1
Analog input gain = squelch
Analog input gain = 0 dB
Analog input gain = 6 dB
Analog input gain = 12 dB
0
0
1
0
1
0
1
1
Analog output gain = squelch
Analog output gain = 0 dB
Analog output gain = –6 dB
Analog output gain = –12 dB
0
0
1
0
1
0
1
1
Thedefaultvalueofthemonitoroutputgainissquelch, whichcorrespondstodatabitsDS05andDS04equal
to 00 (binary).
The default value of the analog input gain is 0 dB, which corresponds to data bits DS03 and DS02 equal
to 01 (binary).
The default value of the analog output gain is 0 dB, which corresponds to data bits DS01 and DS00 equal
to 01 (binary).
The default data value is shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
1
0
1
2.20.6 Register 5 (Analog Configuration Register)
The following command loads the analog configuration register with the individual bit functions described
below.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
Must be set to 0
0
0
1
0
1
X
X
X
X
*
0
*
*
*
High-pass filter disabled
High-pass filter enabled
1
0
Analog loopback enabled
0
0
1
1
0
1
0
1
Enables IN+ and IN– (disables AUXIN+ and AUXIN–)
Enables AUXIN+ and AUXIN– (disables IN+ and IN–)
Enable analog input summing
The default value of the high-pass-filter enable bit is 0, which places the high-pass filter in the signal path.
The default values of DS01 and DS00 are 0 and 1 which enables IN+ and IN–.
2–22
The power-up and reset conditions are as shown below.
DS03 DS02 DS01 DS00
0
0
0
1
In the read mode, eight bits are read but the 4 LSBs are repeated as the 4 MSBs.
2.20.7 Register 6 (Digital Configuration Register)
The following command loads the digital configuration register with the individual bit functions described
below.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
0
0
1
1
0
X
X
*
*
*
*
*
*
ADC and DAC conversion free run
Inactive
1
0
FSD output disable
Enable
1
0
16-Bit mode, ignore primary LSBs
Normal operation
1
0
Force secondary communications
Normal operation
1
0
Software reset
(upon reset, this bit is automatically reset to 0)
Inactive reset
1
0
Software power-down active (automatically reset to 0
after PWR DWN is cycled high to low and back to high)
1
0
Power-down function external
(uses PWR DWN)
The default value of DS07–DS00 is 0 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
2.20.8 Register 7 (Frame-Sync Delay Register)
The following command contains the frame-sync delay (FSD) register address and loads DS07
(MSB)–DS00 into the FSD register. The data byte (DS01–DS00) determines the number of SCLKs
between FS and the delayed frame-sync signal, FSD. The minimum data value for this register is
decimal 18.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
0
0
1
1
1
Register Data
The default value of DS07 – DS00 is 0 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
0
When using a slave device, register 7 must be the last register programmed.
2–23
2.20.9 Register 8 (Frame-Sync Number Register)
The following command contains the frame-sync number (FSN) register address and loads DS07
(MSB)–DS00 into the FSN register. The data byte determines the number of frame-sync signals generated
by the TLC320AC02. This number is equal to the number of slaves plus one.
DS15 DS14 DS13 DS12 DS11 DS10 DS09 DS08 DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
Control Bits R/W
0
1
0
0
0
Register Data
The default value of DS07–DS00 is 1 as shown below.
DS07 DS06 DS05 DS04 DS03 DS02 DS01 DS00
0
0
0
0
0
0
0
1
2–24
3
Specifications
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
†
(Unless Otherwise Noted)
Supply voltage range, DGTL V
(see Notes 1 and 2) . . . . . . . . . . . . . . . –0.3 V to 6.5 V
DD
Supply voltage range, DAC V
Supply voltage range, ADC V
Differential supply voltage range, DGTL V
(see Notes 1 and 2) . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
(see Notes 1 and 2) . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
DD
DD
to DAC V
. . . . . . . . . . . . –0.3 V to 6.5 V
DD
DD
Differential supply voltage range, all positive supply voltages to
ADC GND, DAC GND, DGTL GND, SUBS . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
Output voltage range, DOUT . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DGTL V
Input voltage range, DIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DGTL V
Ground voltage range, ADC GND, DAC GND,
+ 0.3 V
+ 0.3 V
DD
DD
DGTL GND, SUBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DGTL V
+ 0.3 V
DD
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
3.2 Recommended Operating Conditions (see Note 2)
MIN
NOM
MAX
5.5
UNIT
V
V
DD
Positive supply voltage
4.5
5
Steady-state differential voltage between any two supplies
High-level digital input voltage
0.1
V
V
V
2.2
V
IH
Low-level digital input voltage
0.8
V
IL
I
O
Load output current from ADC V
and DAC
MID
100
µA
Conversion time for the ADC and DAC channels
Master-clock frequency
10 FCLK periods
f
10.368
6
15
70
MHz
V
MCLK
V
Analog input voltage (differential, peak to peak)
ID(PP)
Differential output load resistance
600
R
Ω
L
Single-ended to buffered DAC V
Operating free-air temperature
voltage load resistance
300
0
MID
T
°C
A
NOTES: 1. VoltagevaluesforDGTLV
arewithrespecttoDGTLGND, voltagevaluesforDACV
arewithrespect
arewithrespecttoADCGND. Forthesubsequentelectrical,
DD
toDACGND, andvoltagevaluesforADCV
DD
DD
operating, and timing specifications, the symbol V
DGTL GND, and SUBS are at 0 V unless otherwise specified.
denotes all positive supplies. DAC GND, ADC GND,
DD
2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence
below should be followed when applying power:
(1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground.
(2) Connect voltages ADC V ,and DAC V
.
DD DD
(3) Connect voltage DGTL V
DD
.
(4) Connect the input signals.
When removing power, follow the steps above in reverse order.
3–1
3.3 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, MCLK = 5.184 MHz, V
Unloaded, Total Device
= 5 V, Outputs
DD
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
PWR DWN = 1 and clock signals
present
20
1
22
mA
Supply
current
I
DD
PWR DWN = 0 after 500 µs and
clock signals present
2
mA
mW
mW
mW
V
PWR DWN = 1 and clock signals
present
100
5
Power
PWR DWN = 0 after 500 µs and
dissipation clock signals present
P
D
Software power down, (bit D00,
register 6 set to 1)
15
20
Midpoint
voltage
ADC V /2
DD
ADC V /2
DD
ADC V
DAC V
No load
No load
MID
MID
–0.1
+0.1
Midpoint
voltage
DAC V /2
DD
DAC V /2
DD
V
–0.1
+0.1
3.4 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, V = 5 V, Digital I/O Terminals (DIN, DOUT, EOC,
DD
FC0, FC1, FS, FSD, MCLK, M/S, SCLK)
†
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
I
I
= –1.6 mA
= 1.6 mA
2.4
OH
OH
0.4
10
10
V
OL
OL
I
I
High-level input current, any digital input V = 2.2 V to DGTL V
DD
µA
µA
pF
pF
IH
I
Low-level input current, any digital input
Input capacitance
V = 0 V to 0.8 V
I
IL
C
C
5
5
i
Output capacitance
o
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
3.5 Electrical Characteristics Over Recommended Range of Operating
Free-Air Temperature, V = 5 V, ADC and DAC Channels
DD
ADC Channel Filter Transfer Function, FCLK = 144 kHz, f = 8 kHz
3.5.1
s
PARAMETER
TEST CONDITIONS
MIN
MAX
–2
UNIT
f = 50 Hz
i
f = 200 Hz
–1.8
–0.15
–0.35
–1
–0.2
0.2
i
f = 300 Hz to 3 kHz
i
Gain relative to gain at f = 1020 Hz (see Note 3)
f = 3.3 kHz
i
0.03
–0.1
–14
–32
dB
i
f = 3.4 kHz
i
f = 4 kHz
i
f ≥ 4.6 kHz
i
NOTE 3: The differential analog input signals are sine waves at 6 V peak to peak. The reference gain is at 1020 Hz.
3–2
3.5.2
ADC Channel Input, V
Noted)
= 5 V, Input Amplifier Gain = 0 dB (Unless Otherwise
DD
†
PARAMETER
TEST CONDITIONS
Single-ended
MIN TYP
MAX
UNIT
V
3
6
V
I(PP)
Peak-to-peak input voltage (see Note 4)
Differential
V
ADC converter offset error
Band-pass filter selected
10
30
mV
Common-mode rejection ratio at IN+, IN–,
AUX IN+, AUX IN– (see Note 5)
CMRR
55
dB
kΩ
dB
Input resistance at IN+, IN–, AUX IN+,
AUX IN–
r
i
100
60
DS03, DS02 = 0 in
register 4
Squelch
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTES: 4. The differential range corresponds to the full-scale digital output.
5. Common-mode rejection ratio is the ratio of the ADC converter offset error with no signal and the ADC
converter offset error with a common-mode nonzero signal applied to either IN+ and IN– together or
AUX IN+ and AUX IN– together.
3.5.3
ADC Channel Signal-to-Distortion Ratio, V
Otherwise Noted)
= 5 V, f = 8 kHz (Unless
DD s
A
= 0 dB
A
= 6 dB
A = 12 dB
V
V
V
PARAMETER
TEST CONDITIONS
V = –6 dB to –1 dB
UNIT
MIN
64
59
56
50
44
38
32
26
MAX
MIN
—
MAX
MIN
—
MAX
I
V = –12 dB to –6 dB
I
64
59
56
50
44
38
32
—
V = –18 dB to –12 dB
I
64
59
56
50
44
38
ADC channel signal-to-
distortion ratio
(see Note 6)
V = –24 dB to –18 dB
I
dB
V = –30 dB to –24 dB
I
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
NOTE 6: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog-input signal.
3.5.4
DAC Channel Filter Transfer Function, FCLK = 144 kHz, f = 9.6 kHz, V
= 5 V
DD
s
PARAMETER
TEST CONDITIONS
f < 200 Hz
MIN
MAX
UNIT
0.15
0.2
i
f = 200 Hz
i
–0.5
–0.15
–0.35
–1
f = 300 Hz to 3 kHz
i
0.2
Gain relative to gain at f = 1020 Hz (see Note 7)
f = 3.3 kHz
i
0.03
–0.1
–14
–32
dB
i
f = 3.4 kHz
i
f = 4 kHz
i
f ≥ 4.6 kHz
i
NOTE 7: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak.
3–3
3.5.5
DAC Channel Signal-to-Distortion Ratio, V
Otherwise Noted)
= 5 V, f = 8 kHz (Unless
DD s
A
= 0 dB
A
= –6 dB
A = –12 dB
V
V
V
PARAMETER
TEST CONDITIONS
UNIT
MIN
64
59
56
50
44
38
32
26
MAX
MIN
—
MAX
MIN
—
MAX
V
V
V
V
V
V
V
V
= –6 dB to 0 dB
O
O
O
O
O
O
O
O
= –12 dB to –6 dB
= –18 dB to –12 dB
= –24 dB to –18 dB
= –30 dB to –24 dB
= –36 dB to –30 dB
= –42 dB to –36 dB
= –48 dB to –42 dB
64
59
56
50
44
38
32
—
64
59
56
50
44
38
DAC channel signal-to-
distortion ratio
(see Note 8)
dB
NOTE 8: The input signal, V , is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
I
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 Ω from OUT+ to OUT–.
3.5.6
System Distortion, V
Noted)
= 5 V, f = 8 kHz, FCLK = 144 kHz (Unless Otherwise
DD s
†
PARAMETER
TEST CONDITIONS
Single-ended input (see Note 9)
Differential input (see Note 9)
Single-ended input (see Note 9)
Differential input (see Note 9)
Single-ended output
MIN TYP
MAX
UNIT
82
82
77
77
Second harmonic
64
64
ADC channel
attenuation
Third harmonic and
higher harmonics
dB
82
(buffered DAC V
(see Note 10)
)
MID
Second harmonic
DAC channel
attenuation
Differential output (see Note 10)
64
64
82
77
77
Single-ended output
(see Note 10)
Third harmonic and
higher harmonics
Differential output (see Note 10)
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTES: 9. The input signal is a 1020-Hz sine wave for the ADC channel. Harmonic distortion is defined for an input
level of –1 dB.
10. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 Ω from OUT+ to OUT–. Harmonic distortion is specified for a signal input level
of 0 dB.
3–4
3.5.7
Noise, Low-Pass and Band-Pass Switched-Capacitor Filters Included,
= 5 V (Unless Otherwise Noted)
V
DD
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Inputs tied to ADC V
,
MID
ADC idle-channel noise
180
300
f = 8 kHz, FCLK = 144 kHz,
s
(see Note 11)
µVrms
Broad-band noise
Noise (0 to 7.2 kHz)
Noise (0 to 3.6 kHz)
180
180
180
300
300
300
DIN INPUT = 00000000000000,
f = 8 kHz, FCLK = 144 kHz,
s
(see Note 12)
DAC idle-channel
noise
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTES: 11. The ADC channel noise is calculated by taking the RMS value of the digital output codes of the ADC
channel and converting to microvolts.
12. The DAC channel noise is measured differentially from OUT+ to OUT– across 600 Ω.
3.5.8
Absolute Gain Error, V
= 5 V, f = 8 kHz (Unless Otherwise Noted)
DD s
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ADC channel absolute gain error (see Note 13)
–1-dB input signal
0-dB input signal,
T
= –40 – 85°C
±1
A
dB
DAC channel absolute gain error (see Note 14)
T
A
= –40 – 85°C
±1
R
= 600 Ω
L
NOTES: 13. ADC absolute gain error is the variation in gain from the ideal gain over the specified input signal levels.
Thegain is measured with a –1-dB, 1020-Hz sine wave. The –1-dB input signal allows for any positive gain
or offset error that may affect gain measurements at or close to 0-dB input signal levels.
14. The DAC input signal is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at digital full-
scaleinput=0dB). ThenominaldifferentialDACchanneloutputvoltagewiththisinputconditionis6Vpeak
to peak. The load impedance for the DAC output buffer is 600 Ω from OUT+ to OUT–.
3.5.9
Relative Gain and Dynamic Range, V
Noted)
= 5 V, f = 8 kHz (Unless Otherwise
DD s
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ADC channel relative gain tracking error
(see Note 15)
–48-dB to –1-dB input signal range
–48-dB to 0-dB input signal range
±0.2
dB
DAC channel relative gain tracking error
(see Note 16)
±0.2
R
= 600 Ω
L(diff)
NOTES: 15. ADC gain tracking is the ratio of the measured gain at one ADC channel input level to the gain measured
at any other input level. The ADC channel input is a –1-dB 1020-Hz sine wave input signal. A –1-dB input
signalallowsforanypositivegainoroffseterrorthatmayaffectgainmeasurementsatorcloseto0-dBADC
input signal levels.
16. DAC gain tracking is the ratio of the measured gain at one DAC channel digital input level to the gain
measured at any other input level. The DAC-channel input signal is the digital equivalent of a 1020-Hz sine
wave (digital full scale =0dB). ThenominaldifferentialDACchanneloutputvoltagewiththisinputcondition
is 6 V peak to peak. The load impedance for the DAC output buffer is 600 Ω from OUT+ to OUT–.
3–5
3.5.10 Power-Supply Rejection, V
= 5 V (Unless Otherwise Noted) (see Note 17)
DD
†
PARAMETER
TEST CONDITIONS MIN TYP
MAX
UNIT
f = 0 to 30 kHz
50
55
40
45
50
55
i
ADC V
DAC V
Supply-voltage rejection ratio, ADC channel
Supply-voltage rejection ratio, DAC channel
Supply-voltage rejection ratio, ADC channel
DD
DD
f = 30 to 50 kHz
i
f = 0 to 30 kHz
i
f = 30 to 50 kHz
i
f = 0 to 30 kHz
i
DGTL V
DD
f = 30 to 50 kHz
i
dB
Single ended,
f = 0 to 30 kHz
i
40
45
40
45
f = 30 to 50 kHz
i
DGTL V
Supply-voltage rejection ratio, DAC channel
DD
Differential,
f = 0 to 30 kHz
i
f = 30 to 50 kHz
i
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTE 17: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.
3.5.11 Crosstalk Attenuation, V
= 5 V (Unless Otherwise Noted)
DD
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
DAC channel idle with
DIN = 00000000000000,
ADC input = 0 dB,
1020-Hz sine wave,
Gain = 0 dB (see Note 18)
ADC channel crosstalk attenuation
DAC channel crosstalk attenuation
80
dB
ADC channel idle with INP, INM,
AUX IN+, and AUX IN– at ADC V
80
80
MID
dB
DAC channel input = digital equivalent
of a 1020-Hz sine wave (see Note 19)
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTES: 18. The test signal is a 1020-Hz sine wave with a 0 dB = 6-V peak-to-peak reference level for the analog input
signal.
19. The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the
DAC output buffer is 600 Ω from OUT+ to OUT–.
3–6
3.5.12 Monitor Output Characteristics, V
(see Note 20)
= 5 V (Unless Otherwise Noted)
DD
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Peak-to-peak ac output
voltage
Quiescent level = ADC V
MID
V
V
V
1.3
1.5
5
V
O(PP)
Z
L
= 10 kΩ and 60 pF
No load, single ended
relative to ADC V
Output offset voltage
10
mV
OO
MID
0.4 ADC 0.5 ADC 0.6 ADC
Output common-mode voltage No load
DC output resistance
V
OC
V
DD
V
DD
50
V
DD
r
o
Ω
Gain = 0 dB
–0.2
–8.2
0
0.2
–7.8
Gain 2 = –8 dB
Gain 3 = –18 dB
–8
A
Voltage gain (see Note 21)
dB
V
–18.4
–18
–17.6
–60
Squelch (see Note 22)
= 5 V and T = 25°C.
†
All typical values are at V
DD
A
NOTES: 20. All monitor output tests are performed with a 10-kΩ load resistance.
21. Monitor gains are measured with a 1020-Hz, 6-V peak-to-peak sine wave applied differentially between
IN+ and IN–.The monitor output gains are nominally 0 dB, –8 dB, and –18 dB relative to its input; however,
the output gains are –6 dB relative to IN+ and IN– or AUX IN+ and AUX IN–.
22. Squelch is measured differentially with respect to ADC V
.
MID
3–7
3.6 Timing Requirements and Specifications in Master Mode
3.6.1
Recommended Input Timing Requirements for Master Mode, V
= 5 V
DD
MIN
NOM
MAX
UNIT
ns
t
t
Master clock rise time
5
5
r(MCLK)
Master clock fall time
ns
f(MCLK)
Master clock duty cycle
40%
1 MCLK
25
60%
t
t
t
RESET pulse duration
w(RESET)
su(DIN)
h(DIN)
DIN setup time before SCLK low (see Figure 4–2)
DIN hold time after SCLK low (see Figure 4–2)
ns
ns
20
3.6.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V = 5 V (Unless Otherwise Noted) (see Note 23)
DD
†
PARAMETER
MIN TYP
MAX
18
UNIT
ns
t
t
Shift clock fall time (see Figure 4–2)
Shift clock rise time (see Figure 4–2)
Shift clock duty cycle
13
13
f(SCLK)
18
ns
r(SCLK)
45%
55%
Delay time from SCLK high to FSD low
(see Figures 4–2 and 4–4 and Note 24)
t
t
t
5
5
20
20
20
ns
ns
ns
d(CH-FL)
Delay time from SCLK high to FS high (see Figure 4–2)
d(CH-FH)
Delay time from SCLK high to DOUT valid
(see Figures 4–2 and 4–7)
d(CH-DOUT)
Delay time from SCLK↑ to DOUT in high-impedance state
(see Figure 4–8)
t
20
ns
d(CH-DOUTZ)
t
t
t
t
Delay time from MCLK low to EOC low (see Figure 4–9)
Delay time from MCLK low to EOC high (see Figure 4–9)
EOC fall time (see Figure 4–9)
40
40
13
13
ns
ns
ns
ns
d(ML-EL)
d(ML-EH)
f(EL)
EOC rise time (see Figure 4–9)
r(EH)
t
t
Delay time from MCLK high to SCLK high
Delay time from MCLK high to SCLK low
50
50
ns
ns
d(MH-CH)
d(MH-CL)
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTES: 23. All timing specifications are valid with C = 20 pF.
L
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
3–8
3.7 Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode
3.7.1
Recommended Input Timing Requirements for Slave Mode, V
= 5 V
DD
MIN
NOM
MAX
UNIT
ns
t
t
Master clock rise time
5
5
r(MCLK)
Master clock fall time
ns
f(MCLK)
Master clock duty cycle
40%
1 MCLK
20
60%
t
t
t
t
RESET pulse duration
w(RESET)
DIN setup time before SCLK low (see Figure 4–3)
DIN hold time after SCLK high (see Figure 4–3)
Setup time from FS low to SCLK high
ns
ns
ns
su(DIN)
20
±SCLK/4
h(DIN)
su(FL-CH)
3.7.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V = 5 V (Unless Otherwise Noted) (see Note 23)
DD
†
PARAMETER
MIN TYP
MAX
UNIT
ns
t
t
t
Shift clock cycle time (see Figure 4–3)
Shift clock fall time (see Figure 4–3)
Shift clock rise time (see Figure 4–3)
Shift clock duty cycle
125
c(SCLK)
f(SCLK)
r(SCLK)
18
18
ns
ns
45%
55%
50
t
t
Delay time from SCLK high to FSD low (see Figure 4–6)
Delay time from SCLK high to FSD high
ns
ns
d(CH-FDL)
40
d(CH-FDH)
Delay time from FS low to FSD low (slave to slave)
(see Figure 4–5)
t
t
t
40
40
ns
ns
ns
d(FL-FDL)
Delay time from SCLK high to DOUT valid
(see Figures 4–3 and 4–7)
d(CH-DOUT)
d(CH-DOUTZ)
Delay time from SCLK↑ to DOUT in high-impedance state
(see Figure 4–8)
20
t
t
t
t
t
t
Delay time from MCLK low to EOC low (see Figure 4–9)
Delay time from MCLK low to EOC high (see Figure 4–9)
EOC fall time (see Figure 4–9)
40
40
13
13
ns
ns
ns
ns
ns
ns
d(ML-EL)
d(ML-EH)
f(EL)
EOC rise time (see Figure 4–9)
r(EH)
Delay time from MCLK high to SCLK high
Delay time from MCLK high to SCLK low
50
50
d(MH-CH)
d(MH-CL)
†
All typical values are at V
= 5 V and T = 25°C.
A
DD
NOTE 23: All timing specifications are valid with C = 20 pF.
L
3–9
4
Parameter Measurement Information
R
fb
_
+
R
R
+
_
IN+ or AUX IN+
IN– or AUX IN–
To Multiplexer
R
fb
R
R
R
= R for DS03 = 0 and DS02 = 1
= 2R for DS03 = 1 and DS02 = 0
= 4R for DS03 = 1 and DS02 = 1
fb
fb
fb
R = 100 kΩ nominal
Figure 4–1. IN+ and IN– Gain-Control Circuitry
Table 4–1. Gain Control (Analog Input Signal Required for
†
Full-Scale Bipolar A/D-Conversion 2s Complement)
CONTROL REGISTER 4
A/D CONVERSION
RESULT
‡
INPUT CONFIGURATION
ANALOG INPUT
DS03
DS02
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
All
Squelch
±Full scale
±Full scale
±Full scale
Squelch
Differential configuration
Analog input = IN+ – IN–
= AUX IN+ – AUX IN–
V
V
V
= ±3 V
= ±1.5 V
= ±0.75 V
All
ID
ID
ID
§
Single-ended configuration
V = ±1.5 V
±Half scale
±Full scale
±Full scale
I
Analog input = IN+ – V
MID
= AUX IN+ – V
V = ±1.5 V
I
MID
V = ±0.75 V
I
†
‡
V
V
= 5 V
DD
ID
= differential input voltage, V = input voltage referenced to ADC V
with IN– or AUX IN– connected to
. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale.
I
MID
ADC V
MID
For single-ended inputs, the analog input voltage should not exceed the supply rails. All single-ended inputs should be
referenced to the internal reference voltage, ADC V , for best common-mode performance.
§
MID
4–1
t
f(SCLK)
t
r(SCLK)
2 V
2 V
2 V
SCLK
0.8 V
t
t
d(CH-FH)
d(CH-FL)
2 V
†
‡
FS
0.8 V
t
d(CH-DOUT)
D15
D15
D14
D13
D13
D12
D11
D2
D2
D1
D1
D0
DOUT
t
su(DIN)
DIN
D14
D12
D11
D0
t
h(DIN)
†
‡
The time between falling edges of two primary FS signals is the conversion period.
The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
Figure 4–2. AIC Stand-Alone and Master-Mode Timing
t
f(SCLK)
t
t
c(SCLK)
r(SCLK)
2 V
2 V
2 V
2 V
SCLK
0.8 V
§
†
‡
FS
t
d(CH-DOUT)
D15
D15
D14
D13
D13
D12
D11
D2
D1
D0
D0
DOUT
t
su(DIN)
DIN
D14
D12
D11
D2
D1
t
h(DIN)
†
‡
The time between falling edges of two primary FS signals is the conversion period.
The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling
edge of the shift clock.
§
The high-to-low transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock
for the codec mode.
Figure 4–3. AIC Slave and Codec Emulation Mode
4–2
2.4 V
SCLK
FSD
SCLK Period/2
0.8 V
t
d(CH-FL)
FS
0.8 V
NOTE A: Timing shown is for the TLC320AC02 operating as the master or as a stand-alone device.
Figure 4–4. Master or Stand-Alone FS and FSD Timing
FS
0.8 V
t
d(FL-FDL)
FSD
0.8 V
NOTE A: Timing shown is for the TLC320AC02 operating in the slave mode (FS and SCLK signals are generated
externally). The programmed data value in the FSD register is 0.
Figure 4–5. Slave FS to FSD Timing
2.4 V
SCLK
0.8 V
t
d(CH-FDL)
FSD
0.8 V
NOTE A: Timing shown is for the TLC320AC02 operating in the slave mode (FS and SCLK signals are generated
externally). There is a data value in the FSD register greater than 18 (decimal).
Figure 4 – 6. Slave SCLK to FSD Timing
4–3
2 V
SCLK
DOUT
0.8 V
t
d(CH-DOUT)
Hi-Z
2.4 V
0.4 V
2.4 V
0.4 V
Figure 4–7. DOUT Enable Timing From Hi-Z
2 V
SCLK
0.8 V
t
d(CH-DOUTZ)
Hi-Z
0.8 V
DOUT
Figure 4–8. DOUT Delay Timing to Hi-Z
t
d(ML-EH)
2 V
2 V
0.8 V
MCLK
EOC
0.8 V
t
t
r(EH)
d(ML-EL)
2.4 V
2.4 V
0.4 V
0.4 V
t
f(EL)
Internal ADC
Conversion Time
Figure 4–9. EOC Frame Timing
4–4
†
Delay Is m Shift Clocks
Master
FS
†
Delay Is m Shift Clocks
Master FSD,
Slave Device 1 FS
†
Delay Is m Shift Clocks
Slave Device 1 FSD,
Slave Device 2 FS
Slave Device 2 FSD,
Slave Device 3 FS
Slave Device
(n – 1) FSD,
Slave Device n FS
†
The delay time from any FS signals to the corresponding FSD signals is m shift clocks with the value of m being the
numerical value of the data programmed into the FSD register. In the master mode with slaves, the same data word
programs the master and all slave devices; therefore, master to slave 1, slave 1 to slave 2, slave 2 to slave 3, etc., have
the same delay time.
Figure 4–10. Master-Slave Frame-Sync Timing After a Delay Has Been
Programmed Into the FSD Registers
t = 0
t = 1
t = 2
Sampling
Period
Master AIC
Only Primary
Frame Sync
FS
FS
MP
MP
MP
1/2 Period
Master AIC
Only Primary
and Secondary
Frame Sync
MP
MS
MP
MS
MP
FSD
Value
Master and Slave
AIC Primary
Frame Sync
FS
MP
MP
SP
SP
MP
MP
SP
SP
MP
MP
SP
SP
Master and Slave
AIC Primary and
Secondary
FS
MS
SS
MS
SS
MS
SS
Frame Sync
MP = Master Primary
MS = Master Secondary
SP = Slave Primary
SS = Slave Secondary
Figure 4–11. Master and Slave Frame-Sync Sequence with One Slave
4–5
5
Typical Characteristics
ADC LOW-PASS RESPONSE
0
–10
–20
T
= 25°C
A
FCLK = 144 kHz
–30
–40
–50
–60
0
1
2
3
4
5
6
7
8
9
10
f – Input Frequency – kHz
i
Normalized Frequency
144
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–1
5–1
ADC LOW-PASS RESPONSE
0.5
0.4
0.3
0.2
T
= 25°C
A
FCLK = 144 kHz
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
f – Input Frequency – kHz
i
Normalized Frequency
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
144
Figure 5–2
5–2
ADC GROUP DELAY
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
T
= 25°C
A
FCLK = 144 kHz
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
f – Input Frequency – kHz
i
Normalized Frequency
144
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–3
5–3
ADC BAND-PASS RESPONSE
0
–10
–20
T
= 25°C
= 8 kHz
A
f
s
FCLK = 144 kHz
–30
–40
–50
–60
0
1
2
3
4
5
6
7
8
f – Input Frequency – kHz
i
Normalized Frequency
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
144
Figure 5–4
5–4
ADC BAND-PASS RESPONSE
0.5
0.4
T
= 25°C
= 8 kHz
A
f
s
FCLK = 144 kHz
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
f – Input Frequency – kHz
i
Normalized Frequency
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
144
Figure 5–5
5–5
ADC HIGH-PASS RESPONSE
–0
–5
–10
–15
–20
–25
–30
T
= 25°C
= 8 kHz
A
f
s
FCLK = 144 kHz
150 200
f – Input Frequency – kHz
0
50
100
250
i
Normalized Frequency
144
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–6
5–6
ADC BAND-PASS GROUP DELAY
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
T
= 25°C
= 8 kHz
A
f
s
FCLK = 144 kHz
0.2
0.1
0
7
0
1
2
3
4
5
6
8
f – Input Frequency – kHz
i
Normalized Frequency
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
144
Figure 5–7
5–7
DAC LOW-PASS RESPONSE
0
–10
–20
T
= 25°C
= 9.6 kHz
A
f
s
FCLK = 144 kHz
–30
–40
–50
–60
0
1
2
3
4
5
6
7
8
9
10
f – Input Frequency – kHz
i
Normalized Frequency
144
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–8
5–8
DAC LOW-PASS RESPONSE
0.5
0.4
0.3
0.2
T
= 25°C
= 9.6 kHz
A
f
s
FCLK = 144 kHz
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
f – Input Frequency – kHz
i
Normalized Frequency
144
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–9
5–9
DAC LOW-PASS GROUP DELAY
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
T
= 25°C
= 9.6 kHz
A
f
s
FCLK = 144 kHz
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
f – Input Frequency – kHz
i
Normalized Frequency
144
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–10
5–10
DAC (sin x)/x CORRECTION FILTER RESPONSE
4
2
0
– 2
– 4
– 6
T
= 25°C
A
Input = ± 3-V Sine Wave
0
2
4
6
8
10 12 14 16 18 20
Normalized Frequency
Normalized Frequency
288
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–11
5–11
DAC (sin x)/x CORRECTION FILTER RESPONSE
500
T
A
= 25°C
Input = ± 3-V Sine Wave
400
300
200
100
0
0
2
4
6
8
10 12 14 16 18 20
Normalized Frequency
Normalized Frequency
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
288
Figure 5–12
5–12
DAC (sin x)/x CORRECTION ERROR
2
1.6
T
= 25°C
A
Input = ± 3-V Sine Wave
1.2
(sin x) /x Correction
Error
0.8
0.4
0
– 0.4
– 0.8
19.2-kHz (sin x) /x
Distortion
–1.2
–1.6
– 2
0
1
2
3
4
5
6
7
8
9
10
Normalized Frequency
Normalized Frequency
288
FCLK (kHz)
NOTE A : Absolute Frequency (kHz)
Figure 5–13
5–13
6
Application Information
TMS320C2x/3x
TLC320AC02
DAC V
5
6
5 V
0.1 µF
DD
14
CLKOUT
MCLK
DIN
DAC V
MID
10
0.1 µF
0.1 µF
DX
7
DAC GND
11
DR
DOUT
FS
24
23
5 V
0.1 µF
ADC V
DD
12
FSX
ADC V
MID
FSR
22
9
13
ADC GND
DGTL V
CLKX
SCLK
5 V
0.1 µF
CLKR
DD
DGTL GND
20
D
A
GND
GND
NOTE A: Terminal numbers shown are for the FN package.
Figure 6–1. Stand-Alone Mode (to DSP Interface)
TMS320C2x/3x
TLC320AC02
14
10
CLKOUT
MCLK
DX
DR
DIN
11
12
DOUT
FS
FSX
FSR
13
CLKX
CLKR
SCLK
NOTE A: Terminal numbers shown are for the FN package.
Figure 6–2. Codec Mode (to DSP Interface)
6–1
TMS320C2x/3x
TLC320AC02
14
10
CLKOUT
MCLK
DX
DR
DIN
11
12
DOUT
FS
Master Mode
FSX
FSR
FSD
SCLK
13
CLKX
CLKR
TLC320AC02
14
10
MCLK
DIN
11
12
DOUT
FS
FSD
13
Slave Mode
SCLK
NOTE A: Terminal numbers shown are for the FN package.
Figure 6–3. Master With Slave (to DSP Interface)
10 kΩ
10 kΩ
+
–
IN+
†
V
–
I
+
TLE2022
10 kΩ
10 kΩ
–
+
IN–
ADC V
MID
TLE2022
†
The V source must be capable of sinking a current equal to [ADC V
+ |V |(max)]/10 kΩ.
I
I
MID
Figure 6–4. Single-Ended Input (Ground Referenced)
6–2
IN+
10 kΩ
10 kΩ
10 kΩ
†
V
I
10 kΩ
–
+
–
+
IN–
TLE2064
TLE2064
4
4
10 kΩ
–
+
ADC V
MID
TLE2064
4
10 kΩ
†
The V source must be capable of sinking a current equal to [(ADC V
/2) + |V |(max)]/10 kΩ.
I
I
MID
Figure 6–5. Single-Ended to Differential Input (Ground Referenced)
OUT–
600-Ω
Load
OUT+
Figure 6–6. Differential Load
10 kΩ
5 V
10 kΩ
–
+
OUT–
OUT+
600-Ω
Load
TLE2062
10 kΩ
– 5 V
10 kΩ
NOTE A: When a signal changes from a single supply with a nonzero reference system to a
grounded load, the operational amplifier must be powered from plus and minus supplies
or the load must be capacitively coupled.
Figure 6–7. Differential Output Drive (Ground Referenced)
6–3
–
+
OUT+
OUT–
TLE2062
TLE2062
600-Ω
Load
–
+
Figure 6–8. Low-Impedance Output Drive
100 kΩ
5 V
100 kΩ
600-Ω
Load
–
+
OUT+
DAC V
MID
TLE2062
– 5 V
100 kΩ
100 kΩ
NOTE A: When a signal changes from a single supply with a nonzero reference system to a
grounded load, the operational amplifier must be powered from plus and minus supplies
or the load must be capacitively coupled.
Figure 6–9. Single-Ended Output Drive (Ground Referenced)
6–4
Appendix A
Primary Control Bits
The function of the primary-word control bits D01 and D00 and the hardware terminals FC0 and FC1 are
shown below. Any combinational state of D01, D00, FC1, and FC0 not shown is ignored.
CONTROL FUNCTION OF CONTROL BITS
BITS
TERMINALS
D01
D00
FC1
FC0
0
0
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
0
0
0
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of the next internal FS, the next ADC/DAC sampling time occurs later
by the number of MCLK periods equal to the value contained in the A′ register. When
the A′ register value is negative, the internal falling edge of FS occurs earlier.
0
0
1
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
rising edge of the next internal FS, the next ADC/DAC sample time occurs earlier by
the number of MCLK periods determined by the value contained in the A′ register.
When the A′ register value is negative, the internal falling edge of FS occurs later.
0
0
0
1
1
0
1
0
On the next falling edge of the primary FS, the AIC receives DAC data D15–D02 at
DIN and transmits the ADC data D15–D00 from DOUT.
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, the falling edge of FS occurs earlier.
1
1
0
1
0
0
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A′ register. When the A′ register
value is negative, the internal falling edge of FS occurs later.
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
When D00 and D01 are both high, the AIC initiates a secondary FS to receive a
secondary control word at DIN. The secondary frame sync occurs at 1/2 the sampling
time as measured from the falling edge of the primary FS.
A–1
CONTROL FUNCTION OF CONTROL BITS (Continued)
BITS
TERMINALS
D01
0
D00
FC1
FC0
1
1
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
1
0
1
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sample time occurs earlier by the number of MCLK
periods determined by the value contained in the A′ register. When the A′ register
value is negative, FS occurs later.
When FC0 and FC1 are both taken high, the AIC initiates a secondary FS to receive
a secondary control word at DIN. The secondary frame sync occurs at 1/2 the
sampling time as measured from the falling edge of the primary FS.
1
1
1
1
1
0
1
1
On the next falling edge of the primary FS, the AIC receives DAC data D15–D02 at
DIN and transmits the ADC data D15–D00 from DOUT.
When FC1 and FC0 are both high or D01 and D00 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
When D00 and D01 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
1
1
1
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 to DIN and
transmits the ADC data D15–D00 from DOUT.
When D00 and D01 are high, the AIC initiates a secondary FS to receive a secondary
control word at DIN. The secondary frame sync occurs at 1/2 the sampling time as
measured from the falling edge of the primary FS.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
1
1
1
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
When FC1 and FC0 are both high or D01 and D00 are both high, the AIC initiates a
secondary FS to receive a secondary control word at DIN. The secondary FS occurs
at 1/2 the sampling time measured from the falling edge of the primary FS.
A–2
Appendix B
Secondary Communications
The function of the control bits DS15 and DS14 and the hardware terminals FC0 and FC1 are shown below.
Any combinational state of DS15, DS14, FC1, and FC0 not shown is ignored.
CONTROL FUNCTION OF SECONDARY COMMUNICATION
BITS
TERMINALS
FC1 FC0
Ignored
DS15 DS14
0
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
0
1
Ignored
Ignored
On the next falling edge of the FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of DS15 and DS14 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
1
0
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A′ register. When the A′ register
value is negative, FS occurs later.
1
1
1
1
0
0
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
0
1
1
On the next falling edge of the FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
1
1
1
1
0
1
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
nextrisingedgeofFS, thenextADC/DACsamplingtimeoccursearlierbythenumber
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs later.
On the next falling edge of FS, the AIC receives DAC data D15–D02 at DIN and
transmits the ADC data D15–D00 from DOUT.
B–1
Appendix C
TLC320AC01C/TLC320AC02C Specification Comparisons
Texas Instruments manufactures the TLC320AC01C and the TLC320AC02C specified for the 0°C to 70°C
commercial temperature range and the TLC320AC02I specified for the –40°C to 85°C temperature range.
The TLC320AC02C and TLC320AC02I operate at a relaxed TLC320AC01C specification. The differences
are listed in the following tables.
ADC Channel Signal-to-Distortion Ratio, V
Otherwise Noted) (see Note 1)
= 5 V, f = 8 kHz (Unless
s
DD
A
= 0 dB
A
= 6 dB
A = 12 dB
V
V
V
PARAMETER
TEST CONDITIONS
UNIT
MIN
68
64
63
59
57
56
51
50
45
44
39
38
33
32
27
26
MAX
MIN
—
MAX
MIN
—
MAX
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
V = –6 dB to –1 dB
I
—
—
68
64
63
59
57
56
51
50
45
44
39
38
33
32
—
V = –12 dB to –6 dB
I
—
68
64
63
59
57
56
51
50
45
44
39
38
V = –18 dB to –12 dB
I
V = –24 dB to –18 dB
I
dB
V = –30 dB to –24 dB
I
V = –36 dB to –30 dB
I
V = –42 dB to –36 dB
I
V = –48 dB to –42 dB
I
NOTE 1: The analog-input test signal is a 1020-Hz sine wave with 0 dB = 6 V peak to peak as the reference level for
the analog input signal.
C–1
DAC Channel Signal-to-Distortion Ratio, V
Otherwise Noted) (see Note 2)
= 5 V, f = 8 kHz (Unless
s
DD
A
= 0 dB
A
= –6 dB
A = –12 dB
V
V
V
PARAMETER
TEST CONDITIONS
UNIT
MIN
68
64
63
59
57
56
51
50
45
44
39
38
33
32
27
26
MAX
MIN
—
MAX
MIN
—
MAX
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
V
O
V
O
V
O
V
O
V
O
V
O
V
O
V
O
= –6 dB to 0 dB
—
—
68
64
63
59
57
56
51
50
45
44
39
38
33
32
—
= –12 dB to –6 dB
= –18 dB to –12 dB
= –24 dB to –18 dB
= –30 dB to –24 dB
= –36 dB to –30 dB
= –42 dB to –36 dB
= –48 dB to –42 dB
—
68
64
63
59
57
56
51
50
45
44
39
38
dB
NOTE 2: The input signal, V , is the digital equivalent of a 1020-Hz sine wave (full-scale analog output at full-scale digital
I
input = 0 dB). The nominal differential DAC channel output with this input condition is 6 V peak to peak. The
load impedance for the DAC output buffer is 600 Ω from OUT+ to OUT–.
C–2
System Distortion, ADC Channel Attenuation, V
FCLK = 144 kHz (Unless Otherwise Noted)
= 5 V, f = 8 kHz,
s
DD
PARAMETER
TEST CONDITIONS
MIN
70
MAX
UNIT
dB
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
Second harmonic
64
dB
Differential input
(see Note 3)
70
dB
Third harmonic and higher harmonics
64
dB
NOTE 3: The input signal is a 1020 Hz-sine wave for the ADC channel. Harmonic distortion is defined for an input level
of –1 dB.
System Distortion, DAC Channel Attenuation, V
FCLK = 144 kHz (Unless Otherwise Noted)
= 5 V, f = 8 kHz,
s
DD
PARAMETER
TEST CONDITIONS
MIN
70
MAX
UNIT
dB
TLC320AC01
TLC320AC02
TLC320AC01
TLC320AC02
Second harmonic
64
dB
Differential output
(see Note 4)
70
dB
Third harmonic and higher harmonics
64
dB
NOTE 4: The input signal is the digital equivalent of a 1020-Hz sine wave (digital full scale = 0 dB). The nominal
differential DAC channel output with this input condition is 6 V peak to peak. The load impedance for the DAC
output buffer is 600 Ω from OUT+ to OUT–. Harmonic distortion is specified for a signal input level of 0 dB.
C–3
Appendix D
Multiple TLC320AC01/02 Analog Interface Circuits on One
TMS320C5X DSP Serial Port
In many applications, digital signal processors (DSP) must obtain information from multiple analog-to-digital
(A/D) channels and transmit digital data to multiple digital-to-analog (D/A) conversion channels. The
problem is how to do it easily and efficiently.
This application report addresses the issue of connecting two channels of an analog interface circuit (AIC)
to one TMS320C5X DSP serial port. In this application report, the AIC is the TLC320AC02.
The TLC320AC02 (and TLC320AC01) analog interface circuit contains both A/D and D/A converters and
using the master/slave mode, it is possible to connect two of them to one TMS320C5X DSP serial port with
no additional logic. The hardware schematic is shown in Figure D–1.
D–1
TMS320C5x
TLC320AC02
14
10
CLKOUT
MCLK
DX
DR
DIN
11
12
DOUT
FS
Master Mode
FSX
FSR
FSD
SCLK
13
CLKX
CLKR
TLC320AC02
14
10
MCLK
DIN
11
12
DOUT
FS
FSD
13
Slave Mode
SCLK
NOTE A: Terminal numbers shown are for the FN package.
Figure D–1. Master With Slave (to DSP Interface)
HARDWARE AND SOFTWARE SOLUTION
Once the hardware connections are completed, the issue becomes distinguishing one channel from
another. Fortunately, this is very easy to do in software and adds very little overhead. The mode that the
AC02s run in is called master/slave mode. One AC02 is the master and all of the rest of the AC02s are
slaves. The master can be distinguished from all of the slaves by examining the least significant bit (LSB)
in the receive word coming from the AC02. The master has a 0 in the LSB and all of the slaves have a 1
in the LSB.
The AC02s in master/slave mode take turns communicating with the DSP serial port. They do this is a round
robin or circular fashion. Synchronizing the system involves looking for the master AC02 and then starting
the software associated with the first AC02. All other AC02s follow in order. It is possible to have different
software for each AC02.
A reference design was constructed using a TMS320C5X DSP starter kit (DSK). The AC02s were
connected to the TDM serial port which is available at the headers on the edge of the DSK.
A listing of the DSK assembly code for a simple stereo input/output program is included in the following
section.
D–2
SOFTWARE MODULE
*****************************************************************************
MODULE NAME: INOUTB.ASM
In-out routine for C5X DSK with two TLC320AC02s on the
TDM serial port of the C5X in master/slave mode.
This version performs the in/out task for both the master
and slave TLC320AC02 in the receive interrupt service
routine.
*****************************************************************************
*
.mmregs
.ds
01000h
0104h
0219h
0300h
0405h
0501h
0600h
0730h
0802h
0800h
0800h
0200h
0400h
PR1
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
.word
;A register
PR2
;B register
PR3
;A prime register
PR4
;amplifier gain register
;analog configuration register
;digital configuration register
;frame synch delay register
;frame synch number register
PR5
PR6
PR7
PR8
value
value2
val_add
val_add2
*****************************************************************************
Set up the ISR vector
*****************************************************************************
.ps
080ah
rint:
xint:
trint:
txint:
B
RECEIVE
TRANSMIT
TDMREC
TDMTX
; 0A; Serial port receive interrupt RINT.
; 0C; Serial port transmit interrupt XINT.
B
B
B
;
******************************************************************************
TMS320C5X INITIALIZATION
*****************************************************************************
.ps 0a00h
.entry
START:
SETC
LDP
INTM
; Disable interrupts
#0
; Set data page pointer
OPL
#0834h,PMST
#0
LACC
SAMM
SAMM
CWSR
PDWSR
D–3
splk
SPLK
call
#00c8h
082h,IMR
AC02INIT
CLRC
SPM
OVM
; OVM = 0
0
; PM = 0
SPLK
SPLK
CLRC
#042h,IMR
#0C8h,TSPC
INTM
; TDMA ser port rec interrupt
;
; enable interrupts
loop
; main program here does nothing.
nop
b
; a user program can be inserted.
;
loop
;
;
end of main program
;
; TDM serial port receiver interrupt service routine
;
TDMREC:
; This loop insures that the master AC02
; is the first one that is written to in the
; loop. the slave AC02(s) will follow in
; sequential order. The master AC02 has a
; 0 in the 1sb. the slave AC02(s) have a 1
; in the 1sb of the receive word.
ldp
#trcv
bit
trcv,15
xxx,tc
bcnd
ldp
#trcv
trcv
lacc
and
#0fffch
;
; user code would go here for master AC02
;
sacl
b
tdxr
yyy
xxx
ldp
#trcv
trcv
lacc
and
#0fffch
;
; user code would go here for slave AC02
;
sacl
rete
tdxr
yyy
D–4
;
; TDM serial port transmit interrupt service routine
;
TDMTX:
rete
;
; RECEIVER INTERRUPT SERVICE ROUTINE
;
RECEIVE:
rete
TRANSMIT:
RETE
D–5
AC02INIT
SPLK
SPLK
MAR
#020h,TCR
#01h,PRD
*,AR0
LACC
SACL
LACC
SACL
SETC
#0008h
TSPC
#00c8h
TSPC
SXM
;
;
;
;
LDP
#PR1
LACC
CALL
PR1
AC02_2ND
LDP
#PR2
LACC
CALL
PR2
AC02_2ND
LDP
#PR8
LACC
CALL
PR8
AC02_2ND
LDP
#PR7
LACC
CALL
PR7
AC02_2ND
ret
AC02_2ND:
LDP
#0
SACH
CLRC
IDLE
ADD
TDXR
INTM
;
#6h, 15
TDXR
; 0000 0000 0000 0011 XXXX XXXX XXXX XXXX b
;
SACH
IDLE
SACL
IDLE
LACL
SACL
IDLE
SETC
RET
TDXR
;
#0
;
TDXR
; make sure the word got sent
INTM
;
D–6
Appendix E
Mechanical Data
PLASTIC J-LEADED CHIP CARRIER
FN/S-PQCC-J**
20-PIN SHOWN
D
0.180 (4,57) MAX
0.120 (3,05) MAX
D
1
0.048 (1,22)
× 45°
0.020 (0,51) MIN
0.042 (1,07)
3
1
19
4
8
18
14
D /E
3
3
E
E
1
D /E
2
2
9
13
0.050 (1,27) TYP
D /E
D/E
D /E
D /E
3 3
1
1
2
2
JEDEC
OUTLINE
NO. OF
PINS**
MIN
MAX
MIN
MAX
MIN
MAX
TYP
0.385
(9,78)
0.395
(10,03)
0.350
(8,89)
0.356
(9,04)
0.290
(7,34)
0.330
(8,38)
0.200
(5,08)
MO-047AA
MO-047AB
MO-047AC
MO-047AD
MO-047AE
MO-047AF
20
28
44
52
68
84
0.485
(12,32)
0.495
(12,57)
0.450
(11,43)
0.456
(11,58)
0.390
(9,91)
0.430
(10,92)
0.300
(7,62)
0.685
(17,40)
0.695
(17,65)
0.650
(16,51)
0.656
(16,66)
0.590
(14,99)
0.630
(16,00)
0.500
(12,70)
0.785
(19,94)
0.795
(20,19)
0.750
(19,05)
0.756
(19,20)
0.690
(17,53)
0.730
(18,54)
0.600
(15,24)
0.985
(25,02)
0.995
(25,27)
0.950
(24,13)
0.956
(24,28)
0.890
(22,61)
0.930
(23,62)
0.800
(20,32)
1.185
(30,10)
1.195
(30,35)
1.150
(29,21)
1.158
(29,41)
1.090
(27,69)
1.130
(28,70)
1.000
(25,40)
4040005/A–07/93
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Dimensions D and E do not include mold flash or protrusion. Protrusion shall not exceed 0.010 (0,25)
1
1
on any side.
D. All dimensions conform to JEDEC Specification MO-047.
E. Maximum deviation from coplanarity is 0.004 (0,10).
E–1
PM/S-PQFP-G64
PLASTIC QUAD FLAT PACKAGE
0,26
0,14
0,50 TYP
48
33
32
49
Pin # 1
Indicator
64
17
0,177
0,147
1
16
1,50
1,30
7,50 SQ TYP
10,10
SQ
9,90
12,20
SQ
11,80
1,70 MAX
0,00 MIN
Seating Plane
0°–10°
0,70
0,30
4040152/A–07/93
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Maximum deviation from coplanarity is 0,08 mm.
D. Body dimensions do not include mold flash or protrusion.
E–2
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