TLC320AD545_技术文档

Data Manual

1999

Mixed Signal Products

SLAS206B

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

2

Contents

Section

Title

Page

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1

1.2

1.3

1.4

1.5

1.6

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Analog Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

2

3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.1

2.2

2.3

2.4

Device Requirements and System Overview . . . . . . . . . . . . . . . . . . . . 2–1

Codec Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Hybrid Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Miscellaneous Logic and Other Circuitry . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Codec Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Operating Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Analog and Digital Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Software Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.10 Test Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.11 Power Supply Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

4

5

4.1

4.2

4.3

4.4

4.5

Primary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

FS Low Mode Primary Communication Timing . . . . . . . . . . . . . . . . . . 4–2

Secondary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

FS High Mode Secondary Communication Timing . . . . . . . . . . . . . . . 4–4

FS Low Mode Secondary Communication Timing . . . . . . . . . . . . . . . . 4–4

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.1

Absolute Maximum Ratings Over Operating Free-Air

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

5.2

5.3

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Electrical Characteristics Over Recommended Operating Free-Air

Temperature Range DV

= 5 V/3.3 V, AV

= 5 V/3.3 V,

DD

MV

= 5 V/3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

DD

5.3.1

Digital Inputs and Outputs, f = 8 kHz,

s

Outputs Not Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

iii

5.3.2

5.3.3

ADC Channel, f = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

s

ADC Dynamic Performance, f = 8 kHz . . . . . . . . . . . . . . . . 5–2

s

5.3.3.1

5.3.3.2

5.3.3.3

ADC Signal-to-Noise . . . . . . . . . . . . . . . . . . . . . 5–2

ADC Signal-to-Distortion . . . . . . . . . . . . . . . . . . 5–2

ADC Signal-to-Distortion + Noise . . . . . . . . . . 5–3

5.3.4

5.3.5

5.3.6

ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

DAC Channel, f = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

s

DAC Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

5.3.6.1

5.3.6.2

5.3.6.3

DAC Signal-to-Noise . . . . . . . . . . . . . . . . . . . . . 5–3

DAC Signal-to-Distortion . . . . . . . . . . . . . . . . . . 5–3

DAC Signal-to-Distortion + Noise . . . . . . . . . . 5–4

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Logic DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 5–4

Power-Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Power-Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4

Flash Write Enable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.4

5.5

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

5.4.1

5.4.2

Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5

6

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Appendix A – Programmable Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

iv

List of Illustrations

Figure

Title

Page

4–1 Primary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . . . 4–1

4–2 FS High Mode Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . 4–2

4–3 FS Low Mode Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . 4–2

4–4 Secondary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . 4–3

4–5 FS Output During Software Secondary Serial Communication Request

(FS High Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

4–6 FS Output During Software Secondary Serial Communication Request

(FS Low Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4

5–1 Serial Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5–2 ADC Decimation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6

5–3 ADC Decimation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5–4 DAC Interpolation Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7

5–5 DAC Interpolation Filter Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8

6–1 Functional Block of a Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

6–2 Differential Configuration Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2

6–3 Single-Ended Configuration Typical Application . . . . . . . . . . . . . . . . . . . . . . . 6–3

List of Tables

Table

Title

Page

4–1 Least-Significant-Bit Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

v

vi

Introduction

The TLC320AD545 single channel data/fax codec is a mixed signal broadband connectivity device. The

TLC320AD545is comprised of a single channel codec and analog hybrid circuitry with a serial port for communication

with the host processor. The device also contains programmable gain control and one AT41 speaker driver. The

device operates with either a 5-V analog, a 5-V digital, and a 5-V monitor power supply or a 3.3-V analog, a 3.3-V

digital, and a 3.3-V monitor power supply or 5-V analog, 3.3-V digital, and a 5-V monitor power supply. The device

will be packaged in a single 48-pin PT (TQFP) package.

1.1 Features

•

Analog, Digital, and Monitor Amp Power Supplies: 5 V or 3.3 V

Differential and Single-Ended Driving of Analog Output

Software Power-Down Mode

Sample Rate Up to 11.025 kHz

16-Bit Signal Processing in the Codec With 2s-Complement Data Format

Typical 80-db Dynamic Range

Total Signal-to-Noise + Distortion of 80 dB for the ADCs

Total Signal-to-Noise + Distortion of 78 dB for the DACs

Programmable Gain Amplifier

600-Ω Driver

8-Ω AT41 Differential Speaker Driver With Programmable Gain Amplifier

Flash Write Enable Circuit Provide Power for Writing the Flash Memory Device

Available in 48-Pin PT (TQFP) Package Operating From –40 C to 85 C

Transformer Reference ( 2.5 mA Source and Sink at 2.5 V for 5 V-Supply and 1.5 V for 3.3-V Supply) to allow

Single-Ended Driving

1.2 Functional Block Diagram

1–1

H

Y

B

R

I

Data

Channel

Serial

Port

Data Channel

Codec

D

A

M

P

Flash

Write

Enable

DRVR

Control

Logic

1.3 Analog Block Diagram

DTRX_FB

Data (Hybrid)

–

+

DTRXM

DTRXP

–

16-Bit

ADC

+

MonOut PGA

0/3/6/9/12 dB Gain

with Mute

Data_In PGA

0/6/12/18 dB Gain

with Mute

2.5 V

DT_REF

2.5 V/1.5 V

–

+

M

U

X

16-Bit

DAC

DTTX_OUTP

DTTX_INM

–

+

Data (Hybrid)

2.5 V/1.5 V

MONOUTP

MONOUTM

–

+

–

DTTX_INP

8-Ω Speaker Buffer

0 dB or Mute

DTTX_OUTM

–

+

DT_BUFP

DT_BUFM

2.5 V/1.5 V

+

–

0/-6/-12/-18 dB or Mute

600-Ω Data_Out PGA

1–2

1.4 Terminal Assignments

4847 46 45 44 43 42 41 40 39 3837

DREFP_DAC

DREFM_DAC

NC

1

2

3

4

5

NC

36

35

34

33

DT_MCLK

DT_DIN

DT_SCLK

DT_DOUT

DT_FS

NC

DAV

DD

SS

32

31

30

6

7

TLC320AD545

NC

8

NC

29

28

27

9

DTRX_FB

DTRXM

RESET

10

DV

SS

NC 11

DTRXP 12

26 NC

25 NC

13 14 1516 17 1819 20 21 22 2324

NC–Make no external connection

1.5 Ordering Information

PACKAGE

T

A

PLASTIC QUAD

FLATPACK (PT)

0°C to 70°C

TLC320AD545PT

TLC320AD545IPT

–40°C to 85°C

1.6 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

NC

3, 4, 7, 8,

11, 21, 25,

26, 35, 36,

45

No connection

DAV

5

6

I

Analog power supply (5 V/3.3 V)

Analog ground

DD

SS

DREFM_ADC

48

O

ADC voltage reference filter output. DREFM_ADC provides lowpass filtering for the internal bandgap

reference. The optimal ceramic capacitor value is 0.1 uF connected between DREFM_ADC and

DREFP_ADC. The nominal dc voltage at this terminal is 0 V.

DREFM_DAC

2

O

DAC voltage reference filter output. DREFM_DAC provides for lowpass filtering the internal bandgap

reference. The optimal ceramic capacitor value is 0.1 µF connected between DREFM_ADC and

DREFP_ADC. The nominal dc voltage at this terminal is 0 V.

1–3

1.6 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

DREFP_ADC

47

O

ADC voltage reference filter output. DREFP_ADC provides lowpass filtering for the internal bandgap reference.

The optimal ceramic capacitor value is 0.1 µF connected between DREFM_ADC and DREFP_ADC. The dc

voltage at this terminal is 3.375 V with a 5-V DAV

supply and 2.25 V with a 3.3-V DAV supply.

DD

DREFP_DAC

1

O

DAC voltage reference filter output. DREFP_DAC provides for lowpass filtering the internal bandgap reference.

The optimal ceramic capacitor value is 0.1 µF connected between DREFM_DAC and DREFP_DAC. The dc

voltage at this terminal is 3.375 V at 5-V DAV

supply and 2.25 V at 3.3-V DAV supply.

DD

DT_BUFM

DT_BUFP

19

18

O

Buffer amp analog inverting output. DT_BUFM can be programmed for 0 dB, -6 dB, -12 dB, and -18 dB gain or

muted using the control registers. This output is normally fed to the DTTX_INM terminal through an input resistor.

Buffer amp analog noninverting output. DT_BUFP can be programmed for 0 dB, -6 dB, -12 dB and -18 dB gain

or muted using the control registers. This output is normally fed to the DTTX_INP terminal through an input

resistor. DT_BUFP must be left unconnected in single-ended hybrid.

DT_DIN

DT_DOUT

DT_FS

33

31

30

I

Digital data input. DT_DIN handles DAC input data as well as control register programming information during

frame sync interval and is synchronized to DT_SCLK.

O

Digital data output. ADC output bits transmit data during the frame sync period which is synchronized to

DT_SCLK. DT_DOUT is at high impedance when DT_FS is not activated.

Serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data and receiving of DAC data.

This signal can be active high (FS high mode) or active low (FS low mode) depending on the voltage applied to

SI_SEL (see Section 4, Serial Communications).

DT_MCLK

DT_REF

34

13

I

Master clock input. All internal clocks are derived from this clock.

O

Reference voltage for the transformer at 2.5 V for a 5-V DAV

supply and 1.5 V for a 3.3-V DAV supply. The

DD

maximumsourceorsinkcurrentatthisterminalis2.5mA.DT_REFmustbeleftunconnectedindifferentialhybrid.

DTRX_FB

9

O

Receive path amplifier feedback node. DTRX_FB terminal is connected to the noninverting output of the receive

path amplifier and allows a parallel resistor/capacitor to be placed in the amplifier feedback path for setting gain

and filter poles.

DTRXM

DTRXP

10

12

32

I

Receive path amplifier analog inverting input

Receive path amplifier analog noninverting input

DT_SCLK

O

Shift clock signal. DT_SCLK clocks serial data into DT_DIN and out of DT_DOUT during the frame-sync interval.

DT_SCLK rate is DT_MCLK/2.

DTTX_INM

DTTX_INP

15

16

I

Transmit amplifier analog inverting input. This node is normally fed by the DT_BUFM output through an input

resistor.

Transmit amplifier analog noninverting input. This node is normally fed by the DT_BUFP output through an input

resistor. DTTX_INP must be shorted to DTTX_OUTM in single-ended hybrid.

DTTX_OUTM

DTTX_OUTP

17

14

22

27

46

O

I

Transmit amplifier analog inverting output. DTTX_OUTM must be shorted to DTTX_INP in single-ended hybrid.

Transmit amplifier analog noninverting output

DV

Digital and RESET circuit power supply (5 V/3.3 V)

DD

SS

I

Digital and RESET circuit ground

FILT

O

Bandgap filter node. FILT provides decoupling of the bandgap reference voltage. This reference is 3.375 V with

a 5-V supply and 2.25 V with a 3.3-V supply. The optimal capacitor value is 0.1 µF (ceramic). This node should

not be used as a voltage source.

FLSH_IN

24

23

I

External ASIC logic input. When brought low, FLSH_IN enables the FLSH_OUT output.

FLSH_OUT

O

Power output to write/erase flash EEPROM device (such as Intel 28F400B or AMD Am29F400). Supplies 45

mA maximum from 5 V when FLSH_IN is brought low.

MONOUTM

MONOUTP

42

40

41

O

I

Analog output from 8-Ω monitor speaker amplifier which can be set for 0-dB gain or muted through the control

registers.

Analog output from 8-Ω monitor speaker amplifier which can be set for 0-dB gain or muted through the control

registers.

MV

DD

Monitor amplifier supply (5 V/3.3 V)

Intel is a trademark of Intel Systems, Inc.

AMD is a trademark of Advanced Micro Devices, Inc.

1–4

1.6 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

39

MV

I

Monitor amplifier ground

Codec device reset. RESET initializes all device internal registers to default values. This signal is active low.

Serial interface mode select. When SI_SEL is tied to DV the serial port is in FS high mode. When SI_SEL is

SS

RESET

SI_SEL

28

37

DD,

tied to DV , the serial port is in FS low mode. (see Section 4, Serial Communications).

SS

TCLK

38

O

Test output port. TCLK is for factory test only and should be either connected to ground or left unconnected.

TEST1

TEST2

43 I/O Test input port. TEST1 is for factory test only and should be either connected to ground or left unconnected.

44 I/O Test input port. TEST2 is for factory test only and should be either connected to ground or left unconnected.

V

SS

20

I

Internal substrate connection. V

SS

should be tied to DAV

SS .

1–5

1–6

2 Functional Description

2.1 Device Requirements and System Overview

The TLC320AD545 device consists of single codec channel, a hybrid circuit with external resistors and capacitors

for setting gain and filter poles, serial port, and miscellaneous other logic functions.

2.2 Codec Functions

The codec portion of the device performs the functions for:

•

One channel of analog-to-digital conversion

Digital-to-analog conversion

Lowpass filtering

Control of analog input and output gains

Internal oversampling coupled with internal decimation and interpolation

A 16-bit serial port interface to the host processor.

The maximum sample rate is 11.025 kHz.

2.3 Hybrid Functions

The hybrid circuitry has integrated amplifiers whose gains and filter pole frequencies are set by external resistors and

capacitors. This allows maximum flexibility to make adjustments for board variations and international standards

while providing integration of the function. The filter amplifier stages are followed by a programmable gain amplifier,

which feeds an 8 Ω differential speaker driver for the AT41 call progress monitor speaker. The monitor speaker driver

can be programmed for 0 dB gain or muted through control register 2. The source for the monitor speaker input can

be chosen to be either the amplified DAC output (Data_Out PGA) or the ADC input signal through control register

1 (see Appendix A).

A 2.5 V/1.5 V reference voltage (DT_REF) is provided as a reference for the transformer. It is necessary to reference

to 2.5 V/1.5 V (rather than ground), since the amplifiers are powered off by single-rail supplies. DT_REF is 2.5 V when

DAV

is 5 V and 1.5 V when DAV

is 3.3 V.

DD

2.4 Miscellaneous Logic and Other Circuitry

The logic functions include the circuitry required to implement serial port and control register programming through

secondary communication on those serial ports. Two control registers can be programmed during secondary

communications from the serial port. These control registers set amplifier gains, select loopback functions, and read

ADC overflow flags. In addition, a flash write enable (FWE) circuit takes an external logic input and provides current

to power the write enable circuit of an external memory device. The flash write enable circuit is powered from the

digital power supply.

2–1

2–2

3 Codec Functional Description

3.1 Operating Frequencies

The TLC320AD545 is capable of supporting any sample rate up to the maximum sample rate of 11.025 kHz. The

sample rate is set by the frequency of the codec master clock.

The sampling (conversion) frequency is derived from the codec master clock by the internal clock divider circuit by

equation (1):

DT_FS= Sampling (conversion) frequency = DT_MCLK/512

(1)

The shift clock (SCLK) is derived from the codec master clock divider circuit by equation (2):

DT_SCLK (frequency)= DT_MCLK/2

(2)

Where MCLK is codec clock fed to the codec externally by the clock rate divider circuit which divides the system

master clock to get the necessary clock frequency to feed the codec.

The conversion period is the inverse of sampling frequency.

3.2 ADC Signal Channel

The input signals are amplified and filtered by on-chip buffers before being applied to ADC input. The ADC converts

the signal into discrete output digital words in 2s-complement format, corresponding to the analog signal value at the

sampling time. These 16-bit digital words, representing sampled values of the analog input signal, are sent to the host

through the serial port interface. If the ADC reaches its maximum value, a control register flag is set. This overflow

bit resides at D0 in control register 2. This bit can only be read from the serial port, and the overflow flag is only cleared

if it is read through the serial port. The ADC and DAC conversions are synchronous and phase-locked.

3.3 DAC Signal Channel

The DAC receives 16-bit data words (2s complement) from the host through the serial port interface. The data is

converted to an analog voltage by the sigma-delta DAC comprised of a digital interpolation filter and a digital

modulator. The DAC output is then passed to an internal low-pass filter to complete the signal reconstruction resulting

in an analog signal. This analog signal is then buffered and amplified by differential output driver capable of driving

the required load. The gain of the DAC output amplifier is programmed by the codec control register as shown in

Appendix A.

3.4 Sigma-Delta ADC

The ADC is an oversampling sigma-delta modulator. The ADC provides high resolution and low noise performance

using oversampling techniques and the noise shaping advantages of sigma-delta modulators.

3.5 Decimation Filter

The decimation filter reduces the digital data rate to the sampling rate. This is accomplished by decimating with a ratio

equal to the oversampling ratio. The output of this filter is a sixteen-bit 2s-complement data word clocking at the

selected sample rate.

3.6 Sigma-Delta DAC

The DAC is an oversampling sigma-delta modulator. The DAC perform high-resolution, low-noise digital-to-analog

conversion using oversampling sigma-delta techniques.

3–1

3.7 Interpolation Filter

The interpolation filter resamples the digital data at a rate of N times the incoming sample rate where N is the

oversampling ratio. The high-speed data output from this filter is then applied to the sigma-delta DAC.

3.8 Analog and Digital Loopbacks

The test capabilities include an analog loopback and digital loopback. The loopbacks provide a means of testing the

ADC/DAC channels and can be used for in-circuit system-level tests.

Analog loopback loops the DAC output back into the ADC input. Digital loopback loops the ADC output back into the

DAC input. Analog loopback is enabled by setting bit D4 in the control register 1. Digital loopback is enabled by setting

bit D5 high in control register 1. The analog loopback function tests only the codec portion of the device and does

not include the hybrid amplifier.

3.9 Software Power Down

The software power down resets all internal counters but leaves the contents of the programmable control registers

unchanged. The software power down feature is invoked by setting bit D6 high in control register 1. There is no

hardware power down function in the TLC320AD545.

3.10 Test Module

The test module serves the purpose of facilitating design verification test and simplifying factory production testing.

There are three input/output terminals (TEST1, TEST2 and TCLK) dedicated to implementing the test functions. The

function of these terminals is for factory self-test only and NO CONNECTION (NC) should be made to either of these

terminals.

3.11 Power Supply Options

ANALOG SUPPLY

(DAV

DIGITAL SUPPLY

(DV

MONITOR SUPPLY

(MV

)

DD

5 V

DD

5 V

DD

5 V

Option 1

Option 2

Option 3

3.3 V

5 V

3.3 V

5 V

3–2

4 Serial Communications

DT_DOUT, DT_DIN, DT_SCLK, and DT_FS, are the serial communication signals for the serial port. The digital

output data from the ADC is taken from DT_DOUT. The digital input data for the DAC is applied to DT_DIN. The

synchronization clock for the serial communication data and the frame-sync is taken from DT_SCLK. The frame-sync

pulse, which signals the beginning of the ADC and DAC data transfer interval, is taken from DT_FS.

For signal data transmitted from the ADC or to the DAC, a primary serial communication is used. A secondary

communication is used to read or write words to the control registers, which control both the options and the circuit

configurations of the device.

The purpose of the primary and secondary communications is to allow conversion data and control data to be

transferred across the same serial port. A primary transfer is always dedicated to conversion data. A secondary

transfer is used to set up or read the control register values described in Appendix A, Programmable Register Set.

A primary transfer occurs for every conversion period. A secondary transfer occurs only when requested. Secondary

serial communication is requested by software (D0 of the primary data input to DT_DIN). Control registers 1 and 2

can only be read/write from/to the serial port.

4.1 Primary Serial Communication

Primary serial communication is used to both transmit and receive conversion signal data. The DAC word length is

15 bits and the last bit of the primary 16-bit serial communication word is a control bit used to request secondary serial

communication. For all serial communications, the most significant bit is transferred first. For the 16-bit ADC word,

D15 is the most significant bit and D0 is the least significant bit. For the 15-bit DAC data word in a primary

communication, D15 is the most significant bit, D1 is the least significant bit, and D0 is used for the secondary

communication request control. All digital data values are in 2s-complement data format. Refer to Figure 4–1.

DT_DIN

D15–D1

D0

Secondary

Communication Request

D/A Data

A/D Data

DT_DOUT

D15–D0

Figure 4–1. Primary Communication DIN and DOUT Data Format

4–1

4.1.1

FS High Mode Primary Communication Timing

There are two possible modes for serial data transfer. One mode is the FS high mode, which is selected by tying the

SI_SEL terminal to DV . Figure 4–2 shows the timing relationship for DT_SCLK, DT_FS, DT_DOUT and DT_DIN

DD

in a primary communication when in FS high mode. The timing sequence for this operation is as follows:

1. DT_FS is brought high and remains high for one DT_SCLK period, then goes back low.

2. A 16-bit word is transmitted from the ADC (DT_DOUT) and a 16-bit word is received for DAC conversion

(DT_DIN).

DT_SCLK

DT_FS

DT_DIN

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DT_DOUT

Figure 4–2. FS High Mode Primary Serial Communication Timing

4.2 FS Low Mode Primary Communication Timing

ThesecondpossibleserialinterfacemodeistheFSlowmodewhichisselectedbytyingtheSI_SELterminaltoDV

SS.

This mode differs from the FS high mode in that the frame sync signal (FS) is active low, data transfer starts on the

falling edge of DT_FS, and DT_FS remains low throughout the data transfer. Figure 4–3 shows the timing relationship

for DT_SCLK, DT_FS, DT_DOUT, and DT_DIN in a primary communication when in FS low mode. The timing

sequence for this operation is as follows:

1. DT_FS is brought low by the TLC320AD545.

2. A 16-bit word is transmitted from the ADC (DT_DOUT) and a 16-bit word is received for DAC conversion

(DT_DIN).

3. DT_FS is brought high signaling the end of the data transfer.

4–2

DT_SCLK

DT_FS

DT_DIN

D15 D14 D13 D12

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D11

DT_DOUT

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D11 D10

Figure 4–3. FS Low Mode Primary Serial Communication Timing

4.3 Secondary Serial Communication

Secondary serial communication is used to read or write 16-bit words that program both the options and the circuit

configurations of the device. Register programming always occurs during secondary communication. Control

registers 1 and 2 can only be written to or read from the serial port. Two primary and secondary communication cycles

are necessary to program the control registers. If the default value for a particular register is desired, then the register

addressing can be omitted during secondary communications. The NOOP (no operation) command addresses a

pseudo-register, register 0, and no register programming takes place during this secondary communication.

During a secondary communication, a register may be written to or read from. When writing a value to a register, the

DT_DIN line contains the value to be written. The data returned on DT_DOUT is 00h.

The method for requesting a secondary communication is by asserting the least significant bit (D0) of DT_DIN high

as shown in Table 4–1.

Table 4–1. Least-Significant-Bit Control Function

CONTROL BIT D0

CONTROL BIT FUNCTION

0

1

No secondary communication request

Secondary communication request

Figure 4–4 shows the data format XX_DIN and XX_DOUT during secondary communication.

Don’t Care

D15

DT_DIN

(Read)

––

1

0

D12 D11 D10 D9 D8

D7–D0

R/W

––

Register Address

D12 D11 D10 D9 D8

AII 0

Register Data

D7–D0

D15

––

DT_DIN

(Write)

Register Data

D7–D0

DT_DOUT

(Read)

D15–D8

AII 0

DT_DOUT

(Write)

D15–D0

4–3

Figure 4–4. Secondary Communication DIN and DOUT Data Format

4.4 FS High Mode Secondary Communication Timing

On the rising edge of DT_SCLK, coinciding with the falling edge of FS, D15–D0 is input serially to DT_DIN and

D15–D0 is output serially on DT_DOUT. If a secondary communication request is made, FS goes high again, 128

SCLKsafterthebeginningoftheprimaryframe, tosignalthebeginningofthesecondaryframeoneSCLKperiodlater.

See Figure 4–5.

128 DT_SCLKs

P

S

P

DT_FS

DT_DIN

Data (D0=1)

Register R/W

Data (D0=0)

Secondary Communication

Request

No Secondary

Communication Request

Figure 4–5. FS Output During Software Secondary Serial Communication Request

(FS High Mode)

4.5 FS Low Mode Secondary Communication Timing

On the falling edge of FS for that channel, D15–D0 is input serially to DT_DIN and D15–D0 is output serially on

DT_DOUT. FS remains low during the data transfer and then returns high. If a secondary communication request is

made, FS goes low 128 SCLKs after the beginning of the primary frame to signal the beginning of the secondary

frame. See Figure 4–6.

128 DT_SCLKs

DT_FS

P

S

P

Data (D0=1)

Register R/W

Data (D0=0)

DT_DIN

Secondary Communication

Request

No Secondary

Communication Request

Figure 4–6. FS Output During Software Secondary Serial Communication Request

(FS Low Mode)

4–4

5 Specifications

5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

(Unless Otherwise Noted)

Supply voltage range, DV , AV , (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

DD

Output voltage range, all digital output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV +0.3 V

DD

Input voltage range, all digital input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV +0.3 V

DD

Case temperature for 10 seconds: PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 C

Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 C to 85 C

A

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 C to 150 C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to Vss.

5.2 Recommended Operating Conditions

MIN NOM

MAX

5.5

3.6

3

UNIT

V

Supply voltage, DAV , MV , DVDD (5-V supply)

4.5

3

5

DD

Supply voltage, DAV , MV

DV (3.3-V supply) (see Note 2)

DD

3.3

V

DD

DD,

†

Analog signal peak-to-peak input voltage , DTRXM, DTRXP, V

(5-V supply)

V

I(analog)

†

Analog signal peak-to-peak input voltage , DTRXM, DTRXP, V

(3.3-V supply)

2

V

Differential output load resistance, R (DT_BUFP, DT_BUFM)

600

8

Ω

L

Differential output load resistance, R (MONOUTP, MONOUTM)

Ω

L

Input impedance for hybrid amps (DTRXP, DTRXM, DTTX_INP, DTTX_INM)

Master clock

50

8

kΩ

MHz

pF

kHz

°C

5.645

20

Load capacitance, C

L

ADC or DAC conversion rate

Operating free-air temperature, T

11.025

70

0

A

†

Preamplifier gain set to 0 dB

NOTE 2: Voltages at analog inputs and outputs and xV

are respect to the xV terminal.

SS

DD

5–1

5.3 Electrical Characteristics Over Recommended Operating Free-Air

Temperature Range DV = 5 V/3.3 V, AV = 5 V/3.3 V, MV = 5 V/3.3 V

DD

5.3.1 Digital Inputs and Outputs, f = 8 kHz, Outputs Not Loaded

s

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DV

+ 0.5

DD

V

High-level output voltage, any digital output

I

= –360 µA

2.4

V

OH

O

DV

SS

Low-level output voltage, any digital output

I

= 2 mA

0.4

V

OL

– 0.5

I

High-level input current, any digital input

Low-level input current, any digital input

Input capacitance, any digital input

V

= 5 V

10

µA

pF

µA

IH

= 0.6 V

IL

C

10

j

Output capacitance, any digital output

Input leakage current, any digital input

Output leakage current, any digital output

O

I

10

I(lkg)

OZ

I

5.3.2 ADC Channel, f = 8 kHz (see Note 3)

s

PARAMETER

TEST CONDITIONS

0 to 300 Hz

300 Hz to 3 kHz

3.3 kHz

MIN

–0.5

TYP

MAX

0.2

UNIT

–0.25

–0.35

0.25

0.3

Filter gain relative to gain at 1020 Hz

dB

3.6 kHz

–3

4 kHz

–35

–74

≥4.4 kHz

NOTE 3: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The analog input test signal is a sine wave with

0 dB=3 V at 5-V supply and 0 db = 2 V at 3.3-V supply differential as the reference level for ADC analog input signal. The –3 dB

PP

passband is 0 to 3600 Hz for an 8-kHz sample rate. This passband scales linearly with the sample rate.

5.3.3 ADC Dynamic Performance, f = 8 kHz

s

5.3.3.1 ADC Signal-to-Noise (see Note 4)

PARAMETER

TEST CONDITIONS

V = –1 dB

MIN

76

TYP

81

MAX

UNIT

I

Signal-to-noise ratio (SNR)

V = –9 dB

I

68

73

dB

V = –40 dB

I

37

42

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output common mode is 2.5 V for 5 V supply and

1.5 V for 3.3 V supply. The output configuration is in a 5 V differential-ended mode.

5.3.3.2 ADC Signal-to-Distortion (see Note 4)

PARAMETER

TEST CONDITIONS

V = –3 dB

MIN

74

TYP MAX

UNIT

79

87

63

I

Signal-to-total harmonic distortion (THD)

V = –9 dB

I

82

dB

V = –40 dB

I

58

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output common mode is 2.5 V for 5 V supply and

1.5 V for 3.3 V supply. The output configuration is in a 5 V differential-ended mode.

5–2

5.3.3.3 ADC Signal-to-Distortion + Noise (see Note 4)

PARAMETER

TEST CONDITIONS

V = –3 dB

MIN

71

TYP MAX

UNIT

76

73

42

I

Signal-to-total harmonic distortion + noise (THD + N)

V = –9 dB

I

68

dB

VI = –40 dB

37

NOTE 4: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output common mode is 2.5 V for 5-V supply and

1.5 V for 3.3-V supply. The output configuration is in a 5 V differential-ended mode.

5.3.4 ADC Characteristics

PARAMETER

Peak-input voltage (5.0 V supply)

Peak-input voltage (3.3 V supply)

Dynamic range

TEST CONDITIONS

Preamp gain = 0 dB

MIN

TYP MAX

UNIT

V

3

I(PP)

2

V

I(PP)

V =–1 dB at 1020 Hz

I

80

87

dB

mV

dB

Interchannel isolation

E

Gain error

V = –1 dB at 1020 Hz

I

±0.5

10

G

ADC channel offset error including hybrid amplifiers

Common-mode rejection ratio

Idle channel noise (on-chip reference)

Channel delay

O(ADC)

CMRR

V = –1 dB at 1020 Hz

I

80

50

17/f

100 µVrms

s

5.3.5 DAC Channel, f = 8 kHz (see Note 5)

s

PARAMETER

TEST CONDITIONS

0 to 300 Hz

300 Hz to 3 kHz

3.3 kHz

MIN

–0.5

TYP MAX

UNIT

0.2

0.25

0.3

–0.25

–0.35

Filter gain relative to gain at 1020 Hz

dB

3.6 kHz

–3

4 kHz

–35

NOTE 5: The filter gain outside of the passband is measured with respect to the gain at 1020 Hz. The input signal is the digital equivalent of a

sine wave (digital full scale = 0 dB). The –3 dB pass band is 0 to 3600 Hz for an 8-kHz sample rate. This pass band scales linearly

with the sample rate.

5.3.6 DAC Dynamic Performance

5.3.6.1 DAC Signal-to-Noise (see Note 6)

PARAMETER

TEST CONDITIONS

V = 0 dB

MIN

72

TYP MAX

UNIT

77

68

37

I

Signal-to-noise ratio (SNR)

V = –9 dB

I

63

dB

V = –40 dB

I

32

NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 5 V differential-endedmode.

5.3.6.2 DAC Signal-to-Distortion (see Note 6)

PARAMETER

TEST CONDITIONS

V = –3 dB

MIN

77

TYP MAX

UNIT

82

77

66

I

Signal-to-total harmonic distortion (THD)

V = –9 dB

I

72

dB

V = –40 dB

I

61

NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 5 V differential-endedmode.

5–3

5.3.6.3 DAC Signal-to-Distortion + Noise (see Note 6)

PARAMETER

TEST CONDITIONS

VI = –3 dB

MIN

73

TYP MAX

UNIT

78

72

37

Signal-to-total harmonic distortion + noise (THD + N)

VI = –9 dB

67

dB

VI = –40 dB

32

NOTE 6: The test condition is a 1020-Hz input signal with an 8-kHz conversion rate. The output configuration is in a 5 V differential-endedmode.

5.3.7 DAC Characteristics

PARAMETER

TEST CONDITIONS

V = 0 dB at 1020 Hz

MIN

TYP MAX

UNIT

dB

Dynamic range

82

100

I

Interchannel isolation

Gain error

dB

E

G

V = 0 dB at 1020 Hz

I

±0.5

dB

Idle channel narrow-band noise

Channel delay

0 kHz to 4 kHz (see Note 7)

75

18/f

125 µV rms

s

Differential with respect to common

mode and full-scale digital input (see

Note 8)

V

Analog output voltage, MONOUTP-MONOUTM (5.0 V)

Analog output voltage, MONOUTP-MONOUTM (3.3 V)

–1.78

–1.2

1.78

1.2

V

O

Differential with respect to common

mode and full-scale digital input (see

Note 8)

O

Differential with respect to common

mode and full-scale digital input

V

Analog output voltage (5 V)

Analog output voltage, (3.3 V)

–3

–2

3

2

V

O

Differential with respect to common

mode and full-scale digital input

O

NOTES: 7. The conversion rate is 8 kHz.

8. This amplifier should only be used in differential mode. Common mode : 2.5 V in 5-V supply, 1.5 V in 3.3-V supply.

5.3.8 Logic DC Electrical Characteristics

PARAMETER

MIN

–0.3

TYP

MAX

UNIT

V

Low-level input voltage

High-level input voltage

Input leakage current

Output leakage current

0.8

IL

2

DV +0.3

DD

V

IH

I

10

µA

V

I(lkg)

O(lkg)

V

High-level output voltage at rated load current

Low-level output voltage at rated load current

2.4

DV +0.5

DD

OH

OL

V

DV –0.5

SS

0.4

V

5.3.9 Power-Supply Rejection (see Note 9)

PARAMETER

TEST CONDITIONS

f = 0 to f /2

MIN

TYP

MAX

UNIT

V

DD1

V

DD2

V

DD3

V

DD4

Supply-voltage rejection ratio, ADC channel, DAV

Supply-voltage rejection ratio, DAC channel, DAV

73

76

86

95

DD

I

s

f = 0 to f /2

DD

I

s

dB

Supply-voltage rejection ratio, ADC channel, DV

Supply-voltage rejection ratio, DAC channel, DV

f = 0 to f /2

I s

DD

f = 0 to 30 kHz

I

DD

NOTE 9: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200 mV peak-to-peak signal

applied to the appropriate supply.

5.3.10 Power-Supply

PARAMETER

TEST CONDITIONS

Operating

MIN

TYP

25

5

MAX

UNIT

mA

Codec power supply current, analog (including hybrid and

drivers)

I

(analog)

(digital )

DD

Codec power supply current, digital

Operating

mA

DD

5–4

PARAMETER

TEST CONDITIONS

Operating

MIN

TYP MAX

UNIT

mA

I

(monitor) Power supply current, 8 Ω monitor speaker driver (5 V)

(monitor) Power supply current, 8 Ω monitor speaker driver (3.3 V)

135

315

240

DD

Operating

mA

DD

5.3.11 Flash Write Enable Circuit

PARAMETER

TEST CONDITIONS

FLSH_IN low

MIN

4.5

2.8

0

TYP MAX

UNIT

V

Output high-level voltage (5 V supply), FLSH_OUT

Output high-level voltage (3.3 V supply), FLSH_OUT

Output low-level voltage, FLSH_OUT

5

5.5

3.8

1.5

45

OH(FLSH_OUT)

OL(FLSH_OUT)

O(FLSH_OUT)

FLSH_IN low

3.3

V

FLSH_IN high

FLSH_IN low

V

I

Output current (5 V supply), FLSH_OUT

40

25

mA

Output current (3.3 V supply), FLSH_OUT

FLSH_IN low

5.4 Timing Characteristics (see Parameter Measurement Information)

5.4.1 Timing Requirements

PARAMETER

MIN

TYP

MAX

UNIT

ns

t

Delay time, DT_SCLK↑ to DT_FS↓

0

d1

Setup time, DT_DIN, before DT_SCLK low

Hold time, DT_DIN, after DT_SCLK high

Delay time, DT_MCLK↓ to DT_SCLK↑

Pulse duration, DT_MCLK high

25

ns

su1

h1

20

50

ns

d3

32

20

ns

wH

wL

Pulse duration, DT_MCLK low

ns

5.4.2 Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

20

UNIT

ns

t

Delay time, DT_SCLK↑ to DT_DOUT

Enable time, FS↓ to DT_DOUT

Disable time, FS↑ to DT_DOUT Hi-Z

Reset pulse width

d2

C

= 20 pF

L

25

en1

dis1

20

T

PW

10MCLK

ns

5.5 Parameter Measurement Information

5–5

t

wH

DT_MCLK

DT_SCLK

t

d3

wL

t

d1

DT_FS

DT_DOUT

DT_DIN

t

dis1

t

d2

D15

D14

t

en1

t

su1

D15

t

h1

Figure 5–1. Serial Communication Timing

0

–20

–40

–60

–80

–100

– 120

0.8

1.6

2.4

3.2

4

4.8

5.6

6.4

7.2

f – Input Frequency – kHz

I

Figure 5–2. ADC Decimation Filter Response

5–6

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0.4

0.8

1.2

1.6

2

2.4

2.8

3.2

f – Input Frequency – kHz

I

Figure 5–3. ADC Decimation Filter Passband Ripple

0

–20

–40

–60

–80

–100

– 120

0.8

1.6

2.4

3.2

4

4.8

5.6

6.4

7.2

f – Input Frequency – kHz

I

Figure 5–4. DAC Interpolation Filter Response

5–7

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0.4

0.8

1.2

1.6

2

2.4

2.8

3.2

f – Input Frequency – kHz

I

Figure 5–5. DAC Interpolation Filter Passband Ripple

5–8

6 Application Information

H

Y

B

R

I

Data

Channel

Serial

Port

Matching

Network

POTS

Data Channel

Codec

D

A

M

P

Flash

Write

Enable

Control

Logic

AT41

SPKR

DRVR

Figure 6–1. Functional Block of a Typical Application

6–1

DTRX_FB

Data (Hybrid)

DTRXM

–

+

16-Bit

ADC

+

MonOut PGA

0/3/6/9/12 dB Gain

with Mute

DTRXP

Data_In PGA

T1

0/6/12/18 dB Gain

with Mute

2.5 V/1.5 V

DT_REF

2.5 V/1.5 V

–

+

M

U

X

Primary

Line

16-Bit

DAC

DTTX_OUTP

MONOUTP

AT41

–

+

Data (Hybrid)

–

+

DTTX_INM

DTTX_INP

8-Ω Speaker Buffer

2.5 V/1.5 V

MONOUTM

0 dB or Mute

+

–

DTTX_OUTM

DT_BUFP

–

+

2.5 V/1.5 V

+

–

DT_BUFM

0/-6/-12/-18 dB or Mute

600-Ω Data_Out PGA

†

Required to meet communication standards

Figure 6–2. Differential Configuration Typical Application

6–2

DTRX_FB

Data (Hybrid)

DTRXM

–

+

–

+

16-Bit

ADC

Mon_Out PGA

0/3/6/9/12 dB Gain

with Mute

DTRXP

T1

Data_In PGA

0/6/12/18 dB Gain

with Mute

2.5 V/1.5 V

DT_REF

2.5 V/1.5 V

Primary

Line

–

+

M

U

X

16-Bit

DAC

DTTX_OUTP

MONOUTP

AT41

–

+

Data (Hybrid)

–

+

DTTX_INM

8-Ω Speaker Buffer

0 dB or Mute

2.5 V/1.5 V

MONOUTM

+

–

DTTX_INP

DTTX_OUTM

–

+

DT_BUFP(NC)

DT_BUFM

2.5 V/1.5 V

+

–

0/-6/-12/-18 dB or Mute

600-Ω Data_Out PGA

†

Required to meet communication standards

Figure 6–3. Single-Ended Configuration Typical Application

6–3

6–4

Appendix A

Programmable Register Set

Bits D12–D8 in a secondary serial communication comprise the address of the register that is written with data carried

in bits D7–D0. D13 determines a read or write cycle to the addressed register. When low (0), a write cycle is selected.

The following table shows the register map.

Table A–1. Register Map

REGISTER NO.

D15 D14 D13 D12 D11 D10

D9

0

D8

1

REGISTER NAME

Control 1

1

2

0

R/W

0

1

0

Control 2

Table A–2. Control Register 1

D0 DESCRIPTION

D7

1

D6

D5

D4

D3

D2

D1

Software reset asserted

Software reset not asserted

S/W power down enabled

S/W power down disabled

Digital loopback asserted

Digital loopback not asserted

Analog loopback asserted

Analog loopback not asserted

0

1

0

1

0

1

0

1

0

Select data_in PGA for monitor amp input

Select DAC output for monitor amp input

Monitor amp PGA gain = 12 dB

Monitor amp PGA gain = 9 dB

Monitor amp PGA gain = 6 dB

Monitor amp PGA gain = 3 dB

Monitor amp PGA gain = 0 dB

Monitor amp PGA gain = mute

1

0

1

0

1

0

1

0

1

0

Default value: 00000000

A–1

Table A–3. Control Register 2

D7

1

D6

0

D5

0

D4

D3

D2

D1

D0

DESCRIPTION

Data in (DTRX) PGA gain = mute

Data in (DTRX) PGA gain = 18 dB

Data in (DTRX) PGA gain = 12 dB

Data in (DTRX) PGA gain = 6 dB

Data in (DTRX) PGA gain = 0 dB

DAC data out PGA gain = mute

DAC data out PGA gain = –18 dB

DAC data out PGA gain = –12 dB

DAC data out PGA gain = –6 dB

DAC data out PGA gain = 0 dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8 Ω monitor speaker driver gain = 0 dB

8 Ω monitor speaker driver gain = mute

ADC overflow indicator: ← 1 = overflow

X

Default value: 00000000

A–2