TLC34058-110MHFG [TI]
256 x 24 COLOR PALETTE; 256× 24的调色板
| 型号： | TLC34058-110MHFG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 256 x 24 COLOR PALETTE |
| 文件： | 总21页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
• LinEPIC 1-µm CMOS Process
• 125-MHz Pipelined Architecture
• Available Clock Rate . . . 110 MHz
• Direct Interface to SMJ340xx Graphics
Processors
• Standard Microprocessor Unit (MPU)
Palette Interface
• Dual-Port Color RAM
• Multiplexed-TTL Pixel Ports
256 Words x 24 Bits
• Triple Digital-to-Analog Converters (DACs)
• Dual-Port Overlay Registers . . . 4 × 24 Bits
• 5-V Power Supply
• Bit-Plane Read and Blink Masks
• EIA RS-343-A Compatible Outputs
• Functionally Interchangeable With
Brooktree Bt458
description
The TLC34058-110M color-palette integrated circuit is specifically developed for high-resolution color graphics
in such applications as CAE/CAD/CAM, image processing, and video reconstruction. The architecture provides
for the display of 1280 × 1024 bit-mapped color graphics (up to eight bits per pixel resolution) with two bits of
overlay information. The TLC34058-110M has a 256-word × 24-bit RAM used as a lookup table with three 8-bit
video D/A converters.
On-chip features such as high-speed pixel clock logic minimize costly ECL interface. Multiple pixel ports and
internal multiplexing provide TTL-compatible interface (up to 32 MHz) to the frame buffer while maintaining
sophisticated color graphic data rates (up to 135 MHz). Programmable blink rates, bit plane masking and
blinking, color overlay capability, and a dual-port palette RAM are other key features. The TLC34058-110M
generates red, green, and blue signals compatible with EIA RS-343-A and can drive 75-Ω coaxial cables
terminated at each end without external buffering.
AVAILABLE OPTIONS
PACKAGE
DAC
T
A
SPEED
84-PIN
84-PIN
RESOLUTION
CERAMIC GRID ARRAY
QUAD FLAT PACKAGE
–55°C to 125°C 110 MHz
8 Bits
TLC34058-110MGA
TLC34058-110MHFG
LinEPIC is a trademark of Texas Instruments Incorporated.
Brooktree is a registered trademark of Brooktree Corporation.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
HFG PACKAGE
(TOP VIEW)
21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3 2 1
D0
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
84 P2B
83 P2C
82 P2D
81 P2E
80 P3A
79 P3B
D1
D2
D3
D4
D5
D6
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
P3C
P3D
P3E
GND
D7
CE
GND
GND
V
V
DD
DD
V
DD
C0
C1
CLK
CLK
LD
R/W
V
BLK
SYNC
P4A
P4B
P4C
P4D
DD
IOR
IOG
IOB
FS ADJ
COMP
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
84-pin GA package pin assignments
SIGNAL
BLK
PIN NO.
L9
SIGNAL
Port 5
P5A
PIN NO.
SIGNAL
PIN NO.
Power, Reference and
MPU Interface
SYNC
LD
M10
M9
K11
L12
K12
J11
J12
P5B
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
C12
C11
A9
CLK
L8
P5C
CLK
M8
P5D
P5E
L7
Port 0
P0A
P0B
P0C
P0D
P0E
Port 1
P1A
P1B
P1C
P1D
P1E
Port 2
P2A
P2B
P2C
P2D
P2E
Port 3
P3A
P3B
P3C
P3D
P3E
Port 4
P4A
P4B
P4C
P4D
P4E
Port 6
P6A
M7
A7
G1
G2
H1
H2
J
H11
H12
G12
G11
F12
P6B
GND
GND
GND
GND
GND
COMP
FS ADJ
REF
CE
B12
B11
M6
B6
P6C
P6D
P6E
Port 7
P7A
A6
J2
K1
L1
K2
L2
F11
E12
E11
D12
D11
A12
B10
C10
A5
P7B
P7C
P7D
P7E
R/W
C1
B8
Overlay Select 0
OL0A
OL0B
OL0C
OL0D
OL0E
Overlay Select 1
OL1A
OL1B
OL1C
OL1D
OL1E
DAC Current Outputs
IOG
A8
K3
M1
L3
A1
C2
B1
C1
D2
C0
B7
Data Bus
D0
C3
B2
B3
A2
A3
B4
A4
B5
M2
M3
D1
D2
D3
L4
M4
L5
D1
E2
E1
F1
F2
D4
D5
D6
M5
L6
D7
M11
L10
L11
A10
A11
B9
IOB
IOR
K10
M12
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
functional block diagram
REF
FS ADJ
CLK
CLK
Reference
Amplifier
COMP
IOR
Load
Control
Multiplex
Control
Blink
Control
LD
8-Bit
D/A
Converter
40
10
40
10
40
10
8
2
8
8
2
P0–P7
(A–E)
256 Words
8
8
× 24 Bits
Palette
RAM
Input
Latch
Latch
MUX
Read Blink
Mask Mask
8-Bit
D/A
Converter
OL0–OL1
(A–E)
IOG
IOB
4 × 24
Overlay
Palette
SYNC
BLK
8-Bit
D/A
Converter
Registers
CE
To
R/W
C0
Bus
Control
Control
Functions
C1
To
8
8
8
Address
Control
Functions
Address
Register
D0–D7
Red
Value
Green
Value
Blue
Value
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
Terminal Functions
TERMINAL
NAME
BLK
I/O
DESCRIPTION
†
NO.
69
I
Compositeblank control input. This TTL-compatible blanking input is stored in the input latch on the rising edge
of LD. When low, BLK drives the DAC outputs to the blanking level as shown in Table 6. This causes the P0–P7
(A–E) and OL0–OL1 (A–E) inputs to be ignored. When high, BLK allows the device to perform in the standard
manner.
C0, C1
CE
34, 35
30
I
I
Commandcontrolinputs. C0andC1specifythetypeofwriteorreadoperation(seeTables1, 2, 3, and4). These
TTL-compatible inputs are latched on the falling edge of CE.
Chip-enable input. This TTL-compatible input control allows data to be stored and enables data to be written
or read (see Figure 1). When low, CE enables data to be written or read. When high, CE allows data to be
internally latched on the rising edge during write operations. Care should be taken to avoid transients on this
input.
CLK
72
I
Clockinput. CLKprovidesthepixelclockrate. CLKandCLKinputsaredesignedtobedrivenbyECLlogicusing
a 5-V single supply.
71
42
I
I
Clock input. CLK is the complement of CLK and also provides the pixel clock rate.
CLK
COMP
Compensation input. COMP is used to compensate the internal reference amplifier (see the video generation
section). A 0.1-µF ceramic capacitor is connected between this terminal and V
DD
possible supply voltage rejection ratio is attained by connecting the capacitor to V
(see Figure 4). The highest
rather than to GND.
DD
D0–D7
FS ADJ
22–29
41
I
I
Data input bus. This TTL-compatible bus transfers data into or out of the device. The data bus is an 8-bit
bidirectional bus where D0 is the least significant bit.
Full-scale adjust control input. A resistor R
(see Figure 4), which is connected between this terminal and
GND, controls the magnitude of the full-scale video signal. The proportional current and voltage relationships
set
in Figure 3 are maintained independently of the full-scale output current. The relationships between R
the IOR, IOG, and IOB full-scale output currents are:
and
set
R
(Ω) = 11294 × V (V) / IOG(mA)
set ref
IOR, IOB (mA) = 8067 × V (V) / R (Ω)
ref set
GND
31, 32,
44, 46,
75
Ground. All GND terminals must be connected together.
IOR, IOG
IOB
38, 39,
40
O
I
Current outputs red, green, and blue. High-impedance red, green, and blue video analog current outputs can
directly drive a 75-Ω cable coaxial terminated at each end (see Figure 4).
70
LD
Load-control input. This TTL-compatible load control (LD) input latches the P0–P7 (A–E), OL0–OL1 (A–E),
BLK, and SYNC inputs on its rising edge. The LD strobe occurs at 1/4 or 1/5 the clock rate and may be phased
independently of CLK and CLK. The LD duty cycle limits are specified in the timing requirements table.
OL0A–OL1A
OL0B–OL1B
OL0C–OL1C
OL0D–OL1D
OL0E–OL1E
12–21
l
Overlay selection inputs. These TTL-compatible inputs for the palette-overlay registers are stored in the input
latch on the rising edge of LD. These inputs (up to 2 bits per pixel) along with bit CR6 of the command register
(refer to the command register section and Table 5) specify whether the color information is selected from the
palette RAM or the overlay registers. If the color information is selected from the overlay registers, the
OL0–OL1(A–E)inputsaddressaparticularoverlayregister.TheOL0–OL1(A–D)orOL0–OL1(A–E)inputs
are simultaneously input to the device (see the description of bit CR7 in the command register section). The
OL0–OL1 (A) inputs are processed first, then the OL0–OL1 (B) inputs, and so on. When obtaining the color
information from the overlay registers, the P0–P7 (A – E) inputs are ignored. Unused inputs should be
connected to GND.
P0A –P7A
P0B–P7B
P0C–P7C
P0D–P7D
P0E–P7E
1–11,
48–67,
76–84
l
Addressinputs.TheseTTL-compatibleinputsforthepaletteRAMarestoredintheinputlatchontherisingedge
of LD. These address inputs (up to 8 bits per pixel) select one of 256 24-bit words in the palette RAM, which
is subsequently input to the red, green, and blue D/A converters as three 8-bit or 4-bit bytes. Four or five
addresses are simultaneously input to the P0–P7 (A–D) or P0–P7 (A–E) ports, respectively (see the
description of bit CR7 in the command register section). The word addressed by P0A–P7A is first sent to the
DACs, then the word addressed by P0B–P7B, and so on. Unused inputs should be connected to GND.
REF
43
I
Reference voltage input. Voltage of 1.235 V is supplied at this input. An external voltage reference circuit,
shown in Figure 4, is suggested. Generating the reference voltage with a resistor network is not recommended
since low-frequency power supply noise directly couples into the DAC output signals. This input must be
decoupled by connecting a 0.1-µF ceramic capacitor between V and GND.
ref
†
Terminal numbers shown are for the HFG package only. For the GA package terminal assignments, see page 3.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
†
NAME
R/W
NO.
36
I
Read/write input. This TTL-compatible control input is latched on the falling edge of CE (see Figure 1). When
low, R/W writes data to the device. Data is internally latched on the rising edge of CE. When high, R/W reads
data from the device.
68
I
Composite sync control input. This TTL-compatible SYNC input is stored in the input latch on the rising edge
of LD. When low, SYNC turns off a 40 IRE current source on the IOG output (see Figure 3). This input does
not override any control data input (see Table 6). It should be brought low during the blanking interval only (see
Figure 3). When high, SYNC allows the device to perform in the standard manner.
SYNC
V
DD
33, 37,
45, 47,
73, 74
Supply voltage. All V
terminals must be connected together.
DD
†
Terminal numbers shown are for the HFG package only. For the GA package terminal assignments, see page 3.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Voltage range on any digital input (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to V
Analog output short-circuit current to any power supply or common, I
Operating free-air temperature range, T
+ 0.5 V
DD
. . . . . . . . . . . . . . . . . . . . . . unlimited
OS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
4.5
5
5.5
DD
CLK, CLK
V
–1
V
V
V
+0.5
V
DD
DD
DD
DD
High-level Input voltage, V
IH
Other inputs
CLK, CLK
2
–0.5
–0.5
1.2
+0.5
–1.6
0.8
V
V
Low-level Input voltage, V
IL
Other inputs
V
Reference voltage, V
ref
1.235
37.5
523
1.26
V
Output load resistance, R
Ω
L
FS ADJ resistor, R
set
Ω
Operating free-air temperature, T
–55
125
°C
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, R = 523 Ω, V = 1.235 V (unless otherwise noted)
set
ref
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
µA
I
Input reference current
10
0.5
ref
f = 1 kHZ,
See Figure 4
C8 = 0.1 µF,
%
k
Supply voltage rejection ratio
SVR
%∆V
DD
V
V
= 5 V,
T
= 20°C
195
DD
A
I
I
I
Supply current
mA
DD
= 5.5 V,
T
A
= –55°C
550
10
DD
CLK, CLK
V = V
I
µA
µA
µA
µA
pF
pF
V
CC
High-level input current
Low-level input current
IH
IL
Other inputs
CLK, CLK
V = 2.4 V
I
10
V = 0 V
I
–10
–10
20*
20*
Other inputs
V = 0.8 V
I
C
C
Input capacitance, digital
f = 1 MHz,
f = 1 MHz,
V
V
= 1 V
= 1 V
4
4
i
I(PP)
Input capacitance, CLK, CLK
High-level output voltage, D0–D7
Low-level output voltage, D0–D7
High-impedance-state output current
Output impedance
i(CLK)
OH
OL
I(PP)
V
V
I
I
= –800 µA
2.4
OH
= 6.4 mA
0.4
10
V
OL
I
µA
kΩ
pF
OZ
z
50
13
o
C
Output capacitance (f = 1 MHz, I = 0)
20*
o
O
* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
†
All typical values are at T = 25°C.
A
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, R = 523 Ω, V = 1.235 V (see Note 2)
set
ref
MIN
MAX
110
UNIT
MHz
MHz
ns
Clock frequency
LD frequency
27.5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, R/W, C0, C1 high before CE↓
Setup time, write data before CE↑
Setup time, pixel and control
Hold time, R/W, C0, C1 high after CE↓
Hold time, write data after CE↑
Hold time, pixel and control
Pulse duration, CE low
0
35
3
su1
su2
su3
h1
ns
ns
15
3
ns
ns
h2
2
ns
h3
50
25
4
ns
w1
w2
w3
w4
w5
w6
c1
Pulse duration, CE high
ns
Pulse duration, CLK high
Pulse duration, CLK low
ns
4
ns
Pulse duration, LD high
15
15
9.09
36.36
ns
Pulse duration, LD low
ns
Clock cycle time
ns
LD cycle time
ns
c2
†
See Figures 1 and 2.
NOTE 2: TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are V
–1.8 V to
DD
V
–0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points are
DD
at the 50% signal level. Analog output loads are less than 10 pF. D0–D7 output loads are less than 40 pF.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature, R
= 523 Ω, V = 1.235 V (unless otherwise noted)
set
ref
analog outputs
†
PARAMETER
MIN TYP
MAX
±1
UNIT
LSB
LSB
E
E
Integral linearity error (each DAC)
Differential linearity error
Gray-scale error
L
±1
D
±5%
20.4
18.5
1.9
White level relative to blank
White level relative to black
Black level relative to blank
Blank level on IOR, IOB
Blank level on IOG
17.69 19.05
16.74 17.62
mA
0.95
–10
6.29
–10
1.44
5
I
O
Output current
50
µA
mA
µA
µA
7.6
5
8.96
50
Sync level on IOG
LSB size
69.1
2%
DAC to DAC matching
Output compliance voltage
5%
1.2
–1
V
†
All typical values are at T = 25°C.
A
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, R
= 523 Ω, V = 1.235 V (see Note 2)
set
ref
PARAMETER
MIN
TYP
MAX
UNIT
ns
t
t
t
t
t
t
CE low to data bus enabled
10
en1
en2
dis
d
CE low to data valid
75
15
ns
CE high to data bus disabled
ns
Analog output delay time (see Note 3)
Analog output transition time (see Note 4)
Analog output settling time (see Note 5)
Glitch impulse (see Note 6)
10
2
ns
ns
t
9
ns
s
50
0
pV-s
Analog output skew
Pipeline delay
ns
2
clock
cycles
6
10
NOTES: 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are V
–1.8 V
DD
–0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points
to V
DD
are at the 50% signal level. Analog output loads are less than 10 pF. D0–D7 output loads are less than 40 pF.
3. Measured from 50% point of rising clock edge to 50% point of full-scale transition
4. Measured between 10% and 90% of full-scale transition
5. Measured from 50% point of full-scale transition to output settling within ± 1
6. Glitch impulse includes clock and data feedthrough. The –3-dB test bandwidth is twice the clock rate.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
h1
t
su1
R/W, C0, C1
CE
t
w1
50%
50%
50%
t
w2
t
en2
t
dis
t
en1
D0–D7 (read)
D0–D7 (write)
t
su2
t
h2
Figure 1. Read/Write Timing Waveform
t
c2
t
t
w6
w5
LD
50%
50%
Data
50%
P0 –P7 (A–B),
50%
50%
OL0–OL1 (A–B),
SYNC, BLK
t
d
t
s
90%
t
su3
t
h3
50%
10%
IOR, IOG, IOB
t
t
t
c1
t
w3
CLK
50%
50%
50%
t
w4
Figure 2. Video Input/Output Timing Waveform
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
PARAMETER MEASUREMENT INFORMATION
RED/BLUE
GREEN
mA V
mA
V
White Level
19.05 0.714 26.67 1.000
92.5 IRE
Black Level
Blank Level
1.44 0.054 9.05 0.340
0.00 0.000 7.62 0.286
7.5 IRE
40 IRE
Sync Level
0.00
0.00
NOTE: The IRE (Institute of Radio Engineers – now IEEE) scale is used for defining the relative voltage levels of the sync, white, black, and blank
levelsinamonitorcircuit. Thereferencewhitelevelissetat100IREunits. TheblankinglevelissetatφIREunits. OneIREunitisequivalent
to 1/100 of the difference between the reference white level and the blanking level.
Figure 3. Composite Video Output Waveforms
COMP
C8
L1
V
DD
5 V (V
)
DD
C5–C7
C9
C2–C4
R4
C1
REF
C10
TLC34058
Z1
GND
GND
R
R1
R2
R3
set
FS ADJ
IOR
To
Video
Connector
IOG
IOB
LOCATION
DESCRIPTION
0.1-µF ceramic capacitor
VENDOR PART NUMBER
C1–C4, C8, C9
Erie RPE112Z5U104M50V
C5–C7
C10
0.01-µF ceramic chip capacitor AVX 12102T903QA1018
33-µF tantalum capacitor
ferrite bead
Mallory CSR13-K336KM
Fair-Rite 2743001111
Dale CMF-55C
L1
R1, R2, R3
R4
75-Ω 1% metal film resistor
1000-Ω 1% metal film resistor
523-Ω 1% metal film resistor
1.2-V diode
Dale CMF-55C
R
set
Z1
Dale CMF-55C
National Semiconductor
LM385Z-1.2
NOTE: The above listed vendor numbers are listed only as a guide. Substitution of devices with
similar characteristics does not degrade the performance of the TLC34058.
Figure 4. Circuit Diagram
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
PARAMETER MEASUREMENT INFORMATION
5 V
220 Ω
5 V
CLK
CLK
330 Ω
5 V
220 Ω
Monitor
Products
970E
CLK
LDA
CLK
Clock
Generator
330 Ω
TLC34058
LD
5 V
0.1 µF
1 kΩ
V
ref
REF
Figure 5. Generating the Clock, Load, and Voltage-Reference Signals
V
DD
G0–G7
15 PF
C (stray + load)
BLK
R
L
SYNC
(IOG only)
Figure 6. Equivalent Circuit of the Current Output (IOG)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
APPLICATION INFORMATION
device ground plane
Use of a four-layer PC board is recommended. All the ground pins, voltage reference circuitry, power supply
bypass circuitry, analog output signals, and digital signals as well as any output amplifiers should have a
common ground plane.
device analog power plane (APP)
Thedeviceplusassociatedanalogcircuitryshouldhaveaseparateanalogpowerplane(APP)forV .TheAPP
DD
powers the device, voltage reference circuitry, and any output amplifiers. It is connected to the overall PCB
power plane (V ) at a single point through a ferrite bead, which should be within three inches of the device.
DD
This connection is shown in Figure 4.
PCB power plane and PCB ground plane
The PCB power plane powers the digital circuitry. The PCB power plane and PCB ground planes should not
overlay the APP unless the plane-to-plane noise is common mode.
supply decoupling
Bypass capacitors should have the shortest possible lead lengths to reduce lead inductance. For best results,
connect a parallel combination of 0.1-µF ceramic and 0.01-µF chip capacitors from each V
to GND. If chip
DD
capacitors are not feasible, radial-lead ceramic capacitors may be substituted. These capacitors should be
located as close to the device as possible.
The performance of the internal power supply noise-rejection circuitry decreases with noise frequency. If a
switching power supply is used for V , close attention must be paid to reducing power supply noise. To reduce
DD
such noise, power the APP with a three-terminal voltage regulator.
digital interconnect
Isolate the digital inputs from the analog outputs and other analog circuitry as much as possible. Shielding the
digital inputs reduces noise on the power and ground lines. Minimize the lengths of clock and data lines to
prevent high-frequency clock and data information from inducing noise into the analog part of the video system.
Active termination resistors for the digital inputs should be connected to the PCB power plane, not the APP.
Ensure that these digital inputs do not overlay the device ground plane.
analog signal interconnect
Minimizing the lead lengths between groups of V
and GND minimizes inductive ringing. To minimize noise
DD
pickup due to reflections and impedance mismatch, locate the device as close to the output connectors as
possible. The external voltage reference should also be as close to the device as possible to minimize noise
pickup. To maximize high-frequency supply voltage rejection, overlay the video output signals to the device
ground plane and not the APP.
Each analog output has a 75-Ω load resistor connected to GND for maximum performance. To minimize
reflections, the resistor connections between current output and ground should be as close to the device as
possible.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
APPLICATION INFORMATION
clock interfacing
To facilitate the generation of high-frequency clock signals, CLK and CLK are designed to accept differential
signals that can be generated with 5-V (single-supply) ECL logic. Due to noise margins of the CMOS process,
CLK and CLK must be differential signals. Connecting a single-ended clock signal to CLK and connecting CLK
to GND does not work. CLK and CLK require termination resistors (220 Ω to V and 330 Ω to GND) that should
DD
be as close to the device as possible.
LD is typically generated by dividing the clock frequency by four (4:1 multiplexing) or five (5:1 multiplexing) and
translating the resulting signal to TTL levels. Since no phase relationship between the LD and CLK signals is
required, any propagation delay in LD caused by the divider circuitry does not affect device performance.
The pixel, overlay, sync, and blank data are latched on the rising edge of LD. LD may also be used as the shift
clock for the video DRAMs. In short, LD provides the fundamental timing for the video system.
The Bt438 clock generator (from Brooktree) is recommended for generating the CLK, CLK, LD, and REF
signals. It supports both 4:1 and 5:1 multiplexing. Alternately, the Bt438 can interface the device to a TTL clock.
Figure 5 illustrates the interconnection between the Bt438 and the device.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
microprocessor-unit (MPU) interface
As shown in the functional block diagram, the MPU has direct access to the internal control registers and color
overlay palettes via a standard MPU interface. Since the palette-RAM and overlay registers have dual ports,
they can be updated without affecting the display refresh process. One port is allocated for updating or reading
data and the other for display.
palette-RAM write or read
The palette-RAM location is addressed by the internal 8-bit address register (ADDR0–ADDR7). The MPU can
either write to or read from this register. The register eliminates the need for external address multiplexers.
ADDR0–ADDR7 are updated via D0–D7. To address the red, green, and blue part of a particular RAM location,
the internal address register is provided with two additional bits, ADDRa and ADDRb. These address bits count
modulo 3 and are reset to 0 when the MPU accesses the internal-address register.
After writing to or reading from the internal-address register, the MPU executes three write or read cycles (red,
green, and blue). The register ADDRab is incremented after each of these cycles so that the red, green, and
blue information is addressed from the correct part of the particular RAM location. During the blue write cycle,
the red, green, and blue color information is adjoined to form a 24-bit word, which is then written to the particular
RAM location. After the blue write/read cycle, the internal address register bits ADDR0–ADDR7 are
incremented to access the next RAM location. For an entire palette-RAM write or read, the bits ADDR0–ADDR7
are reset to 00 after accessing the FF (256) palette-RAM location.
Two additional control bits, C0 and C1, are used to differentiate the palette-RAM read/write function from other
operations that utilize the internal-address register. C0 and C1 are respectively set high and low for writing to
or reading from the palette RAM. Table 1 summarizes this differentiation, along with other internal-
address-register operations. C0 and C1 are each set low for writing to or reading from the internal-address
register.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
Table 1. Writing to or Reading From Palette RAM
R/W C1 C0 ADDRb
ADDRa
FUNCTION
L
L
L
L
L
L
L
H
H
X
L
L
X
L
Write ADDR0–ADDR7: D0–D7 → ADDR0–ADDR7; 0 → ADDRa,b
Write red color: D0–D7 → RREG; increment ADDRa,b
Write green color: D0–D7 → GREG; increment ADDRa,b
H
Write blue color: D0–D7 → BREG; increment ADDRa,b; increment ADDR0–ADDR7; write
paletteRAM
L
L
H
H
L
H
H
H
H
L
L
L
L
L
H
H
H
X
L
X
L
Read ADDR0–ADDR7: ADDR0–ADDR7 → D0–D7; 0 → ADDRa,b
Read red color: R0–R7 → D0–D7; increment ADDRa,b
L
H
L
Read green color: G0–G7 → D0–D7; increment ADDRa,b
H
Read blue color: B0–B7 → D0–D7; increment ADDRa,b; increment ADDR0–ADDR7
X = irrelevant
overlay-register write/read
With a few exceptions, the overlay-register operation is identical to the palette-RAM write/read operation (refer
to the palette-RAM write/read section). Upon writing to or reading from the internal-address register, the
additional-address register ADDRab is automatically reset to 0. ADDRab counts modulo 3 as the red, green,
and blue information is written to or read from a particular overlay register. The four overlay registers are
addressed with internal-address-register values 00–03. After writing/reading blue information, the
internal-address register bits ADDR0–ADDR7 are incremented to the next overlay location. After accessing
overlay register value 03, the internal address register does not reset to 00 but is advanced to 04.
For writing to or reading from the internal-address register, C0 and C1 are set low. When accessing the overlay
registers, C0 and C1 are set high. Refer to Table 2 for a quick reference.
Table 2. Writing to or Reading From Overlay Registers
R/W
C1
L
C0
L
ADDRb
ADDRa
FUNCTION
Write ADDR0–ADDR7: D0–D7 → ADDR0–7; 0 → ADDRa,b
Write red color: D0–D7 → RREG; increment ADDRa,b
Write green color: D0–D7 → GREG; increment ADDRa,b
L
L
L
X
L
L
X
L
H
H
H
H
H
Write blue color: D0–D7 → BREG; increment ADDRa,b; increment ADDR0–ADDR7; write
overlay register
L
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
X
L
X
L
Read ADDR0–ADDR7: ADDR0–ADDR7 → D0–D7; 0 → ADDRa,b
Read red color: R0–R7 → D0–D7; increment ADDRa,b
L
H
L
Read green color: G0–G7 → D0–D7; increment ADDRa,b
H
Read blue color: B0–B7 → D0–D7; increment ADDRa,b; increment ADDR0–ADDR7
X = irrelevant
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
control-register write/read
The four control registers are addressed with internal-address-register values 04–07. On writing to or reading
from the internal-address register, the additional address bits ADDRab are automatically reset to 0. To facilitate
read-modify-write operations, the internal-address register does not increment after writing to or reading from
the control registers. All control registers may be accessed at any time. When accessing the control registers,
C0 and C1 are respectively set low and high. Refer to Table 3 for a quick reference.
Table 3. Writing to or Reading From Control Registers
R/W
C1
L
C0
L
ADDRba
ADDRab
FUNCTION
L
X
L
X
L
X
L
X
L
Write ADDR0–ADDR7: D0–D7 → ADDR0–ADDR7; 0 → ADDRa,b
Write control register: D0–D7 → control register
L
H
L
L
H
L
Read ADDR0–ADDR7: ADDR0–ADDR7 → D0–D7; 0 → ADDRa,b
Read control register: control register → D0–D7
H
H
L
X = irrelevant
summary of internal-address-register operations
Table4providesasummaryofoperationsthatusetheinternal-addressregister. Figure1presentstheread/write
timing for the device. If an invalid address is loaded into the internal-address register, the device ignores
subsequent data from the MPU during a write operation and sends incorrect data to the MPU during a read
operation.
Table 4. Internal-Address-Register Operations
INTERNAL-ADDRESS-
REGISTER VALUE
(ADDR0–ADDR7) (HEX)
ADDRab
(COUNTS
MODULO 3)
C1
C0
MPU ACCESS
COLOR
00
01
11
Red value
Green value
Blue value
Red value
Green value
Blue value
00–FF
00–03
L
H
Color-palette RAM
00
01
110
H
H
Over color 0 to 3
04
05
06
07
H
H
H
H
L
L
L
L
Read-mask register
Blink-mask register
Command register
Test register
interruption of display-refresh pixel data (via simultaneous pixel-data retrieval and MPU write)
If the MPU is writing to a particular palette-RAM location or overlay register (during the blue cycle) and the
display-refresh process is accessing pixel data from the same RAM location or overlay register, one or more
pixels on the display screen may be disturbed. If the MPU write data is valid during the complete chip-enable
period, a maximum of one pixel is disturbed.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
frame-buffer interface and timing
An internal latch and multiplexer enables the frame buffer to send the pixel data to the device at TTL rates. On
the rising edges of LD, information for four or five consecutive pixels is latched into the device. This information
includes the palette-RAM address (up to 8 bits), the overlay-register address (up to 2 bits), and the sync and
blank information for each of the four or five consecutive pixels. The timing diagram for this pixel-data input
transfer is shown in Figure 2, along with the video output waveforms (IOR, IOG, and IOB). With this architecture,
the sync and blank timing can only be recognized with four- or five-pixel resolution.
The display-refresh process follows the first-in first-out format. Color data is output from the device in the same
order in which palette RAM and overlay addresses are input. This process continues until all four or five pixels
have been output, at which point the cycle repeats.
The overlay timing can be controlled by the pixel timing; however, this approach requires that the frame buffer
emit additional bit planes to control the overlay selection on a pixel basis. Alternately, the overlay timing can be
controlled by external-character or cursor-generation timing (see the color selection section).
No phase relationship between the LD and CLK signals is required (see Figure 2). Therefore, the LD signal can
bederivedbyexternallydividingtheCLKsignalbyfourorfive. AnypropagationdelayinLDcausedbythedivider
circuitry does not render the device nonfunctional. Regardless of the phase relationship between LD and CLK,
the pixel, overlay, sync, and blank data are latched on the rising edge of LD.
The device has an internal load signal (not brought out to a pin) that is synchronous to CLK and follows LD by
at least one and not more than four clock cycles. This internal load signal transfers the LD-latched data into a
second set of latches, which are then internally multiplexed at the pixel clock or CLK signal frequency.
For 4:1 or 5:1 multiplexing, a rising edge of LD should occur every four or five clock cycles. Otherwise, the
internal load signal generation circuitry cannot lock onto or synchronize with LD.
color selection
The read mask, blink mask, and command registers process eight bits of color information (P0–P7) and two
bits of overlay information (OL0–OL1) for each pixel every clock cycle. Control registers allow individual bit
planes to be enabled/disabled for display and/or blinked at one of four blink rates and duty cycles (see the
command register section, bits CR4–CR5).
By monitoring the BLK input to determine vertical retrace intervals, the device ensures that a color change due
to blinking occurs only during the nonactive display time. A color change does not occur in the middle of the
screen. A vertical retrace is sensed when BLK is low for at least 256 LD cycles. The color information is then
selected from the palette RAM or overlay registers in accordance with the processed input pixel data.
Table 5 presents the effect of the processed input pixel data upon color selection. P0 is the least significant bit
(LSB) of the color-palette RAM. When CR6 is high and both OL1 and OL0 are low, color information resides in
the color-palette RAM. When CR6 is low or either of the overlay inputs is high, the overlay registers provide the
DAC inputs.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
Table 5. Input Pixel Data Versus Color Selection
COMMAND-
REGISTER
BIT
OVERLAY-
SELECT
INPUT
COLOR
ADDRESS
(HEX)
COLOR
INFORMATION
CR6
OL1
OL0
P7–P0
00
01
•
H
L
L
Color palette entry 00
Color palette entry 01
H
L
•
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H
L
L
L
H
H
L
L
H
L
H
FF
XX
XX
XX
XX
Color palette entry FF
Overlay register 0
Overlay register 1
Overlay register 2
Overlay register 3
L
X
X
X
X = irrelevant
video generation
The TLC34058 presents eight bits of red, green, and blue information from either the palette RAM or overlay
registers to the three 8-bit DACs during every clock cycle. The DAC outputs produce currents that correlate to
their respective color input data. These output currents are translated to voltage levels that drive the color CRT
monitor. The SYNC and BLK signals adjust the DAC analog output currents to generate specific output levels
that are required in video applications. Table 6 shows the effect of SYNC andBLKupontheDACoutputcurrents.
Figure 3 presents the overall composite video output waveforms. Only the green output (IOG) contains sync
information.
TheDACarchitectureensuresmonotonicityandreducedswitchingtransientsbyusingidenticalcurrentsources
and routing their outputs to the DAC current output or GND. Utilizing identical current sources eliminates the
need for precision component ratios within the DAC ladder circuitry. An on-chip operational amplifier stabilizes
the DAC full-scale output current over temperature and power supply variations.
Table 6. Effects of SYNC and BLK Upon DAC Output Currents (see Note 7)
IOG
(mA)
IOR, IOB
(mA)
DAC
INPUTS
DESCRIPTION
SYNC
BLK
White
Data
26.67
data + 9.05
data + 1.44
9.05
19.05
H
H
L
H
H
H
H
H
L
FF
data
data
00
data + 1.44
Data w/o SYNC
Black
data + 1.44
1.44
1.44
0
H
L
Black w/o SYNC
Black
1.44
00
7.62
H
L
xx
SYNC
0
0
L
xx
NOTE 7: The data in this table is measured with full-scale IOG current = 26.67 mA, R
= 523 Ω,
set
V
ref
= 1.235 V.
command register
The MPU can write to or read from the command register at any time. The command register is not initialized.
CR0 corresponds to the D0 data bus line. Refer to Table 7 for a quick reference.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
24 COLOR PALETTE
256
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
Table 7. Command Register
COMMAND-
REGISTER
BIT
COMMAND-REGISTER
BIT FUNCTION
COMMAND-REGISTER BIT DESCRIPTION
CR7
Multiplex-select bit
This bit selects either 4:1 or 5:1 multiplexing for the palette RAM and overlay-register address,
low: selects 4:1 multiplexing SYNC, and BLK inputs. If 4:1 multiplexing is selected, the device ignores the E palette RAM and
high: selects 5:1 multiplexing overlay-register-address inputs. These inputs should be connected to GND, and the LD signal
frequency should be 1/4 of the clock frequency. If 5:1 is specified, all of the palette RAM and
overlay-register-address inputs are used and the LD signal should be 1/5 of the clock frequency.
CR6
RAM-enable bit
low: use overlay register 0
high: use palette RAM
When the overlay select bits (OL0 and OL1) are both low, this bit causes the DACs color
information to be selected from overlay register 0 or the palette RAM.
CR5, CR4
Blink-rate-select bits
These two bits select the blink-rate cycle time and duty cycle. The on and off numbers specify
the blink-rate cycle time as the number of vertical periods. The numbers in parentheses specify
the duty cycle in (on/off) percent.
00: 16 on, 48 off (25/75)
01: 16 on, 16 off (50/50)
10: 32 on, 32 off (50/50)
CR3
CR2
CR1
CR0
OL1 blink-enable bit
low: disable blinking
high: enable blinking
If this bit is a high, the OL1 (A–E) inputs toggle between a logic 0 and their input value at the
selected blink rate before latching the incoming pixel data. Simultaneously, command-register
CR1 must be set high. If the CR2 bit is low, the OL0 (A–E) inputs are unaffected.
OL0 blink-enable bit
low: disable blinking
high: enable blinking
If this bit is high, the OL0 (A–E) inputs toggle between a logic 0 and their input value at the
selected blink rate before latching the incoming pixel data. Simultaneously, command-register
CR0 must be set high. If the CR2 bit is low, the OL0 (A–E) inputs are unaffected.
OL1 display-enable bit
low: disable
high: enable
If this bit is low, the OL1 (A–E) inputs are forced to a logic 0 before latching the incoming pixel
data. If the CR1 bit is high, the OL1 (A–E) inputs are affected.
OL0 display-enable bit
low: disable
If this bit is low, the OL0 (A–E) inputs are forced to a logic 0 before latching the incoming pixel
data. If the CR0 bit is high, the OL0 (A–E) inputs are affected.
high: enable
read-mask register
The read-mask register is used to enable (high) or disable (low) the eight bit planes (P0–P7) within the
palette-RAM addresses. The enabling or disabling is accomplished by logic ANDing the read-mask register with
the palette-RAM address before addressing the palette RAM. Read-mask register bit 0 corresponds to data-bus
line D0. The MPU can write to or read from this register at any time. This register is not initialized.
blink-mask register
The blink-mask register is used to enable (high) or disable (low) the blinking of bit planes within the palette-RAM
addresses. For example, if blink-mask register bit n is set high, the true Pn value addresses the palette RAM
during the on portion of the blink cycle. During the off part of the blink cycle, the Pn value is replaced with a 0
before the palette RAM is addressed. The blink-rate cycle time and duty cycle is specified by command-register
bits CR4 and CR5. If blink-mask-register bit n is set low, the true Pn value always addresses the palette RAM.
Blink-mask-register bit 0 corresponds to data-bus line D0. This register is not initialized.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TLC34058-110M
256 24 COLOR PALETTE
×
SGLS075 – JANUARY 1994
PRINCIPLES OF OPERATION
test register
The test register allows the MPU to read the inputs to the DAC for diagnostic purposes. The MPU can write to
or read from this register at any time. This register is not initialized. Only the four least significant bits can be
written to, while all eight bits can be read. Test-register bit 0 corresponds to data-bus line D0. A function
description of this register is presented in Table 8.
Table 8. Functional Description of Test Register
TR3–TR0
0100
D4–D7
FUNCTION
4 MSBs of blue data input
4 MSBs of green data input
4 MSBs of red data input
4 LSBs of blue data input
4 LSBs of green data input
4 LSBs of red data input
0010
MPU read or write D0–D3
0001
1100
1010
MPU read D0–D7
1001
To read the DAC inputs, the MPU must first load the test register four least significant bits. One of the test register
bits, b0 (red DAC), b1 (green DAC), or b2 (blue DAC), must be set high and the other two bits low. This process
determines whether the inputs to the red, green, or blue DAC are read. The test register bit b3 must be set high
for reading the four most significant DAC inputs or low for reading the four least significant inputs. The MPU then
readsthetestregisterwhilethetestregister’sfourleastsignificantbitscontainthepreviouslywritteninformation.
Either the device clock must be slowed down to the MPU cycle time or the same pixel and overlay data must
be continuously presented to the device during the entire MPU read cycle.
Printed in U.S.A.
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SGLS075
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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