TLC34075_技术文档

TLC34075

Video Interface Palette

Data Manual

SLAS044A

January 1994

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to or to discontinue

any semiconductor product or service identified in this publication without notice.

TI advises its customers to obtain the latest version of the relevant information to

verify, before placing orders, that the information being relied upon is current.

TI warrants performance of its semiconductor products to current specifications

in accordance with TI’s standard warranty. Testing and other quality control

techniques are utilized to the extent TI deems necessary to support this warranty.

Unless mandated by government requirements, specific testing of all parameters

of each device is not necessarily performed.

TI assumes no liability for TI applications assistance, customer product design,

software performance, or infringement of patents or services described herein.

Nor does TI warrant or represent that license, either express or implied, is granted

under any patent right, copyright, mask work right, or other intellectual property

right of TI covering or relating to any combination, machine, or process in which

such semiconductor products or services might be or are used.

Texas Instruments products are not intended for use in life-support appliances,

devices, or systems. Use of a TI product in such applications without the written

consent of the appropriate TI officer is prohibited.

D3643, MAY 1991

Printed in the U.S.A.

Contents

Section

Title

Page

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

2.2 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.1 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.2 Color Palette RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2.2.1 Writing to the Color Palette RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.2.2 Reading From the Color Palette RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.2.3 Palette Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.3 Input/Output Clock Selection and Generatio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2.3.1 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2.3.2 VCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2.4 Multiplixing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

2.4.1 VGA Pass-Through Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

2.4.2 Multiplexing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

2.4.3 True Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

2.4.4 Special Nibble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

2.4.5 Multiplex Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8

2.4.6 Read Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.5.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.5.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.5.4 VGA Pass-Through Mode Default Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

2.6 Frame Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

2.7 Analog Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

2.8 HSYNC, VSYNC, and BLANK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

2.9 Split Shift Register Transfer VRAMs and Special Nibble Mode . . . . . . . . . . . . . . . . . . 2–14

2.9.1 Split Shift Register Transfer VRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

2.9.2 Special Nibble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

2.10 MUXOUT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

2.11 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

2.11.1 HSYNCOUT and VSYNCOUT (Bits 0 and 1) . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2.11.2 Split Shift Register Transfer Enable (SSRT) and Special Nibble Mode

Enable (SNM) (Bits 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

1

Contents (Continued)

Section

Title

Page

2.11.3 Pedestal Enable Control (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2.11.4 Sync Enable Control (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2.11.5 MUXOUT (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2.12 Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

2.12.1 Frame Buffer Data Flow Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

2.12.2 Identification Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

2.12.3 Ones Accumulation Screen Integrity Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

2.12.4 Analog Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

3.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

(Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

3.4 Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

3.5 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4

3.6 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

TL34075-66, TLC34075-85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

TL34075-110, TLC34075-135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6

3.7 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

Appendix A SCLK/VCLK and the TMS340x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Appendix B PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1

Appendix C SCLK Frequency < VCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1

Appendix D Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–1

2

List of Illustrations

Figure

Title

Page

1–1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

1–2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

2–1 DOTCLK/VCLK/SCLK Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

2–2 SCLK/VCLK Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

2–3 SCLK/VCLK Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

2–4 SCLK/VCLK Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

2–5 SCLK/VCLK Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7

2–6 Equivalent Circuit of the IOG Current Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12

2–7 7.5-IRE, 8-Bit Composite Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

2–8 0-IRE, 8-Bit Composite Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

2–9 Relationship Between SFLAG/NFLAG, BLANK, and SCLK . . . . . . . . . . . . . . . . . . . . . . 2–15

2–10 SFLAG/NFLAG Timing in Special Nibble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

2–11 Test Register Control Word State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

2–12 Internal Comparator Circuitry for Analog Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

3–1 MPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7

3–2 Video Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

3–3 SFLAG/NFLAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8

B–1 Typical Connection Diagram and Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App B

B–2 Typical Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App B

B–3 Typical Split Power Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App B

C–1 VCLK and SCLK Phase Relationship (Case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App C

C–2 VCLK and SCLK Phase Relationship (Case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . App C

List of Tables

Table

Title

Page

2–1 Internal Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

2–2 Allocation of Palette Page Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

2–3 Input Clock Selection Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

2–4 Output Clock Selection Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2–5 VCLK/SCLK Divide Ratio Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

2–6 Mode and Bus Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9

2–7 Pixel Data Distribution in Special Nibble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

2–8 General Control Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

2–9 Test Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

2–10 Test Register Bit Definitions for Analog Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

2–11 D<7:4> Bit Coding for Analog Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

3

4

1 Introduction

The TLC34075 Video Interface Palette (VIP) is designed to provide lower system cost with a higher level

of integration by incorporating all the high-speed timing, synchronizing, and multiplexing logic usually

associated with graphics systems into one device, thus greatly reducing chip count. Since all high-speed

signals (excluding the clock source) are contained on-chip, RF noise considerations are simplified.

Maximum flexibility is provided through the pixel multiplexing scheme, which allows for 32-, 16-, 8-, and 4-bit

pixel buses to be accommodated without any circuit modification. This enables the system to be easily

reconfigured for varying amounts of available video RAM. Data can be split into 1, 2, 4, or 8 bit planes. The

TLC34075 is software-compatible with the INMOS IMSG176/8 and Brooktree BT476/8 color palettes.

The TLC34075 features a separate VGA bus that allows data from the feature connector of most

VGA-supported personal computers to be fed directly into the palette without the need for external data

multiplexing. This allows a replacement graphics board to remain downward compatible by utilizing the

existing graphics circuitry often located on the motherboard. The TLC34075 also provides a true color mode

in which 24 (3 by 8) bits of color information are transferred directly from the pixel port to the DACs. This

mode of operation supplies an overlay function using the 8 remaining bits of the pixel bus.

The TLC34075 has a 256-by-24 color lookup table with triple 8-bit video D/A converters capable of directly

driving a doubly terminated 75-Ω line. Sync generation is incorporated on the green output channel. HSYNC

and VSYNC are fed through the device and optionally inverted to indicate screen resolution to the monitor.

A palette page register provides the additional bits of palette address when 1, 2, or 4 bit planes are used.

This allows the screen colors to be changed with only one MPU write cycle.

Clocking is provided through one of four or five inputs (3 TTL- and either 1 ECL- or 2 TTL-compatible) and

is software selectable. The video and shift clock outputs provide a software-selected divide ratio of the

chosen clock input.

The TLC34075 can be connected directly to the serial port of VRAM devices, eliminating the need for any

discrete logic. Support for split shift register transfers is also provided.

1.1 Features

•

Versatile multiplexing interface allows lower pixel bus rate

High level of integration provides lower system cost and complexity

Direct VGA pass-through capability

Directly interfaces to TMS34010/TMS34020 and other graphics processors

Triple 8-bit D/A converters

66-, 85-, 110-, and 135-MHz versions

256-word color palette RAM

Palette page register

On-chip voltage reference

RS-343A-compatible outputs

TTL-compatible inputs

Standard MPU interface

Pixel word mask

On-chip clock selection

True color (direct addressing) mode

Directly interfaces to video RAM

Supports split shift register transfers

Software downward-compatible with INMOS IMSG176/8 and Brooktree BT476/8 color palettes

1–1

•

TIGA -software-standard compatible

LinEPIC 1-µm CMOS process

1.2 Functional Block Diagram

LinEPIC and TIGA are trademarks of Texas Instruments Incorporated.

1–2

1.3 Terminal Assignments

11 10 9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

P17

P16

P15

P14

P13

P12

P11

P10

P9

P8

P7

P6

P5

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

CLK3

VGA7

VGA6

VGA5

VGA4

VGA3

VGA2

VGA1

VGA0

8/6

MUXOUT

SFLAG/NFLAG

VGABLANK

BLANK

VSYNC

HSYNC

P4

P3

P2

P1

P0

V

DD

WR

RD

RS0

GND

V

DD

GND

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Figure 2. Terminal Assignments

1.4 Ordering Information

TLC34075

–

(X)XX

FN

Pixel clock frequency indicator

MUST CONTAIN TWO OR THREE CHARACTERS:

–66:

–85:

66-MHz pixel clock

85-MHz pixel clock

–110: 110-MHz pixel clock

–135: 135-MHz pixel clock

Package

MUST CONTAIN TWO LETTERS:

FN: plastic, square, leaded chip carrier (formed leads)

1–4

1.5 Terminal Functions

PIN NAME

NO.

I/O

DESCRIPTION

BLANK,

60, 61

I

Blanking inputs. Two blanking inputs are provided in order to remove any

external multiplexing of the signals that may cause data and blank to skew.

When the VGA pass-through mode is set in the mux control register, the

VGABLANK input is used for blanking; otherwise, BLANK is used.

VGABLANK

CLK<0:2>

77, 76, 75

74, 73

I

Dot clock inputs. Any of the three clocks can be used to drive the dot clock

at frequencies up to 85 MHz. When VGA pass-through mode is active, CLK0

is used by default.

CLK3, CLK3

Dual-mode dot clock input. This input is an ECL-compatible input, but a TTL

clock may be used on either CLK3 or CLK3 if so selected in the input clock

selection register. This input may be selected as the dot clock for any

frequencyofoperationuptothedevicelimitwhileintheECLmode;itmayonly

be used up to 85 MHz in the TTL mode.

COMP

52

I

Compensation input. This terminal provides compensation for the internal

reference amplifier. A resistor and ceramic capacitor are required between

this terminal and V . The resistor and capacitor must be as close to the

DD

device as possible to avoid noise pickup. Refer to Appendix B for more

details.

D<0:7>

36–43

I/O

I

MPU interface data bus. Used to transfer data in and out of the register map

and palette/overlay RAM.

FS ADJUST

GND

51

Full-scale adjustment pin. A resistor connected between this pin and ground

controls the full-scale range of the DACs.

44, 54,

56, 80

Ground. All GND pins must be connected. The analog and digital GND pins

are connected internally.

HSYNCOUT,

VSYNCOUT

46, 47

O

I

Horizontal and vertical sync outputs of the true/complement gate mentioned

in the HSYNC, VSYNC description below (see Section 2.8).

HSYNC, VSYNC 58, 59

Horizontal and vertical sync inputs. These signals are used to generate the

sync level on the green current output. They are active-low inputs for the

normal modes and are passed through a true/complement gate. For the VGA

pass-through mode, they are passed through to HSYNCOUT and

VSYNCOUT without polarity change as specified by the control register (see

Section 2.8).

IOR, IOG, IOB

MUXOUT

48, 49, 50

O

Analog current outputs. These outputs can drive a 37.5-Ω load directly

(doubly terminated 75-Ω line), thus eliminating the need for any external

buffering.

63

MUX output control. This output pin is software programmable. It is set low

to indicate to external devices that VGA pass-through mode is being used

whentheMUXcontrolregistervalueissetto2Dh. Ifbit7ofthegeneralcontrol

register is set high after the mode is set, this output goes high. This pin is only

used for external control; it affects no internal circuitry.

P<0:31>

RD

29–1,

84–82

I

Pixel input port. This port can be used in various modes as shown in the MUX

controlregister. Itisrecommendedthatunusedpinsbetiedtogroundtolower

the device’s power consumption.

31

Read strobe input. A low logic level on this pin initiates a read from the

TLC34075 register map. Reads are performed asynchronously and are

initiated on the falling edge of RD (see Figure 3–1).

RS<0:3>

SCLK

32–35

I

Register select inputs. These pins specify the location in the register map that

is to be accessed, as shown in Table 2–1.

79

O

Shift clock output. This output is selected as a submultiple of the dot clock

input. SCLK is gated off during blanking.

1–5

PIN NAME

NO.

I/O

DESCRIPTION

SFLAG/NFLAG

62

I

Split shift register transfer flag or nibble flag input. This pin has two functions.

When the general control register bit 3 = 0 and bit 2 = 1, split shift register

transfer function is enabled and a low-to-high transition on this pin during a

blank sequence initiates an extra SCLK cycle to allow a split shift register

transfer in the VRAMs. When the general control register bit 3 = 1 and

bit2 = 0, special nibble mode is enabled and this input is sampled at the falling

edge of VCLK. A high value sampled indicates that the next SCLK rising edge

should latch the high nibble of each byte of the pixel data bus; a low value

sampledindicates that the low nibble of each byte of the pixel data bus should

be latched (see Section 2.9). When the general control register bit 3 = 0 and

bit 2 = 0, this pin is ignored. The condition of bit 3 = 1, bit 2 = 1 is not allowed,

and device operation is unpredictable if they are so set.

VCLK

78

O

I

Video clock output. User-programmable output for synchronization of the

TLC34075 to a graphics processor.

V

DD

45, 55,

57, 81

Power. All V

DD

pins must be connected. The analog and digital V

connected internally.

pins are

DD

VGA<0:7>

65–72

VGA pass-through bus. This bus can be selected as the pixel bus for VGA

pass-through mode. It does not allow for any multiplexing.

V

REF

53

Voltage reference for DACs. An internal voltage reference of nominally

1.235 V is designed in. A 0.1-µf ceramic capacitor between this terminal and

GNDisrecommendedfornoisefilteringusingeithertheinternaloranexternal

reference voltage. The internal reference voltage can be overridden by an

externally supplied voltage. The typical connection is shown in Appendix B.

WR

8/6

30

64

I

Writestrobeinput.AlowlogiclevelonthispininitiatesawritetotheTLC34075

register map. Write transfers are asynchronous. The data written to the

register map is latched on the rising edge of WR (see Figure 3–1).

DAC resolution selection. This pin is used to select the data bus width (8 or

6 bits) for the DACs and is provided to maintain compatibility with the INMOS

IMSG176/8 color palette. When this pin is at a high logic level, 8-bit bus

transfersareused, withD<7>beingtheMSBandD<0>theLSB. For6-bitbus

operation, while the color palette still has the 8-bit information, D<5> shifts to

the bit 7 position, D<0> shifts to the bit 2 position, and the two LSBs are filled

with zeros at the output MUX to the DAC. When read in the 6-bit mode, the

palette-holding register zeroes out the two MSBs.

NOTES: 1. Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground

lowers power consumption and, thus, is recommended.

2. All digital inputs and outputs are TTL-compatible, unless otherwise noted.

1–6

2 Detailed Description

2.1 MPU Interface

The processor interface is controlled via read and write strobes (RD, WR), four register select pins

(RS<0:3>), and the 8/6 select pin. The 8/6 select pin is used to select between 8- or 6-bit operation and is

provided in order to maintain compatibility with the IMSG176/8 color palette. This operation is carried out

in order to utilize the maximum range of the DACs.

The internal register map is shown in Table 1. The MPU interface operates asynchronously, with data

transfers being synchronized by internal logic. All the register locations support read and write operations.

Table 1. Internal Register Map

RS3 RS2 RS1 RS0

REGISTER ADDRESSED BY MPU

Palette address register – write mode

Color palette holding register

Pixel read mask

L

H

L

H

L

H

L

Palette address register – read mode

Reserved

L

H

L

H

L

Reserved

L

H

L

Reserved

L

H

L

Reserved

H

General control register

Input clock selection register

Output clock selection register

Mux control register

Palette page register

Reserved

L

H

L

H

L

H

L

H

L

H

L

H

Test register

H

Reset state

2.2 Color Palette RAM

The color palette RAM is addressed by two internal 8-bit registers, one for reading from the RAM and one

for writing to the RAM. These registers are automatically incremented following a RAM transfer, allowing

the entire palette to be read/written with only one access of the address register. When the address register

increments beyond the last location in RAM, it is reset to the first location (address 0). Although all read and

write accesses to the RAM are asynchronous to SCLK, VCLK, and the dot clock, they are performed within

one dot clock and so do not cause any noticeable disturbance on the display.

The color palette RAM is 24 bits wide for each location (8 bits each for red, green, and blue). If 6-bit mode

is chosen (8/6 = low), the two MSBs are still written to the color palette RAM. However, if they are read back

in the 6-bit mode, the two MSBs are set to 0 to maintain compatibility with the IMSG176/8 and BT476/8 color

palettes. The output MUX shifts the six LSBs to the six MSB positions, fills the two LSBs with 0s, then feeds

the eight bits to the DAC. With the 8/6 pin held low, data on the lowest six bits of the data bus are internally

shifted up by two bits to occupy the upper six bits at the output MUX, and the bottom two bits are then zeroed.

The test register and the ones accumulation register both take data before the output MUX to give the user

the maximum flexibility.

The color palette RAM access methodology is described in the following two sections and is fully compatible

with the IMSG176/8 and BT476/8 color palettes.

2–1

2.2.1 Writing to the Color Palette RAM

To load the color palette RAM, the MPU must first write to the address register (write mode) with the address

where the modification is to start. This action is followed by three successive writes to the palette-holding

register with eight bits each of red, green, and blue data. After the blue data write cycle, the three bytes of

color are concatenated into a 24-bit word and written to the color palette RAM location specified by the

address register. The address register then increments to point to the next color palette RAM location, which

the MPU may modify by simply writing another sequence of red, green, and blue data bytes. A block of color

values in consecutive locations may be written to by writing the start address and performing continuous

red, green, and blue write cycles until the entire block has been written.

2.2.2 Reading From the Color Palette RAM

Reading from the color palette RAM is performed by writing the location to be read to the address register.

This action initiates a transfer from the color palette RAM into the holding register followed by an increment

of the address register. Three successive MPU reads from the holding register produce red, green, and blue

color data (six or eight bits, depending on the 8/6 mode) for the specified location. Following the blue read

cycle, the contents of the color palette RAM at the address specified by the address register are copied into

the holding register and the address register is again incremented. As with writing to the color palette RAM,

a block of color values in consecutive locations may be read by writing the start address and performing

continuous red, green, and blue read cycles until the entire block has been read.

2.2.3 Palette Page Register

The 8-bit palette page register provides high-speed color changing by removing the need for color palette

RAM reloading. When using 1, 2, or 4 bit planes, the additional planes are provided by the palette page

register; e.g., when using four bit planes, the pixel inputs specify the lower four bits of the color palette RAM

address with the upper four bits being specified by the palette register. This provides the capability of

selecting from 16 palette pages with only one chip access, thus allowing all the screen colors to be changed

at the line frequency. A bit-to-bit correspondence is used; therefore, in the above configuration, palette page

register bits 7 through 4 map onto color palette RAM address bits 7 through 4, respectively. This is illustrated

below.

NOTE: The additional bits from the palette page register are inserted before the read mask and hence, are

subject to masking.

Table 2. Allocation of Palette Page Register Bits

NUMBER OF

BIT PLANES

COLOR PALETTE RAM ADDRESS BITS

msb

M

isb

M

8

4

2

1

M

P7

P6

P5

P4

M

P3

P2

M

P1

M

Pn = nth bit from palette page register

M = bit from pixel port

2.3 Input/Output Clock Selection and Generation

The TLC34075 provides a maximum of five clock inputs. Three are dedicated to TTL inputs; the other two

can be selected as either one ECL input or two extra TTL inputs. The TTL inputs can be used for video rates

up to 85 MHz, above which an ECL clock source must be used (although the ECL clock may also be used

at lower frequencies). The dual-mode clock input (ECL/TTL) is primarily an ECL input but can be used as

a TTL-compatible input if the input clock selection register is so programmed. The clock source used at

power-up is CLK0; an alternative source can be selected by software during normal operation. This chosen

clock input is used unmodified as the dot clock (representing the pixel rate to the monitor). The device does,

2–2

however, allow for user programming of the SCLK and VCLK outputs (shift and video clocks) via the output

clock selection register. The input/output clock selection registers are shown in Tables 5, 6, and 7.

SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals such

as BLANK and the SYNCs. While SCLK and VCLK are designed as general-purpose shift clock and video

clock, respectively, they also interface directly with the TMS340x0 GSP family. While SCLK and VCLK can

be selected independently, there is still a relationship between the two. Internally, both SCLK and VCLK are

generated from a common clock counter that increments on the rising edge of the DOTCLK. When VCLK

is enabled and the VCLK and SCLK frequencies are programmed to be the same submultiple of the

DOTCLK frequency, then VCLK and SCLK are in phase. When VCLK is enabled and the VCLK and SCLK

frequencies are programmed to be different submultiples of the DOTCLK frequency, then there are

simultaneous rising edges on the two waveforms at times determined by their frequency ratio

(see Figure 3).

Appendix A discusses the SCLK/VCLK relationship specific to the TMS340x0 GSP.

DOTCLK

VCLK

(DOTCLK/4

as an example)

SCLK

(DOTCLK/2

as an example)

Figure 3. DOTCLK/VCLK/SCLK Relationship

Table 3. Input Clock Selection Register Format

†

BITS

‡

FUNCTION

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

§

Select CLK0 as clock source

Select CLK1 as clock source

Select CLK2 as clock source

Select CLK3 as TTL clock source

Select CLK3 and CLK3 as ECL clock sources

†

‡

Register bits 4, 5, 6, and 7 are don’t care bits.

When the clock selection is altered, a minimum 30-ns delay is incurred before the

new clocks are stabilized and running.

§

CLK0 is chosen at power-up to support the VGA pass-through mode.

2–3

Table 4. Output Clock Selection Register Format

†

BITS

‡

FUNCTION

5

0

1

X

4

0

1

0

1

X

3

2

1

X

0

1

0

1

0

X

0

1

X

0

1

VCLK frequency = DOTCLK frequency

VCLK frequency = DOTCLK frequency/2

VCLK frequency = DOTCLK frequency/4

VCLK frequency = DOTCLK frequency/8

VCLK frequency = DOTCLK frequency/16

VCLK frequency = DOTCLK frequency/32

VCLK output held at logic high level (default condition)

SCLK frequency = DOTCLK frequency

SCLK frequency = DOTCLK frequency/2

SCLK frequency = DOTCLK frequency/4

SCLK frequency = DOTCLK frequency/8

SCLK frequency = DOTCLK frequency/16

SCLK frequency = DOTCLK frequency/32

0

1

0

1

§

X

1

0

1

0

1

§

SCLK output held at logic level low (default condition)

X

†

‡

Register bits 6 and 7 are don’t care bits.

When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are

stabilized and running.

§

These lines indicate the power-up conditions required to support the VGA pass-through mode.

Table 5. VCLK/SCLK Divide Ratio Selection

(Output Clock Selection Register Value in Hex)

SCLK

BITS

2. . . 0

000

1

001

2

010

4

011

8

100

16

101

32

¶

VCLK

divide DOTCLK by

divide

BITS

5. . .3

¶

DOTCLK

by

000

001

010

011

100

101

1

2

00

08

10

18

20

28

01

09

11

19

21

29

02

0A

12

1A

22

2A

03

0B

13

1B

23

2B

04

0C

14

1C

24

2C

05

0D

15

1D

25

2D

4

8

16

32

¶

Output clock selection register bits

2.3.1 SCLK

The TLC34075 latches data on the rising edge of the LOAD signal (LOAD is the same as SCLK but is not

disabled while the BLANK signal is active). Therefore, SCLK must be set as a function of the pixel bus width

and the number of bit planes. The SCLK frequency can be selected to be the same as the dot clock

frequency or 1/2, 1/4, 1/8, 1/16, or 1/32 of the dot clock frequency. If SCLK is not used, the output is switched

off and held low to protect against VRAM lock-up due to invalid SCLK frequencies. SCLK is also held low

during the BLANK signal active period. The control timing has been designed to bring the first pixel data

ready from the VRAM when BLANK is disabled and ready for the display. When split shift register transfer

operation is used, SCLK is taken care of by working with SSRT input (see Section 2.9).

Refer to Figure 2–2 for the following timing explanation.

2–4

The falling edge of VCLK is used internally by the TLC34075 to sample and latch the BLANK input level.

When BLANK goes low, SCLK is disabled as soon as possible. In other words, if the last SCLK pulse is at

the high level while the sampled BLANK is low, SCLK is allowed to finish its cycle to low level, then SCLK

is held low until the sampled BLANK goes back high to enable it again. The VRAM shift register should be

updated during the BLANK active period, and the first SCLK pulse is used to clock the first valid pixel data

from the VRAM. The internal pipeline delay of the BLANK input is designed to be in phase with data at the

DAC output to the monitors. The logic described above works in situations wherein the SCLK period is

shorter than, equal to, or longer than the VCLK period.

Figure5 shows the case wherein the SSRT (split shift register transfer) function is enabled. One SCLK pulse

with a minimum width of 15 ns is generated from the rising edge at the SFLAG input with specified delay.

This is designed to meet the VRAM timing requirement, and this SCLK pulse replaces the first SCLK in the

regular shift register transfer case as described above. Refer to Section 2.9 for the detailed explanation of

the SSRT function.

The SCLK output waveform may vary at the time that the sampled BLANK input is low. Refer to Appendix C

for details.

2.3.2 VCLK

The VCLK frequency can be selected to be 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 of that of the dot clock, or it can

be held at a high logic level. The default condition is for VCLK to be held at a high logic level. VCLK is not

used in VGA pass-through mode.

VCLK is used by a GSP or custom-designed control logic to generate control signals (BLANK, HSYNC, and

VSYNC). As can be seen from Figures 4, 5, 6, and 7, since the control signals are sampled by VCLK, it is

obvious that VCLK has to be enabled.

VCLK

BLANK

at Input Pin

Latch Last Group

of Pixel Data

Latch First Group

of Pixel Data

Latch Last Group

of Pixel Data

LOAD

(Internal Signal

for Data Latch)

BLANK

(Internal Signal

Before DOTCLK

Pipeline Delay)

2nd

4th

Group

1st

Group

3rd

5th

6th

Group

Last Group of Pixel Data

PIXEL DATA

at Input Pin

SCLK

NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low

if the SSRT function is enabled (general control register bit 2 = 1).

Figure 4. SCLK/VCLK Control Timing (SSRT Disabled,

SCLK Frequency = VCLK Frequency)

2–5

VCLK

BLANK

at Input Pin

SFLAG/NFLAG

Latch Last Group

of Pixel Data

Latch First Group

of Pixel Data

Latch Last Group

of Pixel Data

LOAD

(Internal Signal

for Data Latch)

BLANK

(Internal Signal

Before DOTCLK

Pipeline Delay)

3rd

Group

5th

Group

2nd

Group

4th

Group

6th

Group

Last

Group

1st Group of Pixel Data

PIXEL DATA

at Input Pin

SCLK Between Split Shift Register Transfer

and Regular Shift Register Transfer

SCLK

NOTE:The SSRT function is enabled (general control register bit 2 = 1).

Figure 5. SCLK/VCLK Control Timing (SSRT Enabled,

SCLK Frequency = VCLK Frequency)

VCLK

BLANK

at Input Pin

Latch Last Group

of Pixel Data

Latch First Group

of Pixel Data

LOAD

(Internal Signal

for Data Latch)

BLANK

(Internal Signal

Before DOTCLK

Pipeline Delay)

2nd

Group

4th

6th

Group

1st

Group

3rd

5th

Group

PIXEL DATA

at Input Pin

Last Group of Pixel Data

SCLK

Figure 6. SCLK/VCLK Control Timing (SSRT Disabled,

SCLK Frequency = 4 × VCLK Frequency)

2–6

NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low

if the SSRT function is enabled (general control register bit 2 = 1).

VCLK

BLANK

at Input Pin

SFLAG/NFLAG

Latch Last Group

of Pixel Data

Latch First Group

of Pixel Data

LOAD

(Internal Signal

for Data Latch)

BLANK

(Internal Signal

Before DOTCLK

Pipeline Delay)

3rd

Group

5th

Group

2nd

Group

4th

Group

6th

Group

Last

Group

PIXEL DATA

at Input Pin

1st Group of Pixel Data

SCLK Between Split Shift Register

and Regular Shift Register Transfer

SCLK

Figure 7. SCLK/VCLK Control Timing (SSRT Enabled,

SCLK Frequency = 4 × VCLK Frequency)

2.4 Multiplexing Scheme

The TLC34075 offers a highly versatile multiplexing scheme as illustrated in Table 6. The on-chip

multiplexing allows the system to be reconfigured to the amount of RAM available. For example, if only

256K bytes of memory are available, an 800-by-600 mode with 4 bit planes (four bits per pixel) could be

implemented using an 8-bit-wide pixel bus. If, at a later date, another 256K bytes are added to another eight

bits of the pixel bus, the user has the option of using 8 bit planes at the same resolution or 4 bit planes at

a 1024-by-768 resolution. When an additional 512K bytes is added to the remaining 16 bits of the pixel bus,

the user has the option of 8 bit planes at 1024-by-768 or 4 bit planes at 1280 by 1024. All the above can

be achieved without any hardware modification and without any increase in the speed of the pixel bus.

2.4.1 VGA Pass-Through Mode

Mode 0, the VGA pass-through mode, is used to emulate the VGA modes of most personal computers. The

advantage of this mode is that the TLC34075 can take data presented on the feature connectors of most

VGA-compatible PC systems into the device on a separate bus, thus requiring no external multiplexing. This

feature is particularly useful for systems in which the existing graphics circuitry is on the motherboard. In

this instance, it enables implementation of a drop-in graphics card that maintains compatibility with all

existing software by using the on-board VGA circuitry but routing the emerging bit-plane data through the

TLC34075. This is the default mode at power-up. When the VGA pass-through mode is selected after the

device is powered up, the clock selection register, the general control register, and the pixel read mask

register are set to their default states automatically.

Since this mode is designed with the feature connector philosophy, all the timing is referenced to CLK0,

which is used by default for VGA pass-through mode. For all the other normal modes, CLK <0:3> are the

oscillator sources for DOTCLK, VCLK, and SCLK; all the data and control timing is referenced to SCLK.

2–7

2.4.2 Multiplexing Modes

In addition to the VGA pass-through mode, there are four multiplexing modes available, all of which are

referred to as normal modes. In each normal mode, a pixel bus width of 8, 16, or 32 bits may be used. Modes

1, 2, and 3 also support a pixel bus width of 4 bits. Data should always be presented on the least significant

bits of the pixel bus. For example, when a 16-bit-wide pixel bus is used and there are 8 bits per pixel, each

8-bit pixel should be presented on P<0:7>. All the unused pixel bus pins should be connected to GND.

Mode 1 uses a single bit plane to address the color palette. The pixel port bit is fed into bit 0 of the palette

address, with the 7 high-order address bits being defined by the palette page register (see Section 2.2.3).

This mode has uses in high-resolution monochrome applications such as desktop publishing. This mode

allows the maximum amount of multiplexing (a 32:1 ratio), thus giving a pixel bus rate of only 4 MHz at a

screen resolution of 1280 by 1024. Although only a single bit plane is used, alteration of the palette page

register at the line frequency allows 256 different colors to be displayed simultaneously with 2 colors per

line.

Mode 2 uses 2 bit planes to address the color palette. The 2 bits are fed into the low-order address bits of

the palette with the 6 high-order address bits being defined by the palette page register (see Section 2.2.3).

This mode allows a maximum divide ratio of 16:1 on the pixel bus and is a 4-color alternative to mode 1.

Mode 3 uses 4 bit planes to address the color palette. The 4 bits are fed into the low-order address bits of

the palette with the 4 high-order address bits being defined by the palette page register (see Section 2.2.3).

This mode provides 16 pages of 16 colors and can be used at SCLK divide ratios of 1 to 8.

Mode 4 uses 8 bit planes to address the color palette. Since all 8 bits of palette address are specified from

the pixel port, the page register is not used. This mode allows dot-clock-to-SCLK ratios of 1:1 (8-bit bus),

2:1 (16-bit bus) or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024-by-768 pixel screen can be

implemented with an external data rate of only 16 MHz.

2.4.3 True Color Mode

Mode 5 is true color mode, in which 24 bits of data are transferred from the pixel port directly to the DACs

with the same amount of pipeline delay as the overlay data and the control signals (BLANK and SYNCs).

In this mode, overlay is provided by using the remaining 8 bits of the pixel bus to address the palette RAM,

resulting in a 24-bit RAM output that is then used as overlay information to the DACs. When all the overlay

inputs (P<0:7>) are at a low logic level or the pixel read mask register is loaded with the value 0, no overlay

information is displayed; when a nonzero value is input with the pixel read mask enabled, the color palette

RAM is addressed and the resulting data is then fed through to the DACs, receiving priority over the true

color data.

The true-color-mode data input only works in the 8-bit mode. In other words, if only 6 bits are used, the 2

MSB inputs for each color should be tied to GND. However, the palette, which is used by the overlay input,

is still governed by the 8/6 input pin, and the output MUX selects 8 bits of data or 6 bits of data accordingly.

In the true color mode, P<15:8> pass red data, P<23:16> pass green data, and P<31:24> pass blue data.

2.4.4 Special Nibble Mode

Mode 6 is special nibble mode, which is enabled when the general control register SNM bit (bit 3) is set to

1 and the general control register SSRT bit (bit 2) is set to 0 (see Section 2.11). When special nibble mode

is enabled, it takes precedence over the other modes, and the mux control register setup is ignored. The

SFLAG/NFLAG input is then used as a nibble flag to indicate which nibble of each byte holds the pixel data.

Special nibble mode is a variation of the 4-bit pixel mode with a 16-bit pixel width. All 32 inputs (P0 through

P31) are connected as 4 bytes, but the 16-bit data bus is composed of either the lower or upper nibble of

each of the 4 bytes. For more detailed information, refer to Section 2.9.2. Since this mode uses 4 bit planes

for each pixel, they are fed into the low-order address bits of the palette, with the 4 high-order address bits

being defined by the palette page register (see Section 2.2.3).

2.4.5 Multiplex Control Register

Themultiplexeriscontrolledviathe8-bitmultiplexcontrolregister. ThebitfieldsoftheregisterareinTable 6.

2–8

Table 6. Mode and Bus Width Selection

DATA BITS PIXEL BUS

SCLK

DIVIDE

PIXEL

LATCHING

¶

SEQUENCE

†

MODE

MUX CONTROL REGISTER BITS

PER

WIDTH

‡

§

PIXEL

RATIO

5

1

0

4

0

1

3

1

0

2

1

0

1

0

#

0

1

0

8

1

8

4

1

4

1) VGA<7:0>

1) P<0>

2) P<1>

3) P<2>

4) P<3>

0

1

0

1

0

1

8

1) P<0>

2) P<1>

8) P<7>

1

16

32

16

32

1) P<0>

2) P<1>

16) P<15>

1) P<0>

2) P<1>

32) P<31>

0

1

0

1

0

1

2

4

8

2

4

1) P<1:0>

2) P<3:2>

1) P<1:0>

2) P<3:2>

3) P<5:4>

4) P<7:6>

2

0

1

0

1

0

1

2

16

32

8

1) P<1:0>

2) P<3:2>

8) P<15:14>

16

1) P<1:0>

2) P<3:2>

16) P<31:30>

1) P<3:0>

0

1

0

1

4

8

1

2

1) P<3:0>

2) P<7:4>

0

1

0

1

0

4

16

4

1) P<3:0>

2) P<7:4>

3) P<11:8>

4) P<15:12>

3

0

1

0

1

4

32

8

1) P<3:0>

2) P<7:4>

8) P<31:28>

2–9

DATA BITS PIXEL BUS

SCLK

DIVIDE

PIXEL

LATCHING

¶

SEQUENCE

†

MODE

MUX CONTROL REGISTER BITS

PER

WIDTH

‡

§

PIXEL

RATIO

5

0

4

1

3

1

2

1

0

1

8

1

2

1) P<7:0>

16

1) P<7:0>

4

2) P<15:8>

0

1

0

8

32

4

1) P<7:0>

2) P<15:8>

3) P<23:16>

4) P<31:24>

||

5

0

1

0

1

24

4

32

16

1

4

1) P<31:8>

NFLAG = 0:

1) P<3:0>

2) P<11:8>

3) P<19:16>

4) P<27:24>

6

NFLAG = 1:

1) P<7:4>

2) P<15:12>

3) P<23:20>

4) P<31:28>

†

‡

Bits 6 and 7 are don’t care bits.

This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,

often referred to as the number of bit planes. This may be color palette address data (Modes 0–4 and 6) or DAC data

(mode 5).

§

¶

The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per

bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8

bit planes, 4 pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but must

be written to the output clock selection register.

For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are

latchedinto the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups

of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the

low-numbered group. For example, in mode 3 with a 16-bit pixel bus width, the rising edge of SCLK latches all the data

groups, and the pixel clock shifts them out in the order P<3:0>, P<7:4>, P<11:8>, P<15:12>.

Mode 0 is VGA pass-through mode.

Mode 5 is true color mode, in which 24 bits of color information are transferred directly from the pixel port to the DACs;

overlay is implemented with the remaining 8 bits of the pixel bus. The distribution of pixel port data to the DACs is as

follows: P<31:24> are passed to the blue DAC, P<23:16> are passed to the green DAC, and P<15:8> are passed to

the red DAC. P<7:0> are used to generate overlay data; this operation can be disabled by either grounding P<7:0> or

by clearing the read mask (see Section 1.4.5).

#

||

Mode 6 is special nibble mode, the only mode in which the pixel bus width is not equal to the actual physical width, in

bits, of the pixel bus. In this mode, the pixel bus is physically 32 bits wide; depending on the value of SFLAG/NFLAG,

either the upper or lower nibble of each of the four physical bytes is selected to comprise the 16 bits of pixel data (equal

to four 4-bit pixels).

NOTE:Althoughleavingunusedpinsfloatingwillnotadverselyaffectdeviceoperation,tyingunusedpinstogroundlowers

power consumption and, thus, is recommended.

2–10

As an example of how to use Table 6, suppose that the design goals specify a system with eight data bits

per pixel and the lowest possible SCLK rate. Table 6 shows that, for non-VGA-pass-through operation, only

mode 4 supports an eight-bit pixel depth. The lowest-possible SCLK rate within mode 4 is 1:4. This set of

conditions is selected by writing the value 1Eh to the mux control register. The pixel latching sequence

column shows that, in this mode, P<7:0> should be connected to the earliest-displayed pixel plane, followed

by P<15:8>, P<23:16>, and then P<31:24> as the last displayed pixel plane. Assuming that VCLK is

programmed as DOTCLK/4, Table 2–5 shows that the 1:4 SCLK ratio is selected by writing the value 12h

to the output clock selection register. The special nibble mode should also be disabled (see Sections 2.9.2

and 2.11.2).

When the mux control register is loaded with 2Dh, the TLC34075 enters the VGA pass-through mode (the

same condition as the default power-up mode). Please refer to Section 2.5.4 for more details.

2.4.6

Read Masking

The read mask register is used to enable or disable a pixel address bit from addressing the color palette

RAM. Each palette address bit is logically ANDed with the corresponding bit from the read mask register

before addressing the palette. This function is performed after the addition of the page register bits and,

therefore, a zeroing of the read mask results in one unique palette location (location 0) and is not affected

by the palette page register contents.

2.5

Reset

There are 3 ways to reset the TLC34075:

1. Power-on reset

2. Hardware reset

3. Software reset

2.5.1 Power-On Reset

TheTLC34075containsapower-onresetcircuit. Oncethevoltagelevelshavestabilizedfollowingpower-on

reset, the device is in the VGA pass-through mode.

2.5.2 Hardware Reset

The TLC34075 resets whenever RS<3:0> = HHHH and a rising edge occurs on the WR input. The more

rising WR edges occur, the more reliable the TLC34075 is reset. This scheme (bursting WR strobes until

the power supply voltage stablizes) is suggested at power-up if a hardware reset approach is used.

The default reset condition is VGA pass-through mode, and the values for each register are shown in

Section 2.5.4.

2.5.3 Software Reset

Whenever the mux control register is set for VGA pass-through mode after power-up, all registers are

initialized accordingly. Since VGA pass-through mode is the default condition at power-up and hardware

reset, the act of selecting the VGA pass-through mode through programming the mux control register is

viewed as a software reset. Therefore, whenever mux control register bits <5:0> are set to 2Dh, the

TLC34075 initiates a software reset.

2.5.4 VGA Pass-Through Mode Default Conditions

The value contained in each register after hardware or software reset is shown below:

Mux control register:

Input clock selection register:

2Dh

00h

Output clock selection register: 3Fh

Palette page register:

General control register:

00h

03h

2–11

Pixel read mask register:

Palette address register:

Palette holding register:

Test register:

FFh

xxh

(Pointing to color palette red value)

2.6

Frame Buffer Interface

The TLC34075 provides two clock signals for controlling the frame buffer interface: SCLK and VCLK. SCLK

can be used to clock out data directly from the VRAM shift registers. Split shift register transfer functionality

is also supported. VCLK is used to clock and synchronize control inputs like HSYNC, VSYNC, and BLANK.

The pixel data presented at the inputs is latched at the rising edge of SCLK in normal mode or the rising edge

of CLK0 in VGA pass-through mode. Control inputs HSYNC, VSYNC, and BLANK are sampled and latched

atthefallingedgeofVCLKinnormalmode, whileHSYNC, VSYNC, andVGABLANKarelatchedattherising

edge of CLK0 in VGA pass-through mode. Both data and control signals are lined up at the DAC outputs

to the monitors through the internal pipeline delay, so external glue logic is not required. The outputs of the

DACs are capable of directly driving a 37.5-Ω load, as in the case of a doubly terminated 75-Ω cable. See

Figures 9 and 10 for nominal output levels.

2.7

Analog Output Specifications

The DAC outputs are controlled by current sources (three for IOG and two each for IOR and IOB) as shown

in Figure 8. In the normal case, there is a 7.5-IRE difference between blank and black levels, which is shown

in Figure 9. If a 0-IRE pedestal is desired, it can be selected by resetting bit 4 of the general control register

(see Section 2.11.3). The video output for a 0-IRE pedestal is shown in Figure 10.

V

AA

IOG

R

L

15 pF

SYNC

BLANK

G <0:7>

(IOG Only)

Figure 8. Equivalent Circuit of the IOG Current Output

2–12

Red/Blue

[mA] [V]

Green

[mA] [V]

26.67 1.000 19.05 0.714

White

92.5 IRE

9.05 0.340 1.44 0.054

7.62 0.286 0.00 0.000

Black

Blank

7.5 IRE

40 IRE

0.00 0.000

Sync

Figure 9. 7.5-IRE, 8-Bit Composite Video Output

Red/Blue

[mA] [V]

Green

[mA] [V]

25.24 0.95 17.62 0.66

White

100 IRE

Black/

Blank

7.62 0.286 0.00 0.000

0.00 0.000

43 IRE

Sync

Figure 10. 0-IRE, 8-Bit Composite Video Output

NOTE: 75-Ω doubly terminated load. V

REF

= 1.235 V, R

= 523 Ω. RS-343A levels and tolerances are assumed.

SET

A resistor (R

)isneededtoconnecttheFSADJpintoGNDtocontrolthemagnitudeofthefull-scalevideo

SET

signal. The IRE relationships in Figures 9 and 10 are maintained regardless of the full-scale output current.

2–13

The relationship between R

and the full-scale output current IOG is:

SET

R

(Ω) = K1 × V

(V) / IOG (mA)

SET

REF

The full-scale output current on IOR and IOB for a given R

is:

SET

IOR, IOB (mA) = K2 × V

(V) / R

(Ω)

REF

SET

where K1 and K2 are defined as:

IOG

IOR, IOB

PEDESTAL

8-BIT OUTPUT

K1 = 11,294

K1 = 10,684

6-BIT OUTPUT

K1 = 11,206

K1 = 10,600

8-BIT OUTPUT

6-BIT OUTPUT

K2 = 7,979

7.5-IRE

0-IRE

K2 = 8,067

K2 = 7,462

K2 = 7,374

2.8

HSYNC, VSYNC, and BLANK

For the normal modes, HSYNC and VSYNC are active-low pulses, and they are passed through

true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT

and VSYNCOUT can be programmed through the general control register. However, for the VGA

pass-through mode, the polarities needed for monitors are already provided at the feature connector from

which HSYNC and VSYNC are sourced, so the TLC34075 just passes HSYNC and VSYNC through to

HSYNCOUT and VSYNCOUT without polarity change. As described in Section 2.3 and Figures 4 through

5, the BLANK, HSYNC, and VSYNC inputs are sampled and latched on the falling edge of VCLK in the

normal modes, and they are latched on the rising edge of the CLK0 input in the VGA pass-through mode.

Refer to Figure 16 for the detailed timing.

The HSYNC and VSYNC inputs are used for both the VGA pass-through and normal modes. If the

application uses both VGA pass-through and normal modes, an external multiplexer is needed to select

HSYNC and VSYNC between VGA pass-throughmodeandnormalmode. TheMUXOUTsignalisdesigned

for this purpose (see Sections 2.10 and 2.11).

The HSYNC, VSYNC, and BLANK signals have internal pipeline delays to align the data at the outputs. Due

to the sample and latch timing delay, it is possible to have active SCLK pulses after the BLANK input

becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch delay

need to be carefully reviewed and programmed. See Section 2.3 and Figures 4 and 5 for more details.

As shown in Figure 18 for the IOG DAC output, active HSYNC and VSYNC signals turn off the sync current

source (after the pipeline delay) independent of the BLANK signal level. In real applications, HSYNC and

VSYNC should only be active (low) when BLANK is active (low).

To alter the polarity of the HSYNCOUT and VSYNCOUT outputs in the normal modes, the MPU must set

or clear the corresponding bits in the general control register (see Section 2.11.1). Again, these two bits

affect only the normal modes, not the VGA pass-through mode. These bits default to 1.

2.9

Split Shift Register Transfer VRAMs and Special Nibble Mode

2.9.1 Split Shift Register Transfer VRAMs

The TLC34075 directly supports split shift register transfer (SSRT) VRAMs. In order to allow the VRAMs

to perform a split shift register transfer, an extra SCLK cycle must be inserted during the blank sequence.

This is initiated when the SSRT enable bit (bit 2 in the general control register) is set to 1, the SNM bit (bit 3

in the general control register) is reset to 0 (see Section 2.11), and a rising edge on the SFLAG/NFLAG input

pin is detected. An SCLK pulse is generated within 20 ns of the rising edge of the SFLAG/NFLAG signal.

A minimum 15-ns high logic level duration is provided to satisfy all of the –15 VRAM requirements. By

controlling the SFLAG/NFLAG rise time, the delay time from the rising edge of the VRAM TRG signal to

SCLK can be satisfied. The relationship between the SCLK, SFLAG/NFLAG, and BLANK signals is as

follows:

2–14

BLANK

SSRT Enable

(General Control

Register Bit 2)

SFLAG/NFLAG

Input

SCLK

Figure 11. Relationship Between SFLAG/NFLAG, BLANK, and SCLK

If SFLAG/NFLAG is designed as an R-S latch set by split shift register transfer timing and reset by BLANK

going high, the delay from BLANK high to SFLAG/NFLAG low cannot exceed one-half of one SCLK cycle;

otherwise, the SCLK generation logic may fail.

If the SSRT function is enabled but SFLAG/NFLAG is held low, SCLK runs as if the SSRT function is

disabled. The SFLAG/NFLAG input is not qualified by the BLANK signal and needs to be held low whenever

anSSRTSCLKpulseisnotdesired. RefertoSection2.3.1andFigures4through10formoresystemdetails.

2.9.2 Special Nibble Mode

Special nibble mode is enabled when the SNM bit (bit 3 in the general control register) is set to 1 and the

SSRT bit (bit 2 in the general control register) is reset to 0 (see Section 2.11). Special nibble mode provides

a variation of the 4-bit pixel mode with a 16-bit bus width. While all 32 inputs (P<0:31>) are connected as

4 bytes, the 16-bit data bus is composed of the lower or upper nibble of each of the 4 bytes, depending on

the level of the SFLAG/NFLAG input. The pixel data is distributed to 16-bit data bus as shown in Table 7.

Table 7. Pixel Data Distribution in Special Nibble Mode

SNM BIT = 1, SSRT BIT = 0

SFLAG/NFLAG = 1

SFLAG/NFLAG = 0

P<7:4>

P<3:0>

P<15:12>

P<23:20>

P<31:28>

P<11:8>

P<19:16>

P<27:24>

The SFLAG/NFLAG value is not latched by the TLC34075. Therefore, it should stay at the same level during

the whole active display period, changing levels only during the BLANK signal active time. Refer to

Figure 12, which is similar to Figure 4 except that the BLANK signal timing reference to SFLAG/NFLAG is

explained. The SFLAG/NFLAG input has to meet the setup time and hold the data long enough to ensure

that no pixel data is missed.

Special nibble mode operates at the line frequency when BLANK is active. However, the typical application

of this mode is double frame buffers with pixel data width of 4 bits. While one frame buffer is being displayed

onthemonitor, theotherframebuffercanbeusedtoacceptnewpictureinformation. SFLAG/NFLAGisused

to indicate which frame buffer is being displayed.

SNM and SSRT must be mutually exclusive. Unpredictable operation occurs if both the SNM and SSRT bits

are set to 1. The mux control register should be set up as shown in Table 6 (see Section 2.4.5). However,

the SNM bit takes precedence over the other mux control register selections. In other words, if the mux

control register is set up for another mode but special nibble mode is still enabled in the general control

register, the input multiplex circuit takes whatever SCLK divide ratio the mux control register specifies and

performs the nibble operation, causing operational failure.

2–15

During special nibble mode, the input mux circuit latches all 8-bit inputs but only passes on the specified

nibble. The specified nibble is stored in the 4 LSBs of the next register pipe after the input latch, and the

4 MSBs are zeroed in that register. The register pipe contents are then passed to the read mask block. With

this structure, the palette page register still functions normally, providing good flexibility to users.

If the general control register bit 3 = 0 and bit 2 = 0, both split shift register transfers and special nibble mode

are disabled and the SFLAG/NFLAG input is ignored.

VCLK

BLANK

(at its input pin)

†

‡

SFLAG/NFLAG

Valid

Don’t Care

Valid

Input

Latch First Group

of Pixel Data

Latch Last Group

of Pixel Data

LOAD

Sampled

BLANK

2nd

Group

4th

Group

1st

Group

3rd

Group

5th

Group

Last Group of Pixel Data

PIXEL DATA

SCLK

†

CAUTION:

If the data is not held valid until SCLK and BLANK both go low, the last few pixels could be missed.

Setup time to next VCLK falling edge after BLANK high (must be met, otherwise the first pixel data

could be missed).

‡

Figure 12. SFLAG/NFLAG Timing in Special Nibble Mode

2.10 MUXOUT Output

MUXOUT is a TTL-compatible output. It is software programmable and is used to control external devices.

Its typical application is to select the HSYNC and VSYNC inputs between the VGA pass-through mode and

the normal modes (see Section 2.8). This output is driven low at power-up or when VGA pass-through mode

is selected; at any other time it can be programmed to the desired polarity via general control register bit

7.

2.11 General Control Register

The general control register is used to control HSYNC and VSYNC polarity, split shift register transfer

enabling, special nibble mode, sync control, the ones accumulation clock source, and the VGA

pass-through indicator. The bit field definitions are as follows:

2–16

Table 8. General Control Register Bit Functions

GENERAL CONTROL REGISTER BIT

FUNCTION

HSYNCOUT is active-low

7

X

0

6

X

0

5

X

0

4

X

0

3

X

0

2

X

0

1

X

0

1

HSYNCOUT is active-high (default)

VSYNCOUT is active-low

VSYNCOUT is active-high (default)

Disable split shift register transfer (default)

Enable split shift register transfer

Disable special nibble mode (default)

Enable special nibble mode

0-IRE pedestal (default)

7.5-IRE pedestal

X

1

X

1

0

X

0

1

X

1

X

Disable sync (default)

1

Enable sync

X

Reserved (default)

1

Reserved

X

MUXOUT is low (default)

MUXOUT is high

1

2.11.1 HSYNCOUT and VSYNCOUT (Bits 0 and 1)

HSYNCOUT and VSYNCOUT polarity inversion is provided to allow indication to monitors of the current

screen resolution. Since the polarities for VGA pass-through mode are provided at the feature connector,

the inputs to the TLC34075 will have the right polarities for monitors already, so the TLC34075 just passes

them through with pipeline delay (see Section 2.8). These two bits only work in the normal modes, and the

input horizontal and vertical syncs are assumed to be active-low incoming pulses. These two bits default

to the value 1 but can be changed by software.

2.11.2 Split Shift Register Transfer Enable (SSRT) and Special Nibble Mode Enable

(SNM) (Bits 2 and 3)

See Section 2.9.

2.11.3 Pedestal Enable Control (Bit 4)

This bit specifies whether a 0- or 7.5-IRE blanking pedestal is to be generated on the video outputs. Having

a 0-IRE blanking pedestal means that the black and blank levels are the same.

0: 0-IRE pedestal (default)

1: 7.5-IRE pedestal

2.11.4 Sync Enable Control (Bit 5)

This bit specifies whether or not SYNC information is to be output onto IOG.

0: Disable sync (default)

1: Enable sync

2.11.5 MUXOUT (Bit 7)

The MUXOUT bit indicates to external circuitry that the device is running in VGA pass-through mode. This

bit does not affect the operation of the device (see Section 2.10).

0: MUXOUT is low (default in VGA pass-through mode)

1: MUXOUT is high

2–17

2.12 Test Register

There are three test functions provided in the TLC34075, and they are all controlled and monitored through

the test register. They are data flow check, DAC analog test, and screen integrity test.

The test register has two ports: one for a control word, accessed by writing to the register location, and one

for the data word, accessed by reading from the register location. Depending on the channel written in the

control word, the data read presents the information for that channel.

The control word is three bits long and occupies D<2:0>. It specifies which of the eight channels to inspect.

The following table and state machine diagrams show how each channel is addressed:

Table 9. Test Mode Selection

D2

0

D1

0

D0

0

CHANNEL

Color palette red value

Color palette green value

Color palette blue value

Identification code

0

1

0

1

0

1

0

Ones accumulation red value

Ones accumulation green value

Ones accumulation blue value

Analog test

1

0

1

0

1

ID code

011

RD

000

010

RESET

Blue

Red

RD

Green

001

Data Flow Check

Red

Blue

110

RD

100

RD

111

RD

Green

Screen Integrity Test

101

DAC Analog Test

Figure 13. Test Register Control Word State Diagrams

2–18

2.12.1 Frame Buffer Data Flow Test

The TLC34075 provides a means to check all the data entering the DAC (but before the output multiplexer

8/6 shift). When accessing these color channels, the data entering the DACs should be kept constant for

the entire MPU read cycle. This can be done either by slowing down the dot clock or ensuring that the data

is constant for a sufficiently long series of pixels. The value read is the one stored in the color palette RAM

location pointed to by the input multiplexer. The read operation causes a post-increment to point to the next

color channel, and the post-increment of blue wraps back to red as shown in the preceeding state diagram.

For example, if D<2:0> is written as 001, then three succsessive reads are performed, the values read out

are green, blue, and red in that sequence.

2.12.2 Identification Code

The ID code can be used for identification of different software versions. The ID code in the TLC34075 is

static and may be read without consideration of the dot clock or video signals. To be user-friendly, the read

postincrement also applies to the ID register, but once it falls into the color channel, it will not come back

pointing to the ID unless the value 011 is written to D<2:0> again. So, if the test register is written as 011

in D<2:0>, then six successive reads are performed, the first value read is the ID and the last value read

is green. The ID value defined here is 75h.

2.12.3 Ones Accumulation Screen Integrity Test

A technique called ones accumulation can be used to detect errors in fixed (not animated) screen displays.

This type of error detection is useful for system checkout and field diagnostics.

Each of the 256 24-bit words in the TLC34075 internal color palette RAM is composed of three bytes, one

each for the red, green, and blue components of the word. When D<2:0> are programmed with the

appropriate binary value (see Table 9), the TLC34075 monitors the corresponding color byte that is output

by the color palette RAM. For example, if D<2:0> are programmed with the value 100, the TLC34075

monitors the red byte. As the current frame is scanned, for each color palette RAM word accessed, the

designated color byte is checked to see how many “1” bits it contains, and this number is added to a

temporary accumulator (the entire byte is checked, even if 6-bit mode is selected). For example, if the

designated color byte contains the value 41h (0100 0001), then the value 2 is added to the temporary

accumulator, as 41h contains two “1” bits. This process is continued until an entire frame has been scanned;

the same color byte is monitored for the entire frame. The temporary accumulator truncates any overflow

above the value 255. Due to circuit speed limitations, the ones accumulation is calculated at a speed of

(DOTCLK frequency)/2. During the vertical retrace activated by a falling edge on the TLC34075 VSYNC

input, the value in the temporary accumulator is transferred into the ones accumulation register, and then

the temporary accumulator is reset to zero (NOTE: the ones accumulation register is updated only on the

falling edge of VSYNC, not by any vertical sync pulses coded into the composite video signal). Before the

next frame scan begins, the TLC34075 automatically changes the value in D<2:0> so that the ones

accumulation performed during the next frame scan is for a different color byte (see the screen integrity test

state diagram of Figure 13). As long as the screen display remains fixed, the ones accumulation value for

a particular color byte should not change; if it does, an error has occurred.

2.12.4 Analog Test

Analog test is used to compare the voltage amplitudes of the analog RGB outputs to each other and to a

145-mV reference. This enables the MPU to determine whether the CRT monitor is connected to the analog

RGB outputs or not and whether the DACs are functional. To perform an analog test, D<2:0> must be set

to 111; D<7:4> are set as shown in Table 11. D<3> contains the result of the analog test.

2–19

Table 10. Test Register Bit Definitions for Analog Test

BIT DEFINITION

D7: Red select

READ/WRITE

R/W

R

D6: Green select

D5: Blue select

D4: 145-mV reference select

D3: Result

Table 11. D<7:4> Bit Coding for Analog Comparisons

D<7:4>

0000

1010

1001

0110

OPERATION

Normal operation

IF D3 = 1

Don’t care

IF D3 = 0

Don’t care

Red DAC compared to blue DAC

Red > blue

Red < blue

Red DAC compared to 145-mV reference

Green DAC compared to blue DAC

Green DAC compared to 145-mV reference

Red > 145 mV

Green > blue

Green > 145 mV

Red < 145 mV

Green < blue

Green < 145 mV

0101

NOTE: All the outputs have to be terminated to compare the voltage.

IOR or IOG

+

D

Q

D3

–

IOB or 145 mV

BLANK

(Internal Signal)

C

Figure 14. Internal Comparator Circuitry for Analog Test

The result of the analog comparison is strobed into D3 at the falling edge of an internal signal derived from

the input BLANKsignal. Inordertohavestableinputstothecomparator, theDACshouldbesettoaconstant

level between syncs. For normal operation, data flow check, and screen integrity test, D<7:4> must be set

to zero.

2–20

3

Specifications

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

†

(Unless Otherwise Noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Analog output short-circuit duration to any power supply or common . . . . . . . . . unlimited

+ 0.5 V

I

DD

Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C

Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These

are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated

under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminal.

3.2 Recommended Operating Conditions

MIN

4.75

1.2

NOM

5

MAX

5.25

1.26

+ 0.5

0.8

UNIT

V

Supply voltage

DD

Reference voltage

1.235

V

REF

TTL inputs

ECL inputs

TTL inputs

ECL inputs

2.4

V

DD

High-level input voltage

Low-level input voltage

V

IH

V

– 1

DD

V

IL

–0.5

V

– 1.6

DD

Output load resistance, R

37.5

523

Ω

L

FS ADJUST resistor, R

SET

Operating free-air temperature

0

70

°C

3–1

3.3 Electrical Characteristics

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

High-level output voltage

I

= –800 µA

= 3.2 mA

= 15 mA

= 18 mA

2.4

V

OH

OL

OH

OL

D<0:7>, MUXOUT, VCLK

HSYNCOUT, VSYNCOUT

SCLK

0.4

1

Low-level output

voltage

V

High-level input

current

TTL inputs

V = 2.4 V

I

V = 4 V

I

IH

µA

ECL inputs

1

I

Low-level input

current

TTL inputs

V = 0.8 V

–1

I

IL

ECL inputs

V = 0.4 V

I

–1

TLC34075-66

TLC34075-85

TLC34075-110

TLC34075-135

TLC34075-66

TLC34075-85

TLC34075-110

TLC34075-135

350

375

400

470

450

10

Supply current,

I

DD

pseudo-color mode

See Note 2

mA

Supply current,

true color mode

I

High-impedance-state output currrent

µA

OZ

TTL inputs

Input capacitance

f = 1 MHz, V = 2.4 V

4

I

C

i

pF

ECL inputs

f = 1 MHz, V = 4 V

I

†

All typical values are at V

= 5 V, T = 25°C.

A

DD

is measured with DOTCLK running at the maximum specified frequency, SCLK frequency =

NOTE 2:

I

DD

DOTCLK frequency/4, and the palette RAM loaded with full-range toggling patterns (00h/00h/FFh/FFh/00h/

00h/FFh/FFh/ . . .). Pseudo-color mode is also known as color indexing mode.

3–2

3.4 Operating Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

8

MAX

UNIT

8/6 high

Resolution (each DAC)

8/6 low

bits

6

E

End-point linearity error

(each DAC)

8/6 high

8/6 low

8/6 high

8/6 low

1

1/4

1

L

LSB

Differential linearity error

(each DAC)

D

1/4

5%

20.4

18.5

1.9

50

Gray scale error

White level relative to blank

17.69 19.05

16.74 17.62

White level relative to black (7.5 IRE only)

Black level relative to blank (7.5 IRE only)

Blank level on IOR, IOB

mA

0.95

0

1.44

5

µA

mA

µA

Output current

Blank level on IOG (with SYNC enabled)

Sync level on IOG (with SYNC enabled)

One LSB (8/6 high)

6.29

0

7.6

8.96

50

5

69.1

276.4

2%

–20

µA

One LSB (8/6 low)

DAC-to-DAC matching

DAC-to-DAC crosstalk

Output compliance

5%

1.2

dB

V

oc

–1

Output impedance

50

13

kΩ

pF

Output capacitance

f = 1 MHz, I = 0

OUT

Clock and data feedthrough

Glitch impulse (see Note 2)

–20

50

dB

pV-s

Normal mode

VGA pass-through mode

1 SCLK + 9 DOTCLK

7.5 DOTCLK

Pipeline delay

periods

NOTE 2: Glitch impulse does not include clock and data feedthrough. The –3-dB test bandwidth is twice the clock rate.

3–3

3.5 Timing Requirements

TLC34075-66 TLC34075-85 TLC34075-110 TLC34075-135

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

DOTCLK frequency

66

85

110

135

MHz

CLK0 frequency for VGA

pass-through mode

66

85

MHz

TTL

15.2

11.8

9.1

7.4

Clock cycle time

t

ns

cyc

su1

h1

ECL

Setup time, RS<0:3>

valid before RD or WR ↓

10

35

0

10

35

0

10

35

0

10

35

0

Hold time, RS<0:3> valid

after RD or WR ↓

Setup time, D<0:7> valid

before WR ↑

su2

h2

Hold time, D<0:7> valid

after WR ↑

Setup time, VGA<0:7> and

HSYNC, VSYNC, and

VGABLANK valid before

CLK0 ↑

t

2

ns

su3

h3

Hold time, VGA<0:7> and

HSYNC, VSYNC, and

VGABLANK valid after CLK0 ↑

t

Setup time, P<0:31> valid

before SCLK ↑

t

2

5

2

5

2

5

0

5

ns

su4

Hold time, P<0:31> valid after

SCLK ↑

h4

Setup time, HSYNC, VSYNC,

and BLANK valid before

VCLK ↓

t

5

ns

su5

h5

Hold time, HSYNC, VSYNC,

and BLANK valid after VCLK ↓

t

2

ns

t

Pulse duration, RD or WR low

Pulse duration, RD or WR high

TTL

50

30

50

30

4

50

30

50

30

3

ns

w1

w2

4.5

5.5

4.5

5.5

3.5

t

ns

Pulse duration, clock high

w3

w4

ECL

4

3

TTL

4

3

t

Pulse duration, clock low

ns

ECL

4

3

Pulse duration, SFLAG/NFLAG

high (see Note 4)

t

30

w5

NOTES: 3. TTL input signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels unless

otherwisespecified.ECLinputsignalsareV –1.8VtoV –0.8Vwithlessthan2nsrise/falltimebetween

DD DD

the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and 90% signal

levels.Analogoutputloadsarelessthan10pF.D<0:7>outputloadsarelessthan50pF.Allotheroutputloads

are less than 50 pF unless otherwise specified.

4. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1

for details.

3–4

3.6 Switching Characteristics

TL34075-66, TLC34075-85

PARAMETER

TLC34075-66

TLC34075-85

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

SCLK frequency (see Note 5)

VCLK frequency

66

40

17

85

40

17

MHz

ns

t

Enable time, RD low to D<0:7> valid

Disable time, RD high to D<0:7> disabled

Valid time, D<0:7> valid after RD high

en1

dis1

v1

ns

5

0

5

0

ns

Propagation delay, SFLAG/NFLAG ↑ to SCLK

high (see Note 6)

t

20

ns

PLH1

d1

Delay time, RD low to D<0:7> starting to turn

on

5

Delay time, selected input clock high/low to

DOTCLK (internal signal) high/low

7

6

7

6

d2

Delay time, DOTCLK high/low to VCLK

high/low

t

d3

t

d4

t

d5

ns

Delay time, VCLK high/low to SCLK high/low

0

5

8

0

5

8

Delay time, DOTCLK high/low to SCLK

high/low

8

Delay time, DOTCLK high to IOR/IOG/IOB

active (analog output delay time) (seeNote7)

t

d6

t

d7

t

d8

20

ns

Analog output settling

time(seeNote 8)

Delay time, DOTCLK high to HSYNCOUT and

VSYNCOUT valid

5

2

5

2

t

Pulse duration, SCLK high (see Note 6)

Analog output rise time (see Note 9)

Analog output skew

15

0

55

2

15

0

55

2

ns

w6

r

NOTES: 5. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and

90% levels is less than 4 ns.

6. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1

for details.

7. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.

8. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within

± 1 LSB (settling time does not include clock and data feedthrough).

9. Measured between 10% and 90% of the full-scale transition.

3–5

3.6 Switching Characteristics (Cont’d.)

TL34075-110, TLC34075-135

PARAMETER

TLC34075-110

TLC34075-135

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

SCLK frequency (see Note 10)

VCLK frequency

85

40

17

85

40

17

MHz

ns

t

Enable time, RD low to D<0:7> valid

Disable time, RD high to D<0:7> disabled

Valid time, D<0:7> valid after RD high

en1

dis1

v1

ns

5

0

5

0

ns

Propagation delay, SFLAG/NFLAG ↑ to SCLK

high (see Note 11)

t

20

ns

PLH1

d1

Delay time, RD low to D<0:7> starting to turn

on

5

Delay time, selected input clock high/low to

DOTCLK (internal signal) high/low

7

6

7

6

d2

Delay time, DOTCLK high/low to VCLK

high/low

t

d3

t

d4

t

d5

ns

Delay time, VCLK high/low to SCLK high/low

0

5

6

0

5

6

Delay time, DOTCLK high/low to SCLK

high/low

8

Delay time, DOTCLK high to IOR/IOG/IOB

active (analog output delay time) (seeNote

12)

t

d6

20

ns

t

Analog output settling time (see Note 13)

ns

d7

Delay time, DOTCLK high to HSYNCOUT and

VSYNCOUT valid

3

2

3

2

d8

t

Pulse duration, SCLK high (see Note 11)

Analog output rise time (see Note 14)

Analog output skew

15

0

55

2

15

0

55

2

ns

w6

r

NOTES: 10.SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and

90% levels is less than 4 ns.

11. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1

for details.

12.Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.

13.Measured from the 50% point of the full-scale transition to the point at which the output has settled, within

± 1 LSB (settling time does not include clock and data feedthrough).

14.Measured between 10% and 90% of the full-scale transition.

3–6

3.7 Timing Diagrams

t

h1

su1

RS <0:3>

RD,WR

Valid

t

w2

w1

t

dis1

en1

d1

D <0:7>

(Output)

Data Out, RD Low

t

v1

D <0:7>

(Input)

Data In,

WR Low

t

h2

su2

Figure 15. MPU Interface Timing

3–7

t

cyc

t

w4

w3

CLK <0:3>

t

d2

DOTCLK

(Internal Signal)

t

d3

VCLK

t

d4

d5

d4

d5

SCLK

t

h3

t

su3

VGA <0:7>,

HSYNC, VSYNC, VGABLANK

(VGA Pass-Through Mode)

Data

t

h4

su4

t

Data

P <0:31>

t

h5

t

su5

HSYNC, VSYNC, BLANK

(Normal Mode)

Data

t

d7

d6

IOR,IOG,IOB

t

r

t

d8

HSYNCOUT

VSYNCOUT

Valid

Figure 16. Video Input/Output

BLANK

t

w5

SFLAG/

NFLAG

t

w6

PLH1

SCLK

Figure 17. SFLAG/NFLAG Timing (When SSRT Function is Enabled)

3–8

3–9

Appendix A

SCLK/VCLK and the TMS340x0

While the TLC34075 SCLK and VCLK outputs are designed for compatibility with all graphics systems, they

are also tightly coupled with the TMS340x0 Graphics System Processors. All the timing requirements of the

TMS340x0 have been considered. However, there are a few points that need to be explained with regard

to applications.

VCLK

All the video control signals in the TMS340x0 (i.e., BLANK, HSYNC, and VSYNC) are triggered and

generated from the falling edge of VCLK. The fact that the TLC34075 uses the falling edge to sample and

latch the BLANK input gives users maximum freedom to choose the frequency of VCLK and interconnect

the TLC34075 with the TMS340x0 GSP without glue logic. Needless to say, the VCLK frequency needs to

be selected to be compatible with the minimum VCLK period required by the TMS340x0.

IntheTMS340x0, thesameVCLKfallingedgethatgeneratesBLANKrequestsascreenrefresh. IftheVCLK

period is longer than 16 TQs (TQ is the period of the TMS340x0 CLKIN), it is possible that the last SCLK

pulse could be used falsely to transfer the VRAM data from memory to the shift register along with the last

pixel transfer. The first SCLK pulse for the next scan line would then shift the first pixel data out of the pipe

and the screen would then falsely start from the second pixel.

SCLK and SFLAG

The TLC34075 SCLK signal is compatible with current -10 and slower VRAMs. When split shift register

transfers are used, one SCLK pulse has to be generated between the regular shift register transfer and the

splitshiftregistertransfertoensurecorrectoperation. TheSFLAGinputisdesignedforthispurpose. SFLAG

can be generated from a programmable logic array and triggered by the rising edge of the TR/QE signal or

the rising edge of the RAS signal of the regular shift register transfer cycle. TR/QE can be used if the

minimum delay from when the VRAM’s TRG signal goes high to SCLK going high can be met by the

programmable logic array delay; otherwise, RAS can be used.

A–1

A–2

Appendix B

PC Board Layout Considerations

PC Board Considerations

A four-layer PC board should be used with the TLC34075: one layer each for 5-V power and GND and two

layers for signals. The layout should be optimized for the lowest-possible noise on the TLC34075 power and

ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups

of V

and GND pins should be minimized so as to reduce inductive ringing. The terminal assignments for

DD

the TLC34075 P<0:31> inputs were selected for minimum interconnect lengths between these inputs and

the VRAM pixel data outputs. The TLC34075 should be located as close to the output connectors as

possible to minimize noise pickup and reflections due to impedance mismatching.

Ground Plane

A single ground plane is recommended for both the TLC34075 and the rest of the logic. Separate digital and

analog ground planes are not needed.

Power Plane

Split power planes are recommended for the TLC34075 and the rest of the logic. The TLC34075 and its

associated analog circuitry should have their own power plane (referred to as A

in Figure 18). The two

VCC

power planes should be connected at a single point through a ferrite bead as shown in Figures 18, 19, and

20. This bead should be located within three inches of the TLC34075.

Supply Decoupling

Bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation,

to reduce the lead inductance.

For the best performance, a 0.1-µF ceramic capacitor in parallel with a 0.01-µF chip capacitor should be

used to decouple each of the three groups of power pins to GND. These capacitors should be placed as

close as possible to the device as shown in Figure 19.

If a switching power supply is used, the designer should pay close attention to reducing power supply noise

and should consider using a three-terminal voltage regulator for supplying power to A

.

VCC

COMP and V

Terminals

REF

A 100-Ω resistor and 0.1-µF ceramic capacitor (approximate values) should be connected in series

between the device’s COMP and V terminals in order to avoid noise and color-smearing problems. Also,

DD

whether an internal or external voltage reference is used, a 0.1-µF capacitor should be connected between

the device’s V

and GND terminals to further stabilize the video image. These resistor and capacitor

REF

values may vary depending on the board layout; experimentation may be required in order to determine

optimum values.

B–1

R6

COMP

C9

L1

AV

CC

V

DD

V

CC

R1

C1-C3

C5-C7

C11

C10

V

REF

C12

D1

TLC34075

GND

R2

R3

R4

R5

FS ADJUST

IOR

IOG

To Video Connector

IOB

LOCATION

DESCRIPTION

C1-C3, C9-C10, C12 0.1-µF ceramic capacitor

C5-C7

C11

0.01-µF ceramic chip capacitor

33-µF tantalum capacitor

ferrite bead

L1

R1

1000-Ω 1% metal-film resistor

523-Ω 1% metal-film resistor

75-Ω 1% metal-film resistor

100-Ω 5% resistor

R2

R3, R4, R5

R6

D1

1.2-V voltage reference

Figure 18. Typical Connection Diagram and Components (Shaded Area is Optional)

B–2

R1

D1

R6

C7

C3

P1

R2

R3

Edge of

the Board

R4

R5

TLC34075

(84-Pin PLCC)

C5

U1

L1

+

C11

Figure 19. Typical Component Placement (Component Side)

V

CC

Edge of

the Board

AV

CC

V

CC

V

CC

Figure 20. Typical Split Power Plane (Solder Side)

B–3

B–4

Appendix C

SCLK Frequency > VCLK Frequency

The VCLK and SCLK outputs generated by the TLC34075 are both free-running clocks. The video control

signals (i.e., HSYNC, VSYNC, and BLANK) are normally generated from VCLK, and a fixed relationship

between the video control signals and VCLK can therefore be expected. The TLC34075 samples and

latches the BLANK input on the falling edge of VCLK. It then looks at the LOAD signal to determine when

to disable or enable SCLK at its output terminal. The decision is deterministic when the SCLK frequency

is greater than or equal to the VCLK frequency. However, when the SCLK frequency is less than the VCLK

frequency, the appearance of the SCLK waveform at its output terminal when BLANK is sampled low on the

VCLK falling edge can vary (see Figures C–1 and C–2).

To avoid this variation in the SCLK output waveform, the SCLK and VCLK frequencies should be chosen

so that HTOTAL is evenly divisible by the ratio of (VCLK frequency:SCLK frequency); that is,

HTOTAL

VCLK frequency

SCLK frequency

remainder of

0.

For example, if HTOTAL is even, VCLK frequency = DOTCLK frequency/8, and SCLK frequency =

DOTCLK frequency/16, then the formula above is satisfied. NOTE: When HTOTAL starts at zero (as in the

TMS340x0 GSP), then the formula becomes

(HTOTAL

1)

remainder of

0.

VCLK frequency

SCLK frequency

VCLK

BLANK

LOAD

(Internal Signal

for Data Latch)

SCLK at

Output Terminal

Figure 21. VCLK and SCLK Phase Relationship (Case 1)

C–1

VCLK

BLANK

LOAD

(Internal Signal

for Data Latch)

SCLK at

Output Terminal

Figure 22. VCLK and SCLK Phase Relationship (Case 2)

C–2

Appendix D

Mechanical Data

FN020, FN028, FN044, FN052, FN068, and FN084

plastic J-leaded chip carrier

Each of these chip carrier packages consists of a circuit mounted on a lead frame and

enncapsulated within an electrically nonconductive plastic compound. The compound

withstands soldering temperatures with no deformation, and circuit performance

characteristics remain stable when the devices are operated in high-humidity conditions.

The package is intended for surface mounting on 1,27 (0.050) centers. Leads require no

additional cleaning or processing when used in soldered assembly.

Designation per JEDEC Std 30:

FN020, FN028, FN044, FN052, FN068, and FN084

(20-PIN package used for illustration)

S-PLCC-J20

S-PLCC-J28

S-PLCC-J52

S-PLCC-J84

S-PLCC-J44

S-PLCC-J68

D

S

D–E

0.18 (0.007)

B

– A –

(see Note D)

D

1

(see Note B)

–H–

Seating Plane

(see Note B)

S

D–E

0.18 (0.007)

B

S

A

1

0,51 (0.020) R. MAX

3 Places

(0.002 IN./IN.)

B

–C–

A

0.10 (0.004)

–D–

1,22 (0.048)

1,07 (0.042)

1,42 (0.056)

1,07 (0.042)

0,81 (0.032)

2 Places

(see Note C)

1,14 (0.045)

0,64 (0.025)

R. TYP

TYP

0,66 (0.026)

3

9

2

1

20 19

18

S

A

0.18 (0.007)

B

4

5

D

, E

2 Sides (see Note E)

2

17

16

15

14

D

, E

3

(see Note

F)

0.38 (0.015)

3

(see Note

F)

1,27 (0.050) T.P.

4 Sides

6

7

8

S

D–E

–G–

0.38 (0.015)

F–G

S

(see Note C)

10 11 12 13

0,51 (0.020) MIN

–E–

(see Note C)

0,36 (0.014)

0,20 (0.008)

(Includes Lead Finish)

Sum of Dam Bar Protrusions

to be 0,18 (0.007) Maximum

Per Lead

1,52 (0.060) MIN

–C–

0,53 (0.021)

0,33 (0.013)

0,64 (0.025)

MIN

M

0.18 (0.007)

F–G S

0.18 (0.007)M D–E

S

(see table on following page for additional dimensions)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTES: A. All dimensions conform to JEDEC Specification MO-047AA/AF. Dimensions and tolerancing are per ANSI

Y14.5M – 1982.

B. Dimensions D and E do not include mold flash protrusion. Protrusion shall not exceed 0,25 (0.010) on any

1

side. Centerline of center pin each side is within 0,10 (0.004) of package centerline by dimension B. The lead

contact points are planar within 0,10 (0.004).

C. Datums D – E and F – G for center leads are determined at datum – H – .

D. Datum – H – is located at top of leads where they exit plastic body.

E. Location of datums – A – and – B – to be determined at datum – H – .

F. Determined at seating plane – C – .

D-1

Mechanical Data

JEDEC

NO. OF

PINS

A

D, E

D , E

3 3

1

2

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

8,89

MAX

MIN

7,37

MAX

BASIC

4,19

4,57

2,29

3,05

9,78

10,03

9,04

8,38

5,08

MO-047AA

MO-047AB

MO-047AC

MO-047AD

MO-047AE

MO-047AF

20

28

44

52

68

84

(0.165) (0.180) (0.090) (0.120) (0.385) (0.395) (0.350) (0.356) (0.290) (0.330) (0.200)

4,19 4,57 2,29 3,05 12,32 12,57 11,43 11,58 9,91 10,92 7,62

(0.165) (0.180) (0.090) (0.120) (0.485) (0.495) (0.450) (0.456) (0.390) (0.430) (0.300)

4,19 4,57 2,29 3,05 17,40 17,65 16,51 16,66 14,99 16,00 12,70

(0.165) (0.180) (0.090) (0.120) (0.685) (0.695) (0.650) (0.656) (0.590) (0.630) (0.500)

4,19 5,08 2,29 3,30 19,94 20,19 19,05 19,20 17,53 18,54 15,24

(0.165) (0.200) (0.090) (0.130) (0.785) (0.795) (0.750) (0.756) (0.690) (0.730) (0.600)

4,19 5,08 2,29 3,30 25,02 25,27 24,13 24,33 22,61 23,62 20,32

(0.165) (0.200) (0.090) (0.130) (0.985) (0.995) (0.950) (0.958) (0.890) (0.930) (0.800)

4,19 5,08 2,29 3,30 30,10 30,35 29,21 29,41 27,69 28,70 25,40

(0.165) (0.200) (0.090) (0.130) (1.185) (1.195) (1.150) (1.141) (1.090) (1.130) (1.000)

NOTES: A. All dimensions conform to JEDEC Specification MO-047AA/AF. Dimensions and tolerancing are per ANSI

Y14.5M – 1982.

F

Determined at seating plane – C – .

D-2

D-3


型号：	TLC34075
厂家：	TEXAS INSTRUMENTS
描述：	Video Interface Palette 视频接口调色板
文件：	总52页 (文件大小：284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC34075 [TI]

相关型号：

TLC34075-110

TLC34075-110AFN

TLC34075-110AFNR

TLC34075-110FN

TLC34075-135

TLC34075-135AFN

TLC34075-135AFNR

TLC34075-135FN

TLC34075-66

TLC34075-66AFN

TLC34075-66AFNR

TLC34075-66FN