TLC3578IPWRG4_技术文档

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SLAS262C − OCTOBER 2000 − REVISED MAY 2003

TLC3578, TLC2578

DW OR PW PACKAGE

(TOP VIEW)

D

14-Bit Resolution for TLC3574/78, 12-Bit for

TLC2574/2578

D

Maximum Throughput 200-KSPS

1

24

23

22

21

20

19

18

17

16

15

14

13

SCLK

FS

SDI

CSTART

D

Multiple Analog Inputs:

− 8 Single-Ended Channels for

TLC3578/2578

− 4 Single-Ended Channels for

TLC3574/2574

2

AV

DD

3

AGND

COMP

REFM

REFP

AGND

4

EOC/INT

SDO

DGND

5

6

D

Analog Input Range: 10 V

7

DV

DD

Pseudodifferential Analog Inputs

8

CS

A0

A1

A2

A3

AV

A7

A6

A5

A4

DD

9

SPI/DSP-Compatible Serial Interfaces With

SCLK up to 25-MHz

10

11

12

D

Built-In Conversion Clock and 8x FIFO

D

Single 5-V Analog Supply; 3-/5-V Digital

Supply

TLC3574, TLC2574

DW, N, OR PW PACKAGE

(TOP VIEW)

D

Low-Power

− 5.8 mA in Normal Operation

− 20 µA in Power Down

D

Programmable Autochannel Sweep and

Repeat

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

SCLK

FS

SDI

CSTART

AV

DD

AGND

COMP

REFM

REFP

AGND

Hardware-Controlled, Programmable

Sampling Period

EOC/INT

SDO

DGND

D

Hardware Default Configuration

D

INL: TLC3574/78: 1 LSB;

TLC2574/78: 0.5 LSB

DV

DD

CS

A0

A1

AV

A3

A2

DD

D

DNL: TLC3574/78: 0.5 LSB;

TLC2574/78: 0.5 LSB

SINAD: TLC3574/78: 79 dB;

TLC2574/78: 72 dB

THD: TLC3574/78: −82 dB;

TLC2574/78: −82 dB

description

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS

analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate

from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital

input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state

serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI,

SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being

transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow

the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must

be tied to DV

if it is not used (such as in an SPI interface). When SDI is tied to DV , the device is set in

DD

hardware default mode after power on and no software configuration is required. In the simplest case, only three

wires (SDO, SCLK, and CS or FS) are needed to interface with the host.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2000 − 2003, Texas Instruments Incorporated

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1

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SLAS262C − OCTOBER 2000 − REVISED MAY 2003

description (continued)

In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog

multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold

function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin,

CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be

programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK

operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are

designed to operate with low-power consumption. The power saving feature is further enhanced with

autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in.

The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78

and TLC2574/78 are specified with bipolar input and a full scale range of 10 V.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

20-TSSOP

(PW)

20-SOIC

(DW)

20-PDIP

(N)

24-SOIC

(DW)

24-TSSOP

(PW)

TLC2574IPW

TLC3574IPW

TLC2574IDW

TLC3574IDW

TLC2574IN

TLC3574IN

TLC2578IDW

TLC3578IDW

TLC2578IPW

TLC3578IPW

−40°C to 85°C

functional block diagram

DV

AV

DD

REFP

COMP

REFM

†

X8

‡

X4

A0 A0

A1 A1

A2 A2

A3 A3

FIFO

X8

SAR

ADC

Analog

MUX

Signal

Scaling

OSC

A4

A5

A6

A7

X

SDO

Conversion

Clock

Command

Decode

CFR

SDI

CMR (4 MSBs)

SCLK

CS

FS

Control

Logic

4-Bit

EOC/INT

Counter

CSTART

DGND AGND

†

‡

TLC3578, TLC2578

TLC3574, TLC2574

NOTE: 4-Bit counter counts the CLOCK, SCLK. The CLOCK is gated in by CS falling edge if CS initiates the conversion operation cycle, or gated

in by the rising edge of FS if FS initiates the operation cycle. SCLK is disabled for serial interface when CS is high.

2

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SLAS262C − OCTOBER 2000 − REVISED MAY 2003

equivalent input circuit

V

DD

REFP

Bipolar Signal Scaling

MUX

Digital Input

3.94 kΩ

6.6 kΩ

1.5 kΩ

9.9 kΩ

Ain

R

on

C

= 30 pF

(sample)

Equivalent Digital Input Circuit

REFM

Diode Turn on Voltage: 35 V

Equivalent Analog Input Circuit

Terminal Functions

TERMINAL

NO.

I/O

DESCRIPTION

NAME

TLC3574 TLC3578

TLC2574 TLC2578

A0

A1

A2

A3

A4

A5

A6

A7

9

I

Analog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The

driving source impedance should be less than or equal to 25 Ω for normal sampling. For larger

source impedance, use the external hardware conversion start signal CSTART (the low time of

CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling

time.

A1

A2

A3

10

11

12

10

11

12

13

14

15

16

AGND

14, 18

18, 22

I

Analog ground return for the internal circuitry. Unless otherwise noted, all analog voltage

measurements are with respect to AGND.

AV

DD

13, 19

17

17, 23

21

I

Analog supply voltage

COMP

CS

Internal compensation pin. Install compensation capacitors 0.1 µF between this pin and AGND.

8

Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is

disabled to clock data, but works as conversion clock source if programmed. The falling edge of

CS input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from

high-impedance state.

If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave

select (SS) to provide an SPI interface.

If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip

select to allow host to access the individual converter.

CSTART

20

24

I

External sampling trigger signal, which initiates the sampling from a selected analog input channel

when the device works in extended sampling mode (asynchronous sampling). A high-to-low

transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold

mode and starts the conversion. The low time of the CSTART signal controls the sampling period.

CSTART signal must stay low long enough for proper sampling. CSTART must stay high long

enough after the low-to-high transition for the conversion to finish maturely. The activation of

CSTART is independent of SCLK and the level of CS and FS. However, the first CSTART cannot

be issued before the rising edge of the eleventh SCLK. Tie this pin to DV

Digital ground return for the internal circuitry

Digital supply voltage

if not used.

DD

DGND

DV

6

7

6

7

I

DD

3

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SLAS262C − OCTOBER 2000 − REVISED MAY 2003

Terminal Functions (Continued)

TERMINAL

NO.

I/O

TLC3574 TLC3578

TLC2574 TLC2578

DESCRIPTION

NAME

EOC(INT)

4

O

End of conversion (EOC) or interrupt to host processor (INT)

EOC: used in conversion mode 00 only. EOC goes from high to low at the end of the sampling and

remains low until the conversion is complete and data is ready.

INT: Interrupt to the host processor. The falling edge of INT indicates data is ready for output. INT

is cleared by the following CS↓, FS↑, or CSTART↓.

FS

2

I

Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being

transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, the

rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI,

SDO, and SCLK. Tie this pin to DV

DD

if FS is not used to initiate the operation cycle.

REFM

REFP

16

15

20

19

I

External low reference input. Connect REFM to AGND.

External positive reference input. The range of maximum input voltage is determined by the

difference between the voltage applied to this terminal and to the REFM terminal. Always install

decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP and REFM.

SCLK

SDI

1

3

1

3

I

Serial clock input from the host processor to clock in the input from SDI and clock out the output

via SDO. It can also be used as the conversion clock source when the external conversion clock

is selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabled

for the data transfer, but can still work as the conversion clock source.

Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits,

except for the WRITE CFR command, are filled with zeros. The WRITE CFR command requires

additional 12-bit data. The MSB of input data, ID(15), is latched at the first falling edge of SCLK

following FS falling edge if FS starts the operation, or latched at the falling edge of first SCLK

following CS falling edge when CS initiates the operation.

The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling

edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a

low-to-high transition of CS, whichever happens first. Refer to the timing specification for the timing

requirements. Tie SDI to DV

DD

if using hardware default mode (refer to Device Initialization).

SDO

5

O

The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO.

SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. The

output format is MSB (OD15) first.

When FS initiates the operation, the MSB of output via SDO, OD(15), is valid before the first falling

edge of SCLK following the falling edge of FS.

When CS initiates the operation, the MSB, OD(15), is valid before the first falling edge of SCLK

following the CS falling edge.

The remaining data bits (if any) are shifted out on the rising edge of SCLK and are valid before the

falling edge of SCLK. Refer to the timing specification for the details.

In select/conversion operation, the first 14 bits (for TLC3574/78) or the first 12 bits (for TLC2574/78)

are the results from the previous conversion (data). In a READ FIFO operation, this data is from

FIFO. In both cases, the last two bits (for TLC3574/78) or the last four bits (for TLC2574/78) are

don’t care.

In a WRITE operation, the output from SDO must be ignored.

SDO goes into high-impedance state at the 16th falling edge of SCLK after the operation cycle is

initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.

4

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SLAS262C − OCTOBER 2000 − REVISED MAY 2003

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, GND to AV

and DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V

DD

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −17 V to 17 V

Analog input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA MAX

Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV

+ 0.3 V

DD

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

J

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

A

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1.16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under electrical characteristics and timing

characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

general electrical characteristics over recommended operating free-air temperature range,

single-ended input, normal long sampling, 200 KSPS, AV

= 5 V, V

= 4 V, V

= 0 V,

DD

REFP

REFM

SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source resistance

= 25 Ω (unless otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

Digital Input

DV

= 5 V

= 3 V

= 5 V

= 3 V

3.8

2.1

DD

V

High-level digital input voltage

Low-level digital input voltage

V

IH

IL

0.8

V

0.6

I

High-level digital input current

Low-level digital input current

Input capacitance

V = DV

0.005

2.5

µA

pF

IH

I

DD

V = DGND

I

−2.5 −0.005

20

IL

25

Digital Output

DV

= 5 V

= 3 V

4.2

2.4

DD

V

I

High-level digital output at 30 pF load

Low-level digital output at 30 pF load

I

= −0.2 mA

V

OH

o

I

o

I

o

I

o

I

o

= 0.8 mA

= 50 µA

= 0.8 mA

= 50 µA

0.4

0.1

0.4

0.1

1

DV

= 5 V

= 3 V

DD

OL

DD

V

= DV

DD

0.02

Off-state output current

(high-impedance state)

O

µA

CS = DV

DD

OZ

V

= DGND

−1

0.02

O

Power Supply

AV

DD

4.75

2.7

5

5.5

V

Supply voltage

DV

DD

AV

Al

current

DD

CC

4.2

1.6

5

Conversion clock is internal OSC,

AV = 5.5 V − 4.5 V, CS = DGND,

Power supply cur-

rent

I

mA

CC

DD

Excluding bipolar input biasing current

DV

Dl

CC

DD

2.0

I

For all digital inputs = DV

or DGND,

= 5.5 V, Excluding bipolar input

SCLK OFF

SCLK ON

20

CC

DD

AV

DD

µA

°C

(autopwrdn):

Autopower-down power supply

current

175

230

85

biasing current, external reference

Operating temperature

−40

†

All typical values are at T = 25°C.

A

5

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SLAS262C − OCTOBER 2000 − REVISED MAY 2003

general electrical characteristics over recommended operating free-air temperature range, single-

ended input, normal long sampling, 200 KSPS, AV

= 5 V, V

= 4 V, V

= 0 V,

DD

REFP

REFM

SCLK frequency = 25 MHz, fixed channel at CONV mode 00, analog input signal source

resistance = 25 Ω (unless otherwise noted)

TLC3574/78 and TLC2574/78

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Resolution

14

bits

Analog Input

Voltage range

−10

10

V

Selected channel at 10 V

Selected channel at –10 V

0.8

−1.2

10

1.6

Selected analog input channel bias current

mA

−1.6

Impedance

Capacitance

Reference

kΩ

30

pF

V

Positive reference voltage

Negative reference voltage

3.96

0

4

4.04

V

REFP

REFM

V

AGND

No conversion (AV

SCLK=DGND)

= 5V, CS= DV ,

DD

100

8.3

MΩ

kΩ

µA

Input impedance

Normal long sampling (AV

DD

SCLK = 25 MHz, External conversion clock)

= 5V, CS=DGND,

12.5

0.4

No conversion (AV = 5 V,

DD

SCLK = DGND, CS = DV

1.5

0.6

)

DD

Reference current

Normal long sampling (AV

External conversion clock, SCLK = 25 MHz,

= 5 V, CS = DGND,

DD

mA

V

= 5 V)

REF

DV

Internal oscillation frequency

Conversion time

= 2.7 V – 5.5 V

6.5

MHz

DD

TLC3574/78

TLC2574/78

TLC3574/78

TLC2574/78

2.785

2.015

Internal OSC, 6.5 MHz minimum

t

µS

(conv)

2.895

2.095

1.2

Conversion clock is external source,

SCLK = 25 MHz (see Note 1)

Acquisition time

Normal short sampling

µS

Normal long sampling, fixed channel

in mode 00 or 01

Throughput rate (see Note 2)

200

KSPS

†

All typical values are at T = 25°C.

A

NOTES: 1. Conversion time t

is (18 × 4 × SCLK) + 15 ns for TLC3574/78. Conversion time is (13 × 4 × SCLK) + 15 ns for TLC2574/78.

(conv)

2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required

to overcome the memory effect of the charge redistribution DAC.

6

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ꢗ ꢚꢛ ꢒ ꢌꢁ ꢌꢍꢌ ꢁꢎ ꢏ ꢊꢀꢎ ꢊꢑꢒꢏ ꢒ ꢀꢌꢁ ꢂꢎ ꢍꢋꢚ ꢛꢀ ꢚꢛꢗ ꢜ ꢒꢀ ꢙ ꢓ ꢕ ꢊꢋ ꢒ ꢍꢘ ꢝ ꢀꢗ

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

AC/DC performance over recommended operating free-air temperature range, single-ended input,

normal long sampling, 200 KSPS, AV

= 5 V, V

= 4 V, V

= 0 V, SCLK frequency = 25 MHz,

DD

REFP

REFM

fixed channel at CONV mode 00, analog input signal source resistance = 25 Ω (unless otherwise

noted)

TLC3574/78 DW and PW package device AC/DC performance

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

DC Accuracy—Normal Long Sampling

E

Integral linearity error

Differential linearity error

Bipolar zero error

See Note 3

−1.5

−1

1

1.5

1

LSB

L

0.5

0.08

0.04

0.13

D

See Note 4

−0.30

−0.55

−0.30

0.36

0.61

0.79

%FS

O

Positive full scale error

Negative full scale error

FS(+)

FS(−)

DC Accuracy—Normal Short Sampling

E

Integral linearity error

Differential linearity error

Bipolar zero error

See Note 3

1

0.5

LSB

L

D

See Note 4

0.08

0.04

0.13

%FS

O

Positive full scale error

Negative full scale error

FS(+)

FS(−)

AC Accuracy (see Note 3)—Normal Long Sampling

f = 20 kHz

76

79

75

i

SINAD

THD

Signal-to-noise ratio + distortion

Total harmonic distortion

Signal-to-noise ratio

dB

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

−82

−78

80

−77

78

12.3

78

SNR

dB

78

12.8

12.2

84

ENOB

SFDR

Effective number of bits

Bits

Spurious free dynamic range

Channel-to-channel isolation

dB

f = 100 kHz

i

79

Fixed channel in conversion mode 00, f = 35 kHz,

i

See Notes 2 and 5

81

Full power bandwidth, −3 dB

Full power bandwidth, −1 dB

1

MHz

kHz

Analog input bandwidth

700

†

All typical values are at T = 25°C.

A

NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required

to overcome the memory effect of the charge redistribution DAC.

3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.

4. Bipolar zero error is the difference between 10000000000000 and the converted output for zero input voltage; positive full-scale error

is the difference between 11111111111111 and the converted output for positive full-scale input voltage (10 V); negative full-scale

error is the difference between 00000000000000 and the converted output for negative full-scale input voltage (−10 V).

5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the

channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if the

converter samples different channels alternately.

7

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ꢄꢊ ꢋ ꢌ ꢍ ꢌꢁ ꢎꢏꢇ ꢃ ꢊꢐ ꢄ ꢊꢋ ꢑꢒ ꢏ ꢒ ꢀꢌꢁ ꢇ ꢓ ꢆ ꢊꢐ ꢓ ꢉꢊꢔ ꢒ ꢀꢇ ꢉ ꢕ ꢕ ꢊꢖꢗꢘ ꢗꢇ ꢆ ꢊꢐꢈ ꢊꢂꢙ ꢌꢍꢍꢚ ꢁ

ꢗ ꢚꢛꢒ ꢌ ꢁ ꢌ ꢍ ꢌꢁ ꢎꢏ ꢊꢀꢎ ꢊꢑꢒ ꢏ ꢒꢀꢌꢁ ꢂꢎ ꢍꢋ ꢚ ꢛꢀ ꢚ ꢛꢗ ꢜ ꢒꢀ ꢙ ꢓ ꢕ ꢊꢋ ꢒꢍ ꢘꢝꢀ ꢗ

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

TLC3574/78 DW and PW package device AC/DC performance (continued)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

AC Accuracy—Normal Short Sampling

f = 20 kHz

79

75

i

SINAD

THD

Signal-to-noise ratio + distortion

Total harmonic distortion

Signal-to-noise ratio

dB

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

−82

−78

80

SNR

dB

f = 100 kHz

i

78

f = 20 kHz

12.8

12.2

84

i

ENOB

SFDR

Effective number of bits

Bits

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

Spurious free dynamic range

Channel-to-channel isolation

dB

79

Fixed channel in conversion mode 00, f = 35 kHz,

i

See Notes 2 and 5

81

Full power bandwidth, −3 dB

Full power bandwidth, −1 dB

1

MHz

kHz

Analog input bandwidth

700

†

All typical values are at T = 25°C.

A

NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required

to overcome the memory effect of the charge redistribution DAC.

5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the

channel of interest. The converter samples this examined channel continuously. The channel-to-channel isolation is degraded if the

converter samples different channels alternately.

8

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ꢗ ꢚꢛ ꢒ ꢌꢁ ꢌꢍꢌ ꢁꢎ ꢏ ꢊꢀꢎ ꢊꢑꢒꢏ ꢒ ꢀꢌꢁ ꢂꢎ ꢍꢋꢚ ꢛꢀ ꢚꢛꢗ ꢜ ꢒꢀ ꢙ ꢓ ꢕ ꢊꢋ ꢒ ꢍꢘ ꢝ ꢀꢗ

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

TLC3574I N package device AC/DC performance

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

DC Accuracy—Normal Long Sampling

E

Integral linearity error

Differential linearity error

Bipolar zero error

See Note 3

−1.5

−1

1

1.5

LSB

L

0.8

0.08

0.04

0.13

D

See Note 4

−0.30

−0.55

−0.30

0.36

0.61

0.79

%FS

O

Positive full scale error

Negative full scale error

FS(+)

FS(−)

DC Accuracy—Normal Short Sampling

E

Integral linearity error

Differential linearity error

Bipolar zero error

See Note 3

1.8

0.8

LSB

L

D

See Note 4

0.08

0.04

0.13

%FS

O

Positive full-scale error

Negative full-scale error

FS(+)

FS(−)

AC Accuracy (see Note 3)—Normal Long Sampling

f = 20 kHz

75

78

75

i

SINAD

THD

Signal-to-noise ratio + distortion

Total harmonic distortion

Signal-to-noise ratio

dB

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

f = 100 kHz

i

f = 20 kHz

i

−82

−75

80

−77

78

12.2

78

SNR

dB

76

12.7

12.2

83