TLC3704MDRG4 [TI]
QUAD COMPARATOR, 10000uV OFFSET-MAX, 2700ns RESPONSE TIME, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14;
| 型号： | TLC3704MDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD COMPARATOR, 10000uV OFFSET-MAX, 2700ns RESPONSE TIME, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14 放大器 光电二极管 |
| 文件： | 总36页 (文件大小：1242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
D, J, OR N PACKAGE
D
Push-Pull CMOS Output Drives Capacitive
Loads Without Pullup Resistor,
I = 8 mA
O
(TOP VIEW)
1OUT
2OUT
VDD
2IN−
2IN+
1IN−
1IN+
3OUT
4OUT
GND
4IN+
4IN−
3IN+
3IN−
1
2
3
4
5
6
7
14
13
12
11
10
9
D
D
D
D
Very Low Power . . . 200 µW Typ at 5 V
Fast Response Time . . . t
With 5-mV Overdrive
= 2.7 µs Typ
PLH
Single Supply Operation . . . 3 V to 16 V
TLC3704M . . . 4 V to 16 V
8
On-Chip ESD Protection
description
PW PACKAGE
(TOP VIEW)
The TLC3704 consists of four independent
micropower voltage comparators designed to
operate from a single supply and be compatible
with modern HCMOS logic systems. They are
functionally similar to the LM339 but use 1/20th
the power for similar response times. The
push-pull CMOS output stage drives capacitive
loads directly without a power-consuming pullup
resistor to achieve the stated response time.
Eliminating the pullup resistor not only reduces
power dissipation, but also saves board space
and component cost. The output stage is also fully
compatible with TTL requirements.
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
2OUT
VDD
2IN−
2IN+
1IN−
1IN+
3OUT
4OUT
GND
4IN+
4IN−
3IN+
3IN−
8
FK PACKAGE
(TOP VIEW)
Texas Instruments LinCMOS process offers
superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing
speed, high input impedance, and low bias
currents, the LinCMOS process offers extremely
stable input offset voltages with large differential
input voltages. This characteristic makes it
possible to build reliable CMOS comparators.
3
2 1 20 19
GND
NC
4IN+
NC
VDD
NC
2IN−
NC
18
17
16
15
14
4
5
6
7
8
4IN−
2IN+
9 10 11 12 13
The TLC3704C is characterized for operation
over the commercial temperature range of 0°C to
70°C. The TLC3704I is characterized for
operation over the extended industrial tempera-
ture range of − 40°C to 85°C. The TLC3704M is
characterized for operation over the full military
temperature range of − 55°C to 125°C. The
TLC3704Q is characterized for operation from −
40°C to 125°C.
NC − No internal connection
symbol (each comparator)
IN+
IN−
OUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 2009, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
AVAILABLE OPTIONS
PACKAGE
V
max
IO
T
A
SMALL OUTLINE
(D)
CERAMIC
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
TSSOP
(PW)
at 25°C
0°C to 70°C
−40°C to 85°C
−55°C to 125°C
−40°C to 125°C
5 mV
5 mV
5 mV
5 mV
TLC3704CD
TLC3704ID
TLC3704MD
—
—
—
TLC3704CN
TLC3704CPW
—
TLC3704MFK
—
—
TLC3704IN
TLC3704IPW
TLC3704MJ
TLC3704QJ
—
—
—
—
The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g., TLC3704CDR).
functional block diagram (each comparator)
V
DD
IN+
IN−
Differential
Input
Circuits
OUT
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 18 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
ID
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to V
I
DD
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to V
O
DD
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Total supply current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
DD
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TLC3704C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70°C
A
TLC3704I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
TLC3704M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
TLC3704Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN−.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
FK
J
N
PW
950 mW
1375 mW
1375 mW
1150 mW
675 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
5.4 mW/°C
608 mW
880 mW
880 mW
736 mW
432 mW
494 mW
715 mW
715 mW
598 mW
351 mW
N/A
275 mW
275 mW
N/A
N/A
recommended operating conditions
TLC3704C
MIN NOM
UNIT
MAX
Supply voltage, V
3
5
16
V
V
DD
Common-mode input voltage, V
− 0.2
V
DD
− 1.5
IC
High-level output current, I
− 20
20
mA
mA
°C
OH
OL
Low-level output current, I
Operating free-air temperature, T
0
70
A
electrical characteristics at specified operating free-air temperature, VDD = 5 V
(unless otherwise noted)
TLC3704C
TYP
†
PARAMETER
Input offset voltage
Input offset current
Input bias current
T
UNIT
TEST CONDITIONS
A
MIN
MAX
5
V
V
= 5 V to 10 V,
25°C
0°C to 70°C
25°C
1.2
DD
V
IO
mV
= V min,
See Note 3
6.5
IC
ICR
1
5
pA
nA
pA
nA
I
IO
V
IC
= 2.5 V
70°C
0.3
0.6
25°C
I
IB
V
= 2.5 V
IC
70°C
0 to
25°C
V
− 1
DD
V
ICR
Common-mode input voltage range
V
0 to
0°C to 70°C
V
− 1.5
DD
25°C
70°C
84
84
84
85
85
85
4.7
CMRR Common-mode rejection ratio
V
V
= V min
dB
dB
IC
ICR
0°C
25°C
70°C
k
Supply-voltage rejection ratio
= 5 V to 10 V
DD
SVR
0°C
25°C
4.5
4.3
V
V
I
High-level output voltage
V
V
= 1 V,
I
I
= −4 mA
= 4 mA
V
OH
ID
OH
70°C
25°C
210
35
300
375
80
Low-level output voltage
= −1 V,
mV
µA
OL
ID
OH
70°C
25°C
Supply current (all four comparators)
Outputs low,
No load
DD
0°C to 70°C
100
†
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
recommended operating conditions
TLC3704I
MIN NOM
UNIT
MAX
Supply voltage, V
3
5
16
V
V
DD
Common-mode input voltage, V
− 0.2
V
DD
− 1.5
IC
High-level output current, I
− 20
20
mA
mA
°C
OH
OL
Low-level output current, I
Operating free-air temperature, T
− 40
85
A
electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless
otherwise noted)
TLC3704I
PARAMETER
Input offset voltage
Input offset current
Input bias current
T
UNIT
TEST CONDITIONS
A
MIN
TYP
MAX
V
V
= 5 V to 10 V,
25°C
−40°C to 85°C
25°C
1.2
5
7
DD
V
IO
mV
= V min,
See Note 3
IC
ICR
1
5
pA
nA
pA
nA
I
IO
V
IC
= 2.5 V
= 2.5 V
85°C
1
2
25°C
I
IB
V
IC
85°C
0 to
25°C
V
− 1
DD
V
ICR
Common-mode input voltage range
V
0 to
−40°C to 85°C
V
− 1.5
DD
25°C
85°C
84
84
83
85
85
83
4.7
CMRR Common-mode rejection ratio
V
V
= V min
dB
dB
IC
ICR
−40°C
25°C
85°C
k
Supply-voltage rejection ratio
= 5 V to 10 V
DD
SVR
−40°C
25°C
4.5
4.3
V
V
I
High-level output voltage
Low-level output voltage
V
V
= 1 V,
I
I
= −4 mA
= 4 mA
V
OH
ID
OH
85°C
25°C
210
35
300
400
80
= −1 V,
mV
µA
OL
ID
OH
85°C
25°C
Supply current (all four comparators) Outputs low,
No load
DD
−40°C to 85°C
125
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
recommended operating conditions
TLC3704M
MIN NOM
UNIT
MAX
Supply voltage, V
4
0
5
16
V
V
DD
Common-mode input voltage, V
V
DD
− 1.5
IC
High-level output current, I
− 20
20
mA
mA
°C
OH
OL
Low-level output current, I
Operating free-air temperature, T
− 55
125
A
electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless
otherwise noted)
TLC3704M
PARAMETER
Input offset voltage
Input offset current
Input bias current
T
UNIT
TEST CONDITIONS
A
MIN
TYP
MAX
5
V
V
= 5 V to 10 V,
25°C
−55°C to 125°C
25°C
1.2
DD
V
IO
mV
= V min,
See Note 3
10
IC
ICR
1
5
pA
nA
pA
nA
I
IO
V
IC
= 2.5 V
= 2.5 V
125°C
15
30
25°C
I
IB
V
IC
125°C
0 to
25°C
V
− 1
DD
V
ICR
Common-mode input voltage range
V
0 to
−55°C to 125°C
V
− 1.5
DD
25°C
125°C
84
83
82
85
85
82
4.7
CMRR Common-mode rejection ratio
V
V
= V min
dB
dB
IC
ICR
−55°C
25°C
125°C
k
Supply-voltage rejection ratio
= 5 V to 10 V
DD
SVR
−55°C
25°C
4.5
4.2
V
V
I
High-level output voltage
Low-level output voltage
V
V
= 1 V,
I
I
= −4 mA
= 4 mA
V
OH
ID
OH
125°C
25°C
210
35
300
500
80
= −1 V,
mV
µA
OL
ID
OH
125°C
25°C
Supply current (all four comparators) Outputs low,
No load
DD
−55°C to 125°C
175
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
recommended operating conditions
TLC3704Q
MIN NOM
UNIT
MAX
Supply voltage, V
3
5
16
V
V
DD
Common-mode input voltage, V
−0.2
V
DD
− 1.5
IC
High-level output current, I
− 20
20
mA
mA
°C
OH
OL
Low-level output current, I
Operating free-air temperature, T
− 40
125
A
electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless
otherwise noted)
TLC3704Q
PARAMETER
Input offset voltage
Input offset current
Input bias current
T
UNIT
TEST CONDITIONS
A
MIN
TYP
MAX
V
V
= 5 V to 10 V,
25°C
−40°C to 125°C
25°C
1.2
5
7
DD
V
IO
mV
= V min,
See Note 3
IC
ICR
1
5
pA
nA
pA
nA
I
I
V
IC
= 2.5 V
= 2.5 V
IO
125°C
15
30
25°C
V
IC
IB
125°C
25°C
0 to V − 1
DD
Common-mode input voltage
range
V
ICR
V
−40°C to 125°C 0 to V − 1.5
DD
25°C
125°C
−40°C
25°C
84
83
83
85
85
83
4.7
CMRR Common-mode rejection ratio
V
V
= V min
dB
IC
ICR
125°C
−40°C
k
Supply-voltage rejection ratio
= 5 V to 10 V
dB
SVR
DD
25°C
125°C
4.5
4.2
V
V
I
High-level output voltage
Low-level output voltage
V
V
= 1 V,
I
I
= −4 mA
= 4 mA
V
OH
ID
OH
25°C
210
35
300
500
80
= −1 V,
mV
µA
OL
ID
OH
125°C
25°C
Supply current (all four
comparators)
Outputs low,
No load
DD
−40°C to 125°C
175
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
switching characteristics, VDD = 5 V, TA = 25°C
TLC3704C, TLC3704I
TLC3704M, TLC3704Q
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
4.5
2.7
1.9
1.4
1.1
1.1
4
MAX
Overdrive = 2 mV
Overdrive = 5 mV
f = 10 kHz,
C = 50 pF
Overdrive = 10 mV
Overdrive = 20 mV
Overdrive = 40 mV
†
L
t
Propagation delay time, low-to-high-level output
µs
PLH
V = 1.4-V step at IN+
I
Overdrive = 2 mV
Overdrive = 5 mV
Overdrive = 10 mV
Overdrive = 20 mV
Overdrive = 40 mV
2.3
1.5
0.95
0.65
0.15
f = 10 kHz,
C = 50 pF
†
L
t
Propagation delay time, high-to-low-level output
µs
PHL
V = 1.4-V step at IN+
I
f = 10 kHz,
C = 50 pF
L
t
t
Fall time
Overdrive = 50 mV
Overdrive = 50 mV
50
ns
ns
f
f = 10 kHz,
C = 50 pF
L
Rise time
125
r
†
Simultaneous switching of inputs causes degradation in output response.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
PRINCIPLES OF OPERATION
LinCMOS process
The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply
applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions from
operational amplifiers to complex mixed-mode converters.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Direct further questions to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g., during board assembly. If a circuit in which one amplifier from a dual op amp is being
used and the unused pins are left open, high voltages tends to develop. If there is no provision for ESD
protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent
voltage buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI
ESD-protection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
V
DD
R1
Input
To Protected Circuit
R2
Q1
Q2
D1
D2
D3
GND
Figure 1. LinCMOS ESD-Protection Schematic
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to V . Q1 turns on when the voltage at the input rises
SS
above the voltage on the V pin by a value equal to the V of Q1. The base current increases through R2
DD
BE
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (V ∼ 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to V is
T
SS
now shunted through the n-channel enhancement-type MOSFET Q2 to V . If the voltage on the input pin
SS
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 to 27 V, which is well below the gate-
oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is − 0.3 V to −1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed V
and not damage the device
ICR
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
5 mA. Figures 2 and 3 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the V
pin and into the device I
or the V
supply through R2
DD
DD
DD
producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input
voltage is below the V of Q2.
T
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 4).
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
PRINCIPLES OF OPERATION
circuit-design considerations (continued)
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
8
7
10
9
T
A
= 25° C
T
A
= 25° C
8
7
6
5
6
5
4
3
2
1
0
4
3
2
1
0
V
V
DD
+ 4
V
DD
+ 8
V
DD
+ 12
V
− 0.3
V
DD
− 0.5
V
DD
− 0.7
V
DD
− 0.9
DD
DD
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 2
Figure 3
V
DD
R
I
Positive Voltage Input Current Limit :
V
I
+
1/2
TLC3704
VI * VDD * 0.3 V
RI
+
5 mA
−
V
ref
Negative Voltage Input Current Limit :
* VI * VDD * (* 0.3 V)
RI
+
5 mA
See Note A
NOTE A: If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required.
Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
The TLC3704 contains a digital output stage which, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo
loop which is designed to force the device output to a level within this linear region. Since the servo-loop method
of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset
voltage, common-mode rejection, etc.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high.
With the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages
can be slewed as shown in Figure 5(b) for the V
greater accuracy.
test, rather than changing the input voltages, to provide
ICR
5 V
1 V
+
+
−
−
Applied V
Applied V
IO
IO
Limit
Limit
V
O
V
O
− 4 V
(b) V WITH V = 4 V
(a) V WITH V = 0 V
IO
IC
IO
IC
Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal,
but opposite in polarity, to the input offset voltage, the output changes states.
Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates
a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any
residual d.c. offset. The signal is then applied to the inverting input of the comparator under test, while the
noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed
by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a
duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when
the voltage at the noninverting input exactly equals the input offset voltage.
Voltage divider R8 and R9 provides an increase in the input offset voltage by a factor of 100 to make
measurement easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading;
therefore, it is suggested that their tolerance level be one percent or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current
and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board
leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be
subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the
device.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
V
DD
C3
0.68 µF
R5
1.8 kΩ 1%
IC1a
1/4 TLC274CN
C2
Buffer
IC1c
1 µF
+
−
1/4 TLC274CN
R6
−
+
1 MΩ
DUT
−
+
V
IO
R4
47 kΩ
(X100)
R7
1.8 kΩ 1%
Integrator
R1
240 kΩ
C4
0.1 µF
IC1b
1/4 TLC274CN
−
+
C1
0.1 µF
Triangle
Generator
R8
10 kΩ 1%
R9
100 Ω 1%
R2
10 kΩ
R3
100 Ω
Figure 6. Circuit for Input Offset Voltage Measurement
Response time is defined as the interval between the application of an input step function and the instant when
the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from
the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the
trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected
by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as
shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV
overdrive, causes the output to change state.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION
V
DD
Pulse
Generator
µ
F
1
Ω
50
+
−
1 V
DUT
10 Ω
10-Turn
C
L
(see Note A)
Potentiometer
Ω
1 k
µ
F
0.1
− 1 V
TEST CIRCUIT
Overdrive
Overdrive
Input
100 mV
Input
100 mV
90%
50%
10%
90%
50%
10%
Low-to-High
Level Output
High-to-Low
Level Output
t
t
f
r
t
t
PHL
PLH
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 7. Response, Rise, and Fall Times Circuit and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input offset voltage
Input bias current
Distribution
8
9
IO
I
IB
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
CMRR Common-mode rejection ratio
10
11
k
Supply-voltage rejection ratio
SVR
vs Free-air temperature
vs High-level output current
12
13
V
High-level output current
OH
OL
vs Low-level output current
vs Free-air temperature
14
15
V
Low-level output voltage
t
Output transition time
vs Load capacitance
16
17
18
19
20
21
t
Supply current response to an output voltage transition
Low-to-high-level output response for various input overdrives
High-to-low-level output response for various input overdrives
Low-to-high-level output response time
t
t
vs Supply voltage
vs Supply voltage
PLH
High-to-low-level output response time
PHL
vs Frequency
vs Supply voltage
vs Free-air temperature
22
23
24
I
Supply current
DD
INPUT BIAS CURRENT
vs
DISTRIBUTION OF INPUT
OFFSET VOLTAGE†
FREE-AIR TEMPERATURE†
10
200
180
160
140
V
V
T
= 5 V
= 2.5 V
= 25° C
V
V
= 5 V
= 2.5 V
DD
IC
A
DD
IC
698 Units Tested
From 4 Wafer Lots
1
0.1
120
100
80
60
40
20
0.01
0.001
0
25
50
75
100
125
−5 −4 −3 −2 −1
0
1
2
3
4
5
T
A
− Free-Air Temperature − °C
V
IO
− Input Offset Voltage − mV
Figure 8
Figure 9
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS†
COMMON-MODE REJECTION RATIO
SUPPLY VOLTAGE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
90
88
86
84
82
80
78
76
90
88
86
84
82
V
DD
= 5 V
V
DD
= 5 V to 10 V
80
78
76
74
72
70
74
72
70
−75 −50 −25
0
25
50
75
100 125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 10
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
V
5
4.95
4.9
DD
V
OH
= 5 V
DD
I
= − 4 mA
−0.25
V
DD
= 16 V
10 V
−0.5
4.85
4.8
−0.75
4.75
−1
5 V
4.7
−1.25
4.65
4 V
−1.5
4.6
4.55
4.5
3 V
−1.75
−2
T
A
= 25°C
0
−2.5 −5 −7.5 −10 −12.5 −15 −17.5 −20
−75 −50 −25
0
25
50
75
100
125
I
− High-Level Output Current − mA
T
A
− Free-Air Temperature − °C
OH
Figure 12
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.5
400
350
300
250
200
150
100
T
A
= 25°C
3 V
V
I
= 5 V
= 4 mA
DD
4 V
1.25
OL
1
5 V
0.75
10 V
0.5
0.25
V
DD
= 16 V
50
0
0
0
2
4
6
8
10 12 14 16 18
20
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
I
− Low-Level Output Current − mA
OL
Figure 14
Figure 15
OUTPUT TRANSITION TIME
vs
SUPPLY CURRENT RESPONSE
TO AN OUTPUT VOLTAGE TRANSITION
LOAD CAPACITANCE
250
225
200
V
= 5 V
DD
L
V
T
= 5 V
= 25°C
DD
A
C = 50 pF
f = 10 kHz
10
Rise Time
175
150
125
100
75
5
0
5
0
Fall Time
50
25
0
0
200
400
600
800
1000
t − Time
C − Load Capacitance − pF
L
Figure 16
Figure 17
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS
HIGH-TO-LOW-LEVEL OUTPUT RESPONSE
FOR VARIOUS INPUT OVERDRIVES
LOW-TO-HIGH-LEVEL OUTPUT RESPONSE
FOR VARIOUS INPUT OVERDRIVES
5
5
40 mV
20 mV
10 mV
5 mV
40 mV
20 mV
10 mV
5 mV
2 mV
2 mV
0
100
0
0
100
0
V
T
= 5 V
= 25° C
DD
A
L
C = 50 pF
V
T
= 5 V
= 25° C
DD
A
L
C = 50 pF
0
1
2
3
4
5
0
1
2
3
4
5
t
− High-to-Low-Level Output
Response Time − µs
t
− Low-to-High-Level Output
Response Time − µs
PHL
PLH
Figure 18
Figure 19
LOW-TO-HIGH-LEVEL
HIGH-TO-LOW-LEVEL
OUTPUT RESPONSE TIME
vs
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
6
5
6
5
C = 50 pF
L
C = 50 pF
T
A
= 25°C
L
T
A
= 25°C
Overdrive = 2 mV
Overdrive = 2 mV
4
3
2
1
0
4
3
5 mV
5 mV
10 mV
2
10 mV
20 mV
20 mV
1
0
40 mV
6
40 mV
6
0
2
4
8
10
12
14
16
0
2
4
8
10
12
14
16
V
DD
− Supply Voltage − V
V
DD
− Supply Voltage − V
Figure 20
Figure 21
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS†
AVERAGE SUPPLY CURRENT
(PER COMPARATOR)
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
FREQUENCY
10000
1000
80
70
T
= − 55°C
Outputs Low
No Loads
A
T
= 25°C
A
L
C = 50 pF
T
A
= − 40°C
V
DD
= 16 V
60
50
40
30
20
10
0
T
A
= 25°C
10 V
5 V
T
A
= 125°C
100
10
4 V
T
= 85°C
A
3 V
0
2
4
6
8
10
12
14
16
0.01
0.1
1
10
100
V
DD
− Supply Voltage − V
f − Frequency − kHz
Figure 22
Figure 23
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
30
25
20
15
V
= 5 V
DD
No Load
Outputs Low
10
Outputs High
5
0
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
Figure 24
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
APPLICATION INFORMATION
The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic
discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the
input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the
common-mode range. For example, at 25°C with V = 5 V, both inputs must remain between − 0.2 V and 4 V to
DD
ensure proper device operation. To ensure reliable operation, the supply should be decoupled with a capacitor
(0.1 µF) that is positioned as close to the device as possible.
Output and supply current limitations should be watched carefully since the TLC3704 does not provide current
protection. For example, each output can source or sink a maximum of 20 mA; however, the total current to ground
can only be an absolute maximum of 60 mA. This prohibits sinking 20 mA from each of the four outputs simultaneously
since the total current to ground would be 80 mA.
The TLC3704 has internal ESD-protection circuits that prevents functional failures at voltages up to 2000 V as tested
under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure
to ESD may result in the degradation of the device parametric performance.
Table of Applications
FIGURE
Pulse-width-modulated motor speed controller
Enhanced supply supervisor
25
26
27
28
Two-phase nonoverlapping clock generator
Micropower switching regulator
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
APPLICATION INFORMATION
12 V
SN75603
Half-H Driver
DIR
EN
5 V
1/2 TLC3704
See
Note A
+
100 kΩ
+
10 kΩ
−
5 V
Motor
10 kΩ
10 kΩ
C1
−
1/2 TLC3704
0.01 µF
(see Note B)
12 V
SN75604
Half-H Driver
DIR
EN
5 V
10 kΩ
Motor Speed Control
Potentiometer
5 V
Direction
Control
S1
SPDT
NOTES: A. The recommended minimum capacitance is 10 µF to eliminate common ground switching noise.
B. Adjust C1 for change in oscillator frequency
Figure 25. Pulse-Width-Modulated Motor Speed Controller
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
APPLICATION INFORMATION
5 V
5 V
12 V
V
SENSE
RESET
GND
CC
3.3 kΩ
10 kΩ
To µP
1/2 TLC3704
12-V
Sense
+
−
TL7705A
Reset
RESIN
REF
1 kΩ
C
T
2.5 V
1 µF
C
T
(see Note B)
1/2 TLC3704
+
−
To µP Interrupt
Early Power Fail
R1
V
(UNREG)
(see Note A)
Monitors 5 VDC Rail
Monitors 12 VDC Rail
Early Power Fail Warning
R2
(R1 +R2)
NOTES: A.
V(UNREG) + 2.5
B. The value of C determines the time delay of reset.
R2
T
Figure 26. Enhanced Supply Supervisor
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
APPLICATION INFORMATION
12 V
R1
12 V
100 kΩ
(see Note B)
12 V
1/2 TLC3704
−
+
OUT1
OUT2
R2
5 kΩ
1/2 TLC3704
(see Note C)
−
+
100 kΩ
1/2 TLC3704
−
+
22 kΩ
C1
0.01 µF
(see Note A)
100 kΩ
100 kΩ
R3
100 kΩ
(see Note B)
12 V
OUT1
OUT2
NOTES: A. Adjust C1 for a change in oscillator frequency where:
1/f = 1.85(100 kΩ)C1
B. Adjust R1 and R3 to change duty cycle
C. Adjust R2 to change deadtime
Figure 27. Two-Phase Nonoverlapping Clock Generator
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC3704, TLC3704M
QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS117C − NOVEMBER 1986 − REVISED NOVEMBER 2009
APPLICATION INFORMATION
V
I
+ 6 V to 16 V
I
+ 0.01 mA to 0.25 mA
L
(R1 ) R2)
V
+ 2.5
O
R2
1/2 TLC3704
SK9504
(see Note C)
V
I
1/2 TLC3704
+
−
100 kΩ
G
S
V
−
I
100 kΩ
+
V
I
47 µF
D
100 kΩ
Tantalum
+
C1
IN5818
180 µF
(see Note A)
100 kΩ
R = 6 Ω
L = 1 mH
(see Note D)
R1
V
O
100 kΩ
TLC271
(see Note B)
V
I
R
L
470 µF
+
−
R2
100 kΩ
C2
100 pF
100 kΩ
270 kΩ
V
I
LM385
2.5 V
NOTES: A. Adjust C1 for a change in oscillator frequency
B. TLC271 − Tie pin 8 to pin 7 for low bias operation
C. SK9504 − VDS = 40 V
IDS = 1 Awill
D. To achieve microampere current drive, the inductance of the circuit must be increased.
Figure 28. Micropower Switching Regulator
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
5962-9096901M2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9096901M2A
TLC3704
MFKB
5962-9096901MCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9096901MC
A
TLC3704MJB
TLC3704CD
TLC3704CDR
TLC3704CDRG4
TLC3704CN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
14
14
14
14
14
14
14
50
2500
2500
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TLC3704C
TLC3704C
TLC3704C
TLC3704CN
TLC3704
P3704
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Pb-Free
(RoHS)
TLC3704CNSR
TLC3704CPW
TLC3704CPWG4
SO
NS
PW
PW
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
P3704
TLC3704CPWLE
TLC3704CPWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P3704
TLC3704CPWRG4
TLC3704ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SOIC
SOIC
SOIC
SOIC
PW
D
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
P3704
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TLC3704I
TLC3704I
TLC3704I
TLC3704I
TLC3704IDG4
TLC3704IDR
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
Green (RoHS
& no Sb/Br)
TLC3704IDRG4
D
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLC3704IN
TLC3704IPW
ACTIVE
PDIP
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
N
14
14
14
14
14
14
14
14
14
20
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC3704IN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
PW
PW
PW
D
90
90
Green (RoHS
& no Sb/Br)
-40 to 85
P3704I
TLC3704IPWG4
TLC3704IPWR
TLC3704IPWRG4
TLC3704MD
Green (RoHS
& no Sb/Br)
-40 to 85
P3704I
2000
2000
50
Green (RoHS
& no Sb/Br)
-40 to 85
P3704I
Green (RoHS
& no Sb/Br)
-40 to 85
P3704I
Green (RoHS
& no Sb/Br)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
TLC3704MD
PJ3704M
TLC3704MD
PJ3704M
TLC3704MDG4
TLC3704MDR
TLC3704MDRG4
TLC3704MFKB
SOIC
D
50
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
1
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
LCCC
FK
TBD
5962-
9096901M2A
TLC3704
MFKB
TLC3704MJ
ACTIVE
ACTIVE
CDIP
CDIP
J
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TLC3704MJ
TLC3704MJB
5962-9096901MC
A
TLC3704MJB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC3704, TLC3704M :
Catalog: TLC3704
•
Automotive: TLC3704-Q1, TLC3704-Q1
•
Military: TLC3704M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Military - QML certified for Military and Defense Applications
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC3704CDR
TLC3704CNSR
TLC3704CPWR
TLC3704IDR
SOIC
SO
D
NS
PW
D
14
14
14
14
14
14
14
2500
2000
2000
2500
2000
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
12.4
16.4
12.4
16.4
16.4
6.5
8.2
6.9
6.5
6.9
6.5
6.5
9.0
10.5
5.6
9.0
5.6
9.0
9.0
2.1
2.5
1.6
2.1
1.6
2.1
2.1
8.0
12.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
12.0
16.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
TSSOP
SOIC
TSSOP
SOIC
SOIC
TLC3704IPWR
TLC3704MDR
TLC3704MDRG4
PW
D
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC3704CDR
TLC3704CNSR
TLC3704CPWR
TLC3704IDR
SOIC
SO
D
NS
PW
D
14
14
14
14
14
14
14
2500
2000
2000
2500
2000
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
35.0
38.0
35.0
38.0
38.0
TSSOP
SOIC
TSSOP
SOIC
SOIC
TLC3704IPWR
TLC3704MDR
TLC3704MDRG4
PW
D
D
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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