TLC374 [TI]
LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS; LinCMOSE四路差动比较仪
| 型号： | TLC374 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS |
| 文件： | 总18页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
Single- or Dual-Supply Operation
D, J, N, OR PW PACKAGE
(TOP VIEW)
Wide Range of Supply Voltages
2 V to 18 V
1OUT
2OUT
3OUT
4OUT
GND
4IN+
4IN–
3IN+
3IN–
1
2
3
4
5
6
7
14
13
12
11
10
9
Very Low Supply Current Drain 0.3 mA Typ
at 5 V
V
DD
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
2IN–
2IN+
1IN–
1IN+
Built-In ESD Protection
12
High Input Impedance . . . 10 Ω Typ
8
Extremely Low Input Bias Current 5 pA Typ
Ultrastable Low Input Offset Voltage
FK PACKAGE
(TOP VIEW)
Input Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/Month,
Including the First 30 Days
Common-Mode Input Voltage Range
Includes Ground
3
4
2
1
20 19
18
GND
V
DD
NC
NC
2IN–
NC
17
16
15
14
5
6
7
8
Outputs Compatible With TTL, MOS, and
CMOS
4IN+
NC
Pin-Compatible With LM339
4IN–
2IN+
9 10 11 12 13
description
These quadruple differential comparators are
fabricated using LinCMOS technology and
NC – No internal connection
consist of four independent voltage comparators
designed to operate from a single power supply.
Operation from dual supplies is also possible if the
difference between the two supplies is 2 V to 18 V.
symbol (each comparator)
IN+
IN–
Each device features extremely high input
OUT
12
impedance (typically greater than 10
Ω),
allowing direct interfacing with high-impedance
sources. The outputs are n-channel open-drain
configurations and can be connected to achieve
positive-logic wired-AND relationships.
The TLC374 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 1000-V
ESD rating using human body model testing. However, care should be exercised in handling this device as
exposure to ESD may result in degradation of the device parametric performance.
The TLC374C is characterized for operation from 0°C to 70°C. The TLC374I is characterized for operation from
–40° to 85°C. The TLC374M is characterized for operation over full military temperature range of
–55°C to 125°C. The TLC374Q is characterized for operation from –40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
FORM
(Y)
V
max
IO
T
A
SMALL OUTLINE CHIP CARRIER CERAMIC DIP
PLASTIC DIP
(N)
TSSOP
(PW)
AT 25°C
(D)
(FK)
(J)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
–40°C to 125°C
5 mV
5 mV
5 mV
5 mV
TLC374CD
TLC374ID
TLC374MD
TLC374QD
—
—
TLC374CN
TLC374IN
TLC374MN
TLC374QN
TLC374CPW TLC374Y
—
TLC374MFK
—
—
TLC374MJ
—
—
—
—
—
—
—
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC374CDR).
equivalent schematic (each comparator)
Common to All Channels
V
DD
OUT
GND
IN+
IN–
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
TLC374Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC374C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
V
DD
(3)
BONDING PAD ASSIGNMENTS
(7)
(6)
(13)
1IN+
1IN–
(12)
(11)
+
–
(10)
(9)
(1)
1OUT
(5)
(4)
+
2IN+
2IN–
(2)
2OUT
3IN+
–
(14)
(1)
(9)
(8)
+
–
(8)
(7)
(14)
3OUT
65
3IN–
(11)
(10)
+
–
4IN+
4IN–
(13)
4OUT
(12)
GND
(6)
(4)
(3)
(5)
(2)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
90
T
= 150°C
JMAX
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
ID
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
I
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 18 V
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TLC374C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC374I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC374M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
TLC374Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Case temperature range for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: D, N, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. Short circuits from outputs to V
can cause excessive heating and eventual device destruction.
DD
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
DERATE
ABOVE T
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
POWER RATING POWER RATING POWER RATING
A
D
FK
J
500 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
5.6 mW/°C
84°C
104°C
104°C
95°C
—
500 mW
500 mW
500 mW
500 mW
448 mW
494 mW
500 mW
500 mW
500 mW
—
190 mW
269 mW
269 mW
224 mW
—
500 mW
500 mW
N
500 mW
PW
700 mW
recommended operating conditions
TLC374C
MIN MAX
TLC374I
TLC374M
MIN MAX
TLC374Q
UNIT
V
MIN MAX
MIN MAX
Supply voltage, V
DD
3
0
0
0
16
3.5
8.5
70
3
0
16
3.5
8.5
85
4
0
16
3.5
8.5
125
3
0
16
3.5
8.5
125
V
V
= 5 V
DD
Common-mode input voltage, V
V
IC
= 10 V
0
0
0
DD
Operating free-air temperature, T
–40
–55
–40
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, V
= 5 V
DD
TLC374C
TLC374I
TYP MAX
TLC374M
TYP MAX
†
PARAMETER
Input offset voltage
Input offset current
Input bias current
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
MIN
25°C
Full range
25°C
1
1
5
5
1
5
7
1
1
5
5
V
IO
V
IC
= V
min, See Note 4
ICR
mV
6.5
10
1
5
pA
nA
pA
nA
I
IO
MAX
0.3
0.6
1
2
10
20
25°C
I
IB
MAX
0 to
0 to
0 to
25°C
V
–1
V
–1
V
–1
DD
DD
DD
Common-mode input
voltage range
V
ICR
V
0 to
0 to
0 to
Full range
V
–1.5
V
–1.5
V
–1.5
DD
DD
DD
V
V
= 5 V
25°C
0.1
0.1
0.1
nA
OH
I
High-level output current
V
ID
= 1 V
OH
= 15 V Full range
1
400
700
1
400
700
1
400
700
µA
OH
25°C
150
150
150
V
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 4 mA
mV
mA
µA
OL
OL
Full range
25°C
I
I
V
OL
= 1.5 V
6
16
6
16
6
16
OL
25°C
300
600
800
300
600
800
300
600
800
Supply current
(four comparators)
No load
DD
Full range
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC374C, –40°C to 85°C for TLC374I, and –55°C to
125°C for the TLC374M, and –40°C to 125°C for TLC374Q. MAX is 70°C for TLC374C, 85°C TLC374I, and 125°C for the TLC374M, and 125°C for TLC374Q. IMPORTANT: See
Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and V . They can
DD
be verified by applying the limit value to the input and checking for the appropriate output state.
switching characteristics, V
= 5 V, T = 25°C
A
DD
TLC374C, TLC374I
TLC374M, TLC374Q
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
650
200
MAX
100-mV input step with 5-mV overdrive
TTL-level input step
R
C
connected to 5 V through 5.1 kΩ,
L
L
Response time
ns
‡
= 15 pF ,
See Note 5
‡
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
electrical characteristics at specified free-air temperature, V
noted)
= 5 V, T = 25°C (unless otherwise
DD
A
TLC374Y
UNIT
PARAMETER
TEST CONDITIONS
= V min, See Note 4
MIN
TYP
MAX
V
IO
Input offset voltage
V
1
1
5
5
mV
pA
pA
V
IC
ICR
I
I
Input offset current
IO
Input bias current
IB
V
ICR
Common-mode input voltage range
High-level output current
Low-level output voltage
Low-level output current
Supply current (four comparators)
0 to V
–1
DD
I
V
ID
V
ID
V
ID
V
ID
= 1 V,
V
= 5 V
0.1
150
16
nA
mV
mA
µA
OH
OH
= 4 mA
V
OL
= –1 V,
= –1 V,
=1 V,
I
400
600
OL
I
I
V
= 1.5 mV
6
OL
OL
No load
300
DD
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and V . They can be verified by applying the limit value to the input and checking for the appropriate output state.
DD
switching characteristics, V
= 5 V, T = 25°C
A
DD
TLC374Y
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
100-mV input step with 5-mV overdrive
TTL-level input step
650
R
C
connected to 5 V through 5.1 kΩ,
L
L
Response time
ns
†
= 15 pF ,
See Note 5
200
†
C
includes probe and jig capacitance.
L
NOTE 4: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC374 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V
accuracy.
test, rather than changing the input voltages, to provide greater
ICR
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but
opposite in polarity to the input offset voltage, the output changes state.
5 V
1 V
5.1 kΩ
5.1 kΩ
Applied V
Limit
Applied V
Limit
IO
IO
V
O
V
O
–4 V
(a) V WITH V = 0
IO IC
(b) V WITH V = 4 V
IO
IC
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
C3
0.68 µF
R5
1.8 kΩ, 1%
V
DD
U1b
1/4 TLC274CN
C2
1 µF
U1c
1/4 TLC274CN
R6
5.1 kΩ
Buffer
+
–
DUT
–
V
R4
47 kΩ
IO
(X100)
R7
1 MΩ
+
R1
Integrator
240 kΩ
C4
R8
0.1 µF
1.8 kΩ, 1%
U1a
+
–
1/4 TLC274CN
C1
0.1 µF
Triangle
Generator
R9
10 kΩ, 1%
R10
100 Ω, 1%
R2
10 kΩ
R3
100 kΩ
Figure 2. Test Circuit for Input Offset Voltage Measurement
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the trailing
edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input
offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3)
so that the circuit is just at the transition point. Then a low signal, for example, 105-mV or 5-mV overdrive, causes
the output to change state.
V
DD
1 µF
5.1 kΩ
Pulse Generator
OUT
C
L
50 Ω
(see Note A)
1 V
Input
Offset Voltage
Compensation
Adjustment
10 Ω
10 Turn
1 kΩ
0.1 µF
–1 V
TEST CIRCUIT
Overdrive
Input
100 mV
Overdrive
Input
100 mV
90%
10%
90%
50%
10%
50%
Low-to-High-
Level Output
High-to-Low-
Level Output
t
t
t
f
r
t
PLH
PLH
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Response, Rise, and Fall Times Test Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
LinCMOS process
LinCMOS process is a linear polysilicon-gate complimentary-MOS process. Primarily designed for single-
supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog
functions from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational
amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision
for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.
To prevent voltage buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than normal operating voltages but lower than the breakdown voltage
of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting
transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on
the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of
picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of TI’s
ESD-protection circuit is presented on the next page.
All input an output pins of LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
V
DD
R1
Input
To Protected Circuit
R2
Q1
Q2
D1
D2
D3
V
SS
Figure 4. LinCMOS ESD-Protection Schematic
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
Input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to V . Q1 turns on when the voltage at the input rises
SS
above the voltage on V
by a value equal to the V of Q1. The base current increases through R2 with input
DD
EB
current as Q1 saturates. The base current through R2 as Q1 saturates forces the voltage at the drain and gate
of Q2 to exceed its threshold level (V 22 to 26 V) and turn on Q2. The shunted input current through Q1 to
is now shunted through the n-channel enhancement-type MOSFET Q2 to V . If the voltage on the input
T
V
SS
SS
pin continues to rise, the breakdown voltage of d3 is exceeded and all remaining energy is dissipated in R1 and
D3. The breakdown voltage of D3 is designed to be 24 V to 27 V, which is well below the gate oxide voltage of
the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward-biased. The voltage seen by the protected circuit is –0.3 V to –1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuits environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed V
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
and not damage the device
ICR
±5 mA. Figures 5 and 6 show typical characteristics for input voltage vs input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. The input current should be externally limited even through internal positive current limiting is
achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This current is forced into the V
the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input voltage is below
pin and into the device I
or the V
supply through R2 producing
DD
DD
DD
the V of Q2.
T
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2,
and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp
is required (see Figure 7).
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
†
†
8
7
10
9
T
A
= 25°C
T
A
= 25°C
8
6
5
7
6
4
5
4
3
2
3
2
1
0
1
0
V
DD
V
DD
+4
V
DD
+8
V
DD
+12
V
– 0.3
V
DD
– 0.5
V
DD
– 0.7
V
DD
– 0.9
DD
V – Input Voltage – V
I
V – Input Voltage – V
I
†
†
The dashed line identifies an area of operation where some
degradation of parametric performance may be experienced.
The dashed line identifies an area of operation where some
degradation of parametric performance may be experienced.
Figure 5
Figure 6
V
DD
Positive Voltage Input Current Limit:
R
L
R
+V – V
– 0.3 V
1/4
L
I
DD
5 mA
Negative Voltage Input Current Limit:
–V – V – (0.3 V)
R =
I
TLC374
V
I
+
–
V
REF
I
DD
5 mA
R =
I
See Note A
NOTE A: If the correct output state is required when the negative input exceeds V , a Schotty clamp is required.
SS
Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
18 17 16 15 14 13 12
TERMINALS
MIN
MAX
MIN
MAX
**
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
21
22
23
24
25
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
B SQ
A SQ
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
MECHANICAL INFORMATION
CERAMIC DUAL-IN-LINE PACKAGE
J (R-GDIP-T**)
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
(19,94)
0.785
(19,94)
0.910
(23,10)
0.975
(24,77)
C
0.755
(19,18)
0.755
(19,18)
0.930
(23,62)
0.280
(7,11)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, and GDIP1-T20
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
MECHANICAL INFORMATION
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
DIM
14
16
18
20
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A MIN
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC374, TLC374Q, TLC374Y
LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS
SLCS118C – NOVEMBER 1983 – REVISED MARCH 1999
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,65
M
0,10
0,19
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
0,50
A
Seating Plane
0,10
1,20 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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