TLC4545IDGKG4 [TI]
5-V, LOW POWER, 16-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN; 5 -V ，低功耗， 16位， 200 KSPS ???串行模拟数字转换器具有自动掉电
| 型号： | TLC4545IDGKG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5-V, LOW POWER, 16-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN |
| 文件： | 总26页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢃꢅ ꢆ ꢀꢁ ꢂꢃ ꢄꢃ ꢄ
SLAS293 − DECEMBER 2001
ꢄ ꢇꢈꢆ ꢁꢉ ꢊ ꢋꢉ ꢊ ꢌꢍꢆ ꢅ ꢎ ꢇꢏꢐ ꢀꢆ ꢑ ꢒ ꢒ ꢇꢓꢔꢋ ꢔ
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FEATURES
APPLICATIONS
D
D
D
D
D
D
D
D
200-KSPS Sampling Rate
Built-In Conversion Clock
D
D
D
D
ATE System
Industrial Process Control
Measurement
INL: 2.5 LSB Max,
DNL: 2 to −1 LSB Max
Motor Control
DESCRIPTION
SINAD = 84.5 dB, SFDR = 95 dB,
THD = 94 dB at 15 kHz f , 200 KSPS
in
The TLC4541 and TLC4545 are a family of high
performance, 16-bit, low power, miniature CMOS
analog-to-digital converters (ADCs). These devices
operate from a single 5-V supply. Devices are available
with single, dual, or single pseudo-differential inputs. All
of these devices have a chip select (CS), serial clock
(SCLK), and serial data output (SDO) that provides a
direct 3-wire interface to the serial port of most popular
host microprocessors (SPI interface). When interfaced
with a DSP, a frame sync signal (FS) is used to indicate
the start of a serial data frame on either pin 1 (CS) or pin
7 (FS) for the TLC4541. The TLC4545 ADC connects
to the DSP via pin 1 only (CS).
SPI/DSP-Compatible Serial Interfaces With
SCLK Input up to 15 MHz
Single 5-V Supply
Rail-to-Rail Analog Input With 500 kHz BW
Two Input Options Available:
− TLC4541 − Single Channel Input
− TLC4545 − Single Channel,
Pseudo-differential Input
D
D
(TLC4541) Optimized DSP Interface −
Requires FS Input Only
Low Power With Auto-Power Down
− Operating Current: 3.5 mA
− Auto-Power Down Current: 5 µA
Pin Compatible 12/14/16-Bit Family in 8-Pin
SOIC and MSOP Packages
The TLC4541 and TLC4545 are designed to operate
with low power consumption. The power saving feature
is further enhanced with an auto-power down mode.
This product family features a high-speed serial link to
modern host processors with an external SCLK up to
15 MHz. Both families use a built-in oscillator as the
conversion clock, providing a 2.94 µs maximum
conversion time.
D
TLC4541
D OR DGK Package
(TOP VIEW)
TLC4545
D OR DGK Package
(TOP VIEW)
CS
REF
GND
AIN
1
2
3
4
8
7
6
5
SDO
FS
CS
REF
1
2
3
4
8
7
6
5
SDO
SCLK
V
GND
DD
V
DD
SCLK
AIN(+)
AIN(−)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001, Texas Instruments Incorporated
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1
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ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢃꢄ
SLAS293 − DECEMBER 2001
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
8-MSOP (DGK)
8-SOIC (D)
TLC4541ID
TLC4545ID
TLC4541IDGK (PKG Code = ALM)
TLC4545IDGK (PKG Code = AME)
−40°C to 85°C
functional block diagram
TLC4541
TLC4545
V
DD
V
DD
REF
AIN
REF
AIN (+)
LOW POWER
SAR ADC
LOW POWER
SAR ADC
S/H
SDO
S/H
SDO
AIN (−)
Conversion
Clock
Conversion
Clock
OSC
OSC
SCLK
CS
CONTROL
LOGIC
CONTROL
LOGIC
SCLK
CS
FS
GND
GND
2
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ꢀ ꢁꢂ ꢃ ꢄ ꢃꢅ ꢆ ꢀꢁ ꢂꢃ ꢄꢃ ꢄ
SLAS293 − DECEMBER 2001
Terminal Functions
TLC4541 single channel unipolar ADCs
TERMINAL
I/O
DESCRIPTION
NAME
NO.
4
AIN
CS
I
I
Analog input channel
1
Chip select. A high-to-low transition on the CS input removes SDO from a high-impedance state within a
maximum delay time. If the TLC4541 is attached to a dedicated TMS320 DSP serial port using the FS input,
CS can be grounded.
FS
7
3
8
I
I
DSP frame sync input. Indication of a start of a serial data frame. A low-to-high transition removes SDO from
the high-impedance state and the MSB is presented. Tie this pin to V
DD
if not used.
GND
SDO
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to
GND.
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when
CS is high. The output format is MSB first. Remaining data bits are presented on the rirsing edge of SCLK.
When FS is not active (FS = 1 at the falling edge of CS): The MSB is presented on the SDO pin on the falling
edge of CS after a maximum delay time. Data is valid on each falling edge of SCLK until all data is read.
When FS is active (FS = 0 at the falling edge of CS): The MSB is presented to the SDO output on the rising
edge of FS. Data is valid on the falling edge SCLK and changes on the rising edge SCLK (this is typically
used with an active FS from a DSP).
SDO returns to the high-impedance state after the 17th rising edge on SCLK. If a 17th SCLK cycle is not
presented, as is the case when using an SPI host, SDO returns to the high-impedance state on the rising
edge of CS.
SCLK
REF
5
2
6
I
I
I
Serial clock. This terminal receives the serial SCLK from the host processor.
External voltage reference input
V
DD
Positive supply voltage
TLC4545 single channel pseudo-differential ADCs
TERMINAL
I/O
DESCRIPTION
NAME
AIN0 (+)
NO.
4
I
I
I
Positive analog input for the TLC4545.
Inverted analog input for the TLC4545.
AIN1 (−)
CS
5
1
Chip select. A high-to-low transition on CS removes SDO from the high-impedance state within a maximum
delay time. The CS input can be connected to a DSP frame sync (FS) output when a dedicated TMS320 DSP
serial port is used.
GND
SDO
3
8
I
Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to
GND.
O
The 3-state serial data output for the A/D conversion result. SDO is kept in the high-impedance state when
CS is high and presents output data after the CS falling edge until the LSB is presented. The output format is
MSB first. The remaining data bits are presented on the rising edge of SCLK. Output data is valid on each
falling edge of SCLK until all data is read. SDO returns to the high-impedance state after the 17th rising edge
on SCLK. If a 17th SCLK cycle is not presented, as is the case when using an SPI host, SDO returns to the
high-impedance state on the rising edge of CS.
SCLK
REF
7
2
6
I
I
I
Serial clock. This terminal receives the serial SCLK from the host processor.
External voltage reference input
V
DD
Positive supply voltage
3
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ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢃꢄ
SLAS293 − DECEMBER 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, GND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5V
DD
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V +0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
DD
DD
DD
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
J
Operating free-air temperature range: T (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
V
Supply voltage, V
Frequency, SCLK
4.5
5
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
100
15000
24
kHz
ps
Tolerable clock jitter, SCLK
Aperature jitter
100
ps
External reference voltage input, V
4
100
20
V
V
REF
DD
V
DD
V
DD
V
DD
= 5 V, CS = 1, SCLK = 0
MΩ
kΩ
mA
V
REF
input impedance
= 5 V, CS = 0, SCLK = 15 MHz
25
External reference input current
= V
REF
= 4.5 V, CS=0, SCLK = 15 MHz
0.02
1
AIN, AIN(+)
AIN(−)
0
−0.2
2.1
V
DD
0.2
Analog input voltage
V
High level control input voltage, V
V
V
IH
Low level control input voltage, V
IL
0.8
85
Operating free-air temperature, T
TLC4541/45I
−40
°C
A
4
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SLAS293 − DECEMBER 2001
electrical characteristics over recommended operating free-air temperature range,
= 5 V, V = 4.096 V, SCLK frequency = 15 MHz (unless otherwise noted)
V
DD
REF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
OH
High-level output voltage
Low-level output voltage
V
V
V
V
= 4.5 V,
= 4.5 V,
I
OH
= −0.2 mA
= 0.8 mA
3.9
DD
V
OL
I
0.4
2.5
V
DD
OL
= V
DD
,
CS = V
1
−1
Off-state output current
(high-impedance-state)
O
O
DD
DD
I
µA
OZ
= 0,
CS = V
−2.5
2.5
I
I
I
High-level input current
Low-level input current
Operating supply current
V = V
I DD
0.005
−0.005
µA
µA
IH
V = 0
I
2.5
IL
CS at 0 V,
V
DD
= 4.5 V to 5.5 V
3.5
mA
CC
For all digital inputs, 0≤ V ≤ 0.3 V or
I
I
Power-down supply current
V
V
≥ V
DD
DD
− 0.3 V, SCLK=V
= 4.5 V to 5.5 V
,
3
5
µA
µA
CC(PD)
I
DD
Selected channel at V
DD
1
−1
Selected analog input channel
leakage current
Selected channel at 0 V
Analog inputs
11
20
14
C
Input capacitance
Input resistance
pF
i
Control Inputs
25
Z
V
DD
= 5.5 V
500
Ω
i
ac specifications (TLC4541/45)
PARAMETER
TEST CONDITIONS
f = 15 kHz at 200 KSPS
MIN
TYP
84.5
85
MAX
UNIT
SINAD Signal-to-noise ratio + distortion
I
dB
SNR
Signal-to-noise ratio
f = 15 kHz at 200 KSPS
I
TLC4541
TLC4545
f = 15 kHz at 200 KSPS
−94
−94
13.7
−95
−95
1
−87
−89
I
THD
Total harmonic distortion
Effective number of bits
dB
f = 15 kHz at 200 KSPS
I
ENOB
f = 15 kHz at 200 KSPS
I
Bits
TLC4541
TLC4545
f = 15 kHz at 200 KSPS
I
−87
−89
SFDR
Spurious free dynamic range
dB
f = 15 kHz at 200 KSPS
I
Full power bandwidth, −3 dB, analog input
Full power bandwidth, −1 dB, analog input
MHz
kHz
dB
500
Crosstalk
0.25 LBS
80
dc specifications (TLC4541/45)
†
PARAMETER
TEST CONDITIONS
MIN TYP
−2.5
−1
MAX
2.5
2
UNIT
LSB
LSB
INL
Integral linearity error (see Note 1)
Differential linearity error
DNL
TLC4541
TLC4545
TLC4541
TLC4545
−3.5
−1
3.5
1
E
Offset error (see Note 2)
Gain error (see Note 2)
mV
mV
O
G
−2
2
E
−1.8
1.8
†
All typical values are at V
DD
= 5 V, T = 25°C.
A
NOTES: 1. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.
2. Zero error is the difference between 0000h and the converted output for zero input voltage: full-scale error is the difference between
ideal full-scale and the converted output for full-scale input voltage.
5
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SLAS293 − DECEMBER 2001
timing requirements, V
= 5 V, V
= 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified)
DD
REF
MIN
66
27
27
3
TYP
MAX
10000
5000
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLK cycle time, V = 4.5 V to 5.5 V (see Note 3)
DD
cyc(SCLK)
Pulse width, SCLK low
Pulse width, SCLK high
ns
w1
5000
ns
w2
Hold time, CS high after SCLK falling edge
Setup time, CS falling edge before the first SCLK falling edge
Hold time, CS low after 16th SCLK falling edge
Pulse width, CS high
ns
h1
15
5
ns
su1
h2
ns
0.5
SCLKs
ns
w3
Delay time, CS falling edge to SDO MSB valid, V
DD
= V
REF
= 4.5 V, 20 pF
= V = 4.5 V, 20 pF
12
17
15
20
d1
Delay time, SCLK rising edge to next SDO data bit valid, V
DD
th
Delay time, 17 SCLK rising edge to SDO 3-stated, V
DD
ns
d2
REF
= 4.5 V, 20 pF (see Note 4)
= V
REF
ns
d3
Setup time, CS falling edge before FS rising edge (TLC4541 only)
Pulse width, FS high (TLC4541 only)
0.5
0.5
12.5
5
1
1
SCLKs
SCLKs
ns
su3
w4
Setup time, FS rising edge before SCLK falling edge (TLC4541 only)
Hold time, FS high after SCLK falling edge (TLC4541 only)
su4
h4
ns
Setup time, FS falling edge before 1st SCLK falling edge (TLC4541 only)
12
ns
su5
d4
Delay time, FS rising edge to SDO MSB valid, (V
Hold time, CS low after 1st SCLK falling edge
= V
REF
= 4.5 V, 20 pF TLC4541 only)
15
ns
DD
5
5
ns
h6
Setup time, CS rising edge before 9th (or the last) SCLK falling edge
Hold time, FS low after 1st SCLK falling edge (TLC4541 only)
Setup time, FS rising edge before 9th (or the last) SCLK falling edge
Active CS/FS cycle time, SCLK falling edges required to initialize ADC
Conversion time (22 conversion clocks based on 7.5-MHz to 12-MHz OSC)
Sample time, 20 SCLKs, SCLK up to 15 MHz
ns
su6
h7
5
ns
5
ns
su7
cyc(reset)
conv
s
1
8
2.94
200
SCLKs
µs
1.83
1.33
µs
NOTES: 3. Timing specifications given for 40/60 to 60/40 duty cycle
4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS edge if a 17th SCLK is not
presented.
6
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SLAS293 − DECEMBER 2001
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
2.5
1.5
0.5
−0.5
−1.5
−2.5
0
10000
20000
30000
Code
40000
50000
60000
Figure 1
INTEGRAL NONLINEARITY
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
10000
20000
30000
Code
40000
50000
60000
Figure 2
7
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SLAS293 − DECEMBER 2001
TYPICAL CHARACTERISTICS
FFT
0
FFT = 15 kHz,
= V = 5 V,
200 KSPS
−20
−40
−60
−80
V
DD
REF
−100
−120
−140
−160
0
20
10
30
40
50
60
70
80
90
100
f − Input Frequency − kHz
i
Figure 3
FFT
0
FFT = 1.5 kHz,
= V = 5 V,
200 KSPS
−20
−40
−60
−80
V
DD
REF
−100
−120
−140
−160
0
10
20
30
40
50
60
70
80
90
100
f − Input Frequency − kHz
i
Figure 4
8
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SLAS293 − DECEMBER 2001
TYPICAL CHARACTERISTICS
SIGNAL-TO NOISE RATIO
TOTAL HARMONIC DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
88
−80
−82
−84
−86
−88
−90
−92
−94
−96
V
DD
= V
REF
= 5 V
V
DD
= V = 5 V
REF
86
84
82
80
78
76
74
72
70
−98
−100
0
20
40
60
80
100
120
0
20
40
60
80
100
120
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 5
Figure 6
TOTAL HARMONIC DISTORTION
vs
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
−82
−84
−86
86
85.9
85.8
f = 1 kHz
i
f = 100 kHz
i
f = 15 kHz
i
85.7
85.6
85.5
−88
−90
−92
85.4
85.3
85.2
85.1
f = 15 kHz
i
−94
−96
−98
f = 1 kHz
i
−40 −25 −10
5
20
35
50
65
80
−40 −25 −10
5
20
35
50
65
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 7
Figure 8
9
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SLAS293 − DECEMBER 2001
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
vs
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
−97.5
−98.0
86.6
86.4
86.2
86.0
85.8
85.6
85.4
85.2
85.0
84.8
84.6
f = 1.5 kHz, 200 KSPS
i
−98.5
−99.0
−99.5
−100.0
−100.5
−101.0
4.0
4.5
5.0
4.0
4.5
5.0
V
REF
− Reference Voltage − V
V
REF
− REFERENCE VOLTAGE − V
Figure 9
Figure 10
MAXIMUM DIFFERENTIAL NONLINEARITY
MINIMUM DIFFERENTIAL NONLINEARITY
vs
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
−0.5
−1.0
−0.5
−1.0
4.0
4.5
5.0
4.5
5.0
4.0
V
REF
− Reference Voltage − V
V
REF
− Reference Voltage − V
Figure 11
Figure 12
10
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SLAS293 − DECEMBER 2001
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
4.0
4.5
5.0
V
REF
− Reference Voltage − V
Figure 13
11
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SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
control and timing
device initialization/RESET cycle
The TLC4541/45 each require one RESET cycle after power-on for initialization in order to operate properly.
This RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK
falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS
high. If a valid RESET cycle is issued, the data presented on the SDO output during the following cycle is FF00h.
This output code is useful in determining when a valid reset/initialization has occurred.
The TLC4541 has separate CS and FS pins. In this case, it is also possible to initiate the RESET cycle by
asserting FS low if CS is already low. The RESET cycle can be terminated by either asserting CS high (as shown
in the first RESET cycle in Figure 14), or by asserting FS high ( as shown in the second RESET cycle in Figure
14), whichever happens first.
1
8
2
1
2
8
1
16
1
4
4
SCLK
t
cyc(reset)
OR
CS
FS
t
FS High for Valid Initialization
cyc(reset)
1−8 Falling SCLK Edges−
ADC is Initialized
Normal Cycle−Sample
and Convert
Normal Cycle−Sample
and Convert
t
(PWRDWN)
SDO
MSB
LSB−3 LSB
1111−1111−0000−0000
SDO Data−Reset of Previous cycle’s Sample
For TLC45xx−LSB Presented on 16th Rising SCLK Edge
Figure 14. TLC4541/45 Initialization Timing
sampling
The converter sample time is 20 SCLKs in duration, beginning on the 5th SCLK received during an active signal
on the CS input (or FS input for the TLC4541.)
conversion
Each device completes a conversion in the following manner. The conversion is started after the 24th falling
SCLK edge. The CS input can be released at this point or at any time during the remainder of the conversion
cycle. The conversion takes a maximum of 2.94 µs to complete. Enough time (for conversion) should be allowed
before the next falling edge on the CS input (or rising edge on the FS input for the TLC4541) so that no
conversion is terminated prematurely. If the conversion cycle is terminated early, the data presented on SDO
during the following cycle is FF00h. This predefined output code is helpful in determining if the cycle time is not
long enough to complete the conversion. The same code is also used to determine if a reset cycle is valid.
For all devices, the SDO data presented during a cycle is the result of the conversion of the sample taken during
the previous cycle. The output data format is shown in the following table.
SERIAL OUTPUT DATA FORMAT
MSB [D15:D2]
LSB [D1:D0]
TLC4541/45
Conversion Result (OD15−OD2)
Conversion Result (OD1 − OD0)
12
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SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
control and timing (continued)
sampling and conversion cycle
TLC4541:
Control via pin 1, CS (FS = 1 at the falling edge of CS)− The falling edge of CS is the start of the cycle.
Transitions on CS can occur when SCLK is high or low. The MSB may be read on the first falling SCLK edge
after CS is low. Output data changes on the rising edge of SCLK. This control method is typically used for a
microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI
interface should be programmed for CPOL=0 (serial clock inactive low) and CPHA=1 (data valid on the
falling edge of serial clock).
Control via pin 7, FS (CS is tied/held low)− The rising edge of FS is the start of the cycle. Transitions on FS
can occur when SCLK is high or low. The MSB is presented on SDO after the rising edge of FS. The MSB
may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the rising
edge of SCLK. This is the typical configuration when the ADC is the only device on the TMS320 DSP serial
port.
Control via pin 1 and pin 7, CS and FS− Transitions on CS and FS can occur when SCLK is high or low. The
MSB is presented after the rising edge of FS. The falling edge of FS is the start of the sampling cycle. The
MSB may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the
rising edge of SCLK. This is typically used for multiple devices connected to a single TMS320 DSP serial
port.
TLC4545:
All control is provided using the CS input (pin 1) on the TLC4545. Transitions on CS can occur when SCLK is
high or low. The cycle is started on the falling edge transition on the CS input. This signal can be provided by
either a CS signal (when interfacing with an SPI microcontroller) or FS signal (when interfacing with a
TMS320 DSP). The MSB is presented to SDO on the falling edge of the signal applied to pin 1 and may be
read on the first falling SCLK edge after this input is low. Output data changes on the rising edge of SCLK.
control modes
control via pin 1 (CS, SPI interface)
All devices are compatible with this mode of operation. A falling edge on the CS input initiates the cycle. (For
the TLC4541, the FS input is tied to V ). The CS input remains low for the entire sampling time plus 4 SCLK
DD
decoding time(16 falling SCLK edges) and can then be released at any point during the remainder of the
conversion. Enough time should be allowed before the next falling CS edge so that the conversion cycle is not
terminated prematurely. The microcontroller SPI interface should be programmed for CPOL=0 (serial clock
inactive low) and CPHA=1 (data is valid on the falling edge of serial clock).
1
3
4
7
12
13
14
15
16
24
2
5
6
1
SCLK
CS
t
t
s
conv
SDO Data is the Result of the Previous Sample
For TLC45xx, the LSB is Presented on the Rising SCLK 16th Edge
t
(PWRDWN)
SDO
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
LSB−4 LSB−3
LSB−2 LSB−1
LSB
MSB MSB−1
Figure 15. SPI Cycle TIming Using the CS Input (FS = 1 for TLC4541)
13
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SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC4541
in this configuration, the FS input is tied to V .) Enough time should be allowed before the next rising CS edge
DD
so that the conversion cycle is not terminated prematurely.
1
3
4
7
2
5
6
12
13
14
15
16
24
1
SCLK
CS
t
s
t
conv
The CS Input Signal is
SDO Data is the Result of the Previous Sample
For TLC45xx, the LSB is Presented on the Rising SCLK 16th Edge
Generated by the FS Output
From a TMS320 DSP
SDO
t
(PWRDWN)
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
LSB−4 LSB−3 LSB−2 LSB−1
LSB
MSB MSB−1
Figure 16. DSP Cycle Timing Using the CS Input (FS = 1 for TLC4541 Only)
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only TLC4541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP or tied to ground. The FS signal from the DSP is connected directly to
the FS input of the ADC. A rising FS edge releases the MSB to the SDO output. The falling edge on the FS input
while SCLK is high or low initiates the cycle. The CS input should remain low for the entire sampling time plus
4 SCLK decoding time after falling FS (24 falling SCLK edges) and can then be released at any time during the
remainder of the conversion cycle. The optimum DSP interface is achieved when tying CS to ground and using
only the FS input to control the ADC.
24
1
3
4
2
5
6
17
14
15
16
3
4
1
2
SCLK
CS
FS
t
t
conv
s
SDO Data is the Result of the Previous Sample
For TLC45xx, the LSB is Presented on the Rising SCLK 16th Edge
t
(PWRDWN)
SDO
LSB−2 LSB−1 LSB
MSB MSB−1 MSB−2 MSB−3
LSB−3
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
The MSB is Presented on the SDO Output After
a Rising Edge on the FS Input.
The Device Will go into the Power Down State After the Conversion is
Complete. A Falling CS Edge or Rising FS Edge, Whichever Occurs First,
Removes the Device From Power Down.
Figure 17. DSP Cycle Timing Using FS Only (or Using Both CS and FS for the TLC4541)
14
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SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
t
cyc
t
t
conv
t
s
cyc(SCLK)
1
5
1
2
14
SCLK
CS
15
16
17,
24
t
t
t
(PWRDWN)
w1
su1
t
h2
t
w2
t
w3
t
h1
t
d2
t
d3
SDO
LSB+2
MSB
MSB
LSB+1
LSB
t
d1
Figure 18. Critical Timing: Control Via CS Input (FS = 1 for TLC4541)
t
t
s
conv
1
1
2
5
14
15
16
17,
24
SCLK
t
su5
t
t
(PWRDWN)
h2
t
h4
t
su4
CS
FS
t
w4
t
(PWRDWN)
t
d2
t
t
d3
su3
SDO
LSB+2
LSB+1
LSB
MSB
MSB
t
d4
Figure 19. Critical Timing: Control Via CS and FS Inputs (TLC4541 Only)
1
2
1
2
8
9
SCLK
t
t
su6
h6
t
cyc(reset)
Normal Cycle Begins
CS
Reset Cycle
SDO
MSB
MSB−1
MSB
(Output = FF00h)
Figure 20. Critical Timing: Reset/Initialization Cycle (FS =1 for TLC4541)
15
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ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢃꢄ
SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
2
2
1
8
9
1
8
t
9
1
2
SCLK
t
t
t
h7
h7
su7
su6
t
cyc(reset)
CS
t
cyc(reset)
OR
Normal Cycle Begins
FS
Initialization Cycle (Reset)
MSB
MSB
MSB
MSB−1
SDO
Figure 21. Critical Timing: Initialization Cycle (TLC4541 Only)
detailed description
The TLC4541/5 are successive approximation (SAR) ADCs utilizing a charge-redistribution DAC. Figure 22
shows a simplified version of the ADC. The sampling capacitor acquires the signal on AIN (or the AIN(+) pin for
TLC4545) during the sampling period. When the conversion process starts, the SAR control logic and charge
redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the
comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the
ADC output code is generated.
Charge
Redistribution
DAC
AIN/
AIN(+)
−
Control
Logic
ADC Code
C
i
+
C
i
GND/
AIN(−)
Figure 22. Simplified SAR Circuit
16
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SLAS293 − DECEMBER 2001
PRINCIPLES OF OPERATION
pseudo-differential inputs
The TLC4545 operate in pseudo-differential mode. The inverted input is available on pin 5. The inverted input
can tolerate a maximum input ripple of 0.2 V. It is normally used for zero-scale offset cancellation or ground
noise rejection.
serial interface
Output data format is binary (unipolar straight binary).
binary
D
Zero Scale Code = 0000h, V
= GND
AIN
D
Full Scale Code = FFFFh, V
= V
– 1LSB
AIN
REF
reference voltage
An external reference must be applied via pin 2, V
limit of the analog inputs to produce a full-scale reading. The value of V
exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The
. The voltage level applied to this pin establishes the upper
REF
, and the analog input should not
REF
digital output is at full scale when the input signal is equal to or higher than V
signal is equal to or less than GND.
and at zero when the input
REF
auto-power down and power up
Auto-power down is built into the devices in order to reduce power consumption. The wake-up time is fast
enough to provide power down between each conversion cycle. The power down state is initiated at the end
of conversion and wakes up on a falling CS edge (or rising FS edge, whichever occurs first, for TLC4541 only).
17
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ꢀ ꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢃꢄ
SLAS293 − DECEMBER 2001
APPLICATION INFORMATION
5 V
DSP to Single TLC4541
0.1 µF
REF
0.1 µF
10 kΩ
10 kΩ
V
DD
FS
REF
FSX0
SD0
SCLK
CS
DR0
DSP
TLC4541
GND
AIN
CLKX0
CLKR0
5 V
DSP to Single TLC4545
0.1 µF
REF
0.1 µF
10 kΩ
10 kΩ
V
CS/FS
SD0
REF
FSX0
DD
DR0
DSP
TLC4545
GND
AIN(+)
AIN(−)
SCLK
CLKX0
CLKR0
DSP to Multiple TLC4541s
XF0
FSX0
DR0
REF
DSP
CLKX0
CLKR0
XF1
0.1 µF
5 V
Ext Ref Input
5 V
0.1 µF
0.1 µF
10 kΩ
10 kΩ
CS
10 kΩ
10 kΩ
V
V
DD
REF
REF
DD
CS
FS
FS
TLC4541
#2
TLC4541
#1
AIN
AIN
SDO
SCLK
SDO
SCLK
GND
GND
Figure 23. Typical ADC Interface to a TMS320 DSP
18
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TLC4541ID
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
4541I
TLC4541IDG4
TLC4541IDGK
TLC4541IDGKG4
TLC4541IDGKR
TLC4541IDGKRG4
TLC4545ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
DGK
DGK
DGK
DGK
D
75
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
4541I
ALM
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
ALM
2500
2500
75
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
ALM
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
ALM
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
4545I
4545I
AME
AME
4545I
4545I
TLC4545IDG4
TLC4545IDGK
TLC4545IDGKG4
TLC4545IDR
SOIC
D
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
VSSOP
VSSOP
SOIC
DGK
DGK
D
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TLC4545IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC4541IDGKR
TLC4545IDR
VSSOP
SOIC
DGK
D
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
6.4
3.4
5.2
1.4
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC4541IDGKR
TLC4545IDR
VSSOP
SOIC
DGK
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
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