TLC545 [TI]
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS; 8位模拟数字转换器与串行控制和19输入量
| 型号： | TLC545 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS |
| 文件： | 总13页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
N PACKAGE
(TOP VIEW)
8-Bit Resolution A/D Converter
Microprocessor Peripheral or Stand-Alone
Operation
INPUT A0
INPUT A1
INPUT A2
INPUT A3
INPUT A4
INPUT A5
INPUT A6
INPUT A7
INPUT A8
INPUT A9
INPUT A10
INPUT A11
INPUT A12
GND
V
CC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
On-Chip 20-Channel Analog Multiplexer
Built-in Self-Test Mode
SYSTEM CLOCK
I/O CLOCK
ADDRESS INPUT
DATA OUT
CS
2
3
Software-Controllable Sample and Hold
Total Unadjusted Error . . . ±0.5 LSB Max
4
5
6
Timing and Control Signals Compatible
With 8-Bit TLC540 and 10-Bit TLC1540 A/D
Converter Families
REF+
REF–
7
8
INPUT A18
INPUT A17
INPUT A16
INPUT A15
INPUT A14
INPUT A13
9
CMOS Technology
10
11
12
13
14
PARAMETER
TL545
TL546
Channel Acquisition Time
Conversion Time (Max)
Sampling Rate (Max)
1.5 µs
9 µs
76 x 10
15 mW
2.7 µs
17 µs
40 x 10
15 mW
3
3
Power Dissipation (Max)
FN PACKAGE
(TOP VIEW)
description
The TLC545 and TLC546 are CMOS
analog-to-digital converters built around an 8-bit
switched capacitor successive-approximation
analog-to-digital converter. They are designed for
serial interface to a microprocessor or peripheral
via a 3-state output with up to four control inputs
including independent SYSTEM CLOCK, I/O
CLOCK, chip select (CS), and ADDRESS INPUT.
A 4-MHz system clock for the TLC545 and a
2.1-MHz system clock for the TLC546 with a
design that includes simultaneous read/write
operation allowing high-speed data transfers and
sample rates of up to 76,923 samples per second
for the TLC545, and 40,000 samples per second
for the TLC546.
4
3
2 1 28 27 26
INPUT A4
5
25
24
23
22
21
20
19
ADDRESS INPUT
DATA OUT
CS
REF+
REF–
INPUT A5
INPUT A6
INPUT A7
INPUT A8
INPUT A9
INPUT A10
6
7
8
9
INPUT A18
INPUT A17
10
11
12 13 14 15 16 17 18
In addition to the high-speed converter and
versatile control logic, there is an on-chip
20-channel analog multiplexer that can be used to
sample any one of 19 inputs or an internal self-test
voltage, and a sample-and-hold that can operate
automatically or under microprocessor control.
The converters incorporated in the TLC545 and TLC546 feature differential high-impedance reference inputs
thatfacilitateratiometricconversion, scaling, andanalogcircuitryisolationfromlogicandsupplynoises. Atotally
switched capacitor design allows low-error (±0.5 LSB) conversion in 9 µs for the TLC545, and 17 µs for the
TLC546, over the full operating temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
AVAILABLE OPTIONS
PACKAGE
CHIP CARRIER
T
A
PLASTIC DIP
(N)
(FN)
TLC545CFN
—
TLC545CN
—
0°C to 70°C
TLC545IFN
TLC546IFN
TLC545IN
TLC546IN
–40°C to 85°C
description (continued)
The TLC545C and the TLC546C are characterized for operation from 0°C to 70°C. The TLC545I and the
TLC546I are characterized for operation from –40°C to 85°C.
functional block diagram
1
A0
2
A1
REF+
22
REF–
21
3
4
5
6
7
8
9
A2
A3
A4
A5
A6
8-Bit
Analog-to-Digital
Converter
A7
A8
Sample
and
Hold
20-Channel
Analog
Multiplexer
10
11
12
13
15
16
17
18
19
20
(Switched-capacitors)
A9
INPUTS
A10
A11
A12
A13
A14
A15
A16
A17
A18
8
Output
8
Data
Register
8-to-1 Data
Selector and
Driver
24
DATA
OUT
Input
Address
Register
5
4
5
Self-Test
Reference
Control Logic
and I/O
Counters
2
25
Input
Multiplexer
ADDRESS
INPUT
26
23
27
I/O
CLOCK
CS
SYSTEM
CLOCK
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
INPUT
A0–A18
5 MΩ TYP
INPUT
A0–A18
C = 60 pF TYP
i
(equivalent input
capacitance)
operating sequence
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
I/O
CLOCK
Don’t
t
Care
Sample
Cycle C
conv
Access
Cycle C
Sample Cycle B
Access
Cycle B
(see Note C)
See Note A
CS
t
wH(CS)
MSB
LSB
MSB
LSB
ADDRESS
INPUT
Don’t Care
Don’t Care
B4 B3 B2 B1 B0
C4 C3 C2 C1 C0
Hi-Z
State
Hi-Z State
DATA
OUT
A7
A6 A5 A4 A3 A2 A1 A0
B7 B6 B5 B4 B3 B2 B1 B0
A7
B7
LSB
LSB
MSB
(see Note B)
Previous Conversion Data A
Conversion Data B
MSB
MSB
MSB
NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth I/O CLOCK↓ after CS↓ for the channel
whose address exists in memory at that time.
B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits
(A6–A0) will be clocked out on the first seven I/O CLOCK falling edges.
C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip
select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the
minimum chip-select setup time has elapsed.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Output voltage range, V
+0.3 V
+0.3 V
I
CC
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
Operating free-air temperature range, T : TLC545C, TLC546C . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC545I, TLC546I . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Case temperature for 10 seconds, T : FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
recommended operating conditions
TLC545
NOM
5
TLC546
NOM
5
UNIT
MIN
4.75
0
MAX
5.5
MIN
4.75
0
MAX
5.5
Supply voltage, V
V
V
V
V
V
V
V
CC
Positive reference voltage, V
(see Note 2)
(see Note 3)
– V (see Note 3)
V
CC
0
V
V
+0.1
V
CC
0
V
V
+0.1
ref+
Negative reference voltage, V
CC
CC
–0.1
0
V
CC
+0.2
–0.1
0
V
CC
+0.2
ref–
Differential reference voltage, V
V
CC
V
CC
ref+
ref–
CC
CC
Analog input voltage (see Note 3)
High-level control input voltage, V
0
V
CC
0
V
CC
2
2
IH
Low-level control input voltage, V
0.8
0.8
IL
Setup time, address bits at data input before I/O CLOCK↑,
200
0
400
0
ns
ns
t
su(A)
Address hold time, t
h
System
clock
cycles
Setup time, CS low before clocking in first address bit, t
(see Note 2)
su(CS)
3
3
I/O CLOCK frequency, f
clock(I/O)
0
2.048
4
0
1.1
2.1
MHz
MHz
SYSTEM CLOCK frequency, f
f
f
clock(I/O)
clock(SYS)
clock(I/O)
System
clock
cycles
Pulse duration, CS high during conversion, t
wH(CS)
36
36
Pulse duration, SYSTEM CLOCK high, t
wH(SYS)
110
100
200
200
210
190
404
404
ns
ns
ns
ns
Pulse duration, SYSTEM CLOCK low, t
wL(SYS)
Pulse duration, I/O CLOCK high, t
wH(I/O)
Pulse duration, I/O CLOCK low, t
wL(I/O)
f
f
f
f
≤ 1048 kHz
30
20
30
20
clock(SYS)
System
ns
ns
> 1048 kHz
Clock transition time
clock(SYS)
(see Note 4)
I/O
≤ 525 kHz
100
40
100
40
clock(I/O)
clock(I/O)
> 525 kHz
TLC545C, TLC546C
TLC545I, TLC546I
0
70
0
70
Operating free-air temperature, T
A
–40
85
–40
85
°C
NOTES: 2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling
edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip select setup time has elapsed.
3. Analog input voltages greater than that applied to REF+ convert as all “1”s (11111111), while input voltages less than that applied
to REF– convert asall“0”s(00000000). Asthedifferentialreferencevoltagedecreasesbelow4.75V, thetotalunadjustederrortends
to increase.
4. This is the time required for the clock input signal to fall from V min to V max or to rise from V max to V min. In the vicinity
IH
IL
IL
IH
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
electrical characteristics over recommended operating temperature range,
V
= V
= 4.75 V to 5.5 V, f
= 2.048 MHz for TLC545 or f
= 1.1 MHz for TLC546
CC
ref+
clock(I/O)
clock(I/O)
(unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX
UNIT
V
V
V
High-level output voltage (DATA OUT)
V
V
V
V
= 4.75 V,
= 4.75 V,
I
I
= –360 µA
OH
CC
OH
Low-level output voltage
= 3.2 mA
0.4
10
V
OL
CC
OL
= V
,
CS at V
CS at V
O
O
CC
= 0,
CC
I
Off-state (high-impedance state) ouput current
µA
OZ
–10
2.5
CC
I
I
I
High-level input current
Low-level input current
Operating supply current
V = V
CC
0.005
–0.005
1.2
µA
µA
IH
I
V = 0
I
–2.5
2.5
IL
CS at 0 V
mA
CC
Selected channel at V
Unselected channel at 0 V
,
CC
0.4
1
Selected channel leakage current
µA
Selected channel at 0 V,
–0.4
–1
Unselected channel at V
CC
CS at 0 V
I + I
CC ref
Supply and reference current
V
ref+
= V
,
CC
1.3
7
3
55
15
mA
pF
Analog inputs
Input capacitance
C
i
Control inputs
5
†
All typical values are at T = 25°C.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
operating characteristics over recommended operating free-air temperature range,
= V = 4.75 V to 5.5 V, f = 2.048 MHz for TLC545 or 1.1 MHz for TLC546,
V
CC
ref+
clock(I/O)
f
= 4 MHz for TLC545 or 2.1 MHz for TLC546
clock(SYS)
TLC545
TLC546
PARAMETER
TEST CONDITIONS
See Note 5
UNIT
MIN TYP
MAX
±0.5
±0.5
±0.5
±0.5
MIN TYP
MAX
±0.5
±0.5
±0.5
±0.5
E
E
E
Linearity error
LSB
LSB
LSB
LSB
L
Zero-scale error
Full-scale error
See Note 6
See Note 6
See Note 7
ZS
FS
Total unadjusted error
INPUT A19 address = 10011
(see Note 8)
01111101
(125)
10000011 01111101
10000011
(131)
Self-test output code
Conversion time
(131)
(125)
t
t
See Operating Sequence
9
17
µs
µs
conv
Total access and
conversion time
See Operating Sequence
13
3
25
I/O
clock
cycles
Channel acquisition time
(sample cycle)
See Operating Sequence
3
acq
Time output data remains
valid after I/O CLOCK↓
t
t
10
10
ns
ns
v
Delay time, I/O CLOCK to
DATA OUT valid
300
400
d
t
t
t
t
Output enable time
Output disable time
Data bus rise time
Data bus fall time
150
150
300
300
150
150
300
300
ns
ns
ns
ns
en
See Parameter
Measurement Information
dis
r(bus)
f(bus)
NOTES: 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The INPUT A19 analog input signal is internally
generated and is used for test purposes.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
V
CC
1.4 V
3 kΩ
3 kΩ
Test
Point
Output
Under Test
Test
Point
Output
Under Test
Test
Point
Output
Under Test
C
C
L
C
L
3 kΩ
L
(see Note A)
(see Note A)
(see Note A)
See Note B
See Note B
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
t AND t
PZL PLZ
t , t , AND t
d
r
f
t
AND t
PHZ
PZH
V
CC
50%
CS
0 V
SYSTEM
CLOCK
t
PZL
t
PLZ
V
CC
Output Waveform 1
(see Note C)
50%
See Note B
10%
0 V
t
PZH
t
PHZ
V
OH
90%
Output Waveform 2
(see Note C)
50%
0 V
VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES
I/O CLOCK
0.8 V
2.4 V
0.4 V
Output
t
d
t
t
f
r
2.4 V
0.8 V
DATA OUT
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME
= 50 pF for TLC545 and 100 pF for TLC546
NOTES: A.
B.
C
L
t = t
en PZH
or t
, t or t
= t
PZL dis PHZ PLZ
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:
S
The capacitance charging voltage is given by
–t /R C
c
t i
(1)
V = V 1–e
(
)
C
S
where
R = R + r
i
t
s
The final voltage to 1/2 LSB is given by
V (1/2 LSB) = V – (V /512)
(2)
C
S
S
Equating equation 1 to equation 2 and solving for time t gives
c
–t /R C
c
t i
V –(V /512) = V 1–e
(3)
(4)
(
)
S
S
S
and
t (1/2 LSB) = R × C × ln(512)
c
t
i
Therefore, with the values given the time for the analog input signal to settle is
t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(512)
(5)
c
s
This time must be less than the converter sample time shown in the timing diagrams.
†
Driving Source
TLC545/6
R
r
i
s
V
I
V
S
V
C
1 kΩ MAX
C
i
50 pF MAX
V
V
= Input Voltage at INPUT A0–A18
= External Driving Source Voltage
I
S
s
R = Source Resistance
r
= Input Resistance
i
C = Input Capacitance
i
†
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the
resolution of the converter.
•
R must be real at the input frequency.
s
Figure 1. Equivalent Input Circuit Including the Driving Source
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
The TLC545 and TLC546 are both complete data acquisition systems on single chips. Each includes such functions
as system clock, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility and
access speed, there are four control inputs; CS, ADDRESSINPUT, I/OCLOCK, andSYSTEMCLOCK. Thesecontrol
inputs and a TTL-compatible 3-state output facilitate serial communications with a microprocessor or microcomputer.
The TLC545 and TLC546 can complete conversions in a maximum of 9 and 17 µs respectively, while complete
input-conversion-output cycles can be repeated at a maximum of 13 and 25 µs, respectively.
The system clock and I/O clock are normally used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and
softwareneedonlybeconcernedwithaddressingthedesiredanalogchannel, readingthepreviousconversionresult,
and starting the conversion by using the I/O CLOCK. SYSTEM CLOCK will drive the “conversion crunching” circuitry
so that the control hardware and software need not be concerned with this task.
When CS is high, DATA OUT is in a high-impedance condition, and ADDRESS INPUT and I/O CLOCK are disabled.
This feature allows each of these terminals, with the exception of CS, to share a control logic point with their
counterpart terminals on additional A/D devices when additional TLC545/TLC546 devices are used. Thus, the above
feature serves to minimize the required control logic terminals when using multiple A/D devices.
The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:
1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the SYSTEM CLOCK after a CS transition before the transition is recognized. The
MSB of the previous conversion result automatically appears on DATA OUT.
2. A new positive-logic multiplexer address is shifted in on the first five rising edges of I/O CLOCK. The MSB of
the address is shifted in first. The negative edges of these five I/O clocks shift out the second, third, fourth,
fifth, and sixth most significant bits of the previous conversion result. The on-chip sample and hold begins
sampling the newly addressed analog input after the fifth falling edge. The sampling operation basically
involves the charging of internal capacitors to the level of the analog input voltage.
3. Two clock cycles are then applied to I/O CLOCK and the seventh and eighth conversion bits are shifted out on
the negative edges of these clock cycles.
4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog
sampling process and initiates the hold function. Conversion is then performed during the next 36 system
clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36
system clock cycles to allow for the conversion function.
CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple
conversion, special care must be exercised to prevent noise glitches on the I/O CLOCK line. If glitches occur on the
I/O CLOCK line, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also,
if CS is taken high, it must remain high until the end of conversion. Otherwise, a valid falling edge of CS causes a
reset condition, which aborts the conversion in progress.
A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and
not the ongoing conversion.
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TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise,
additional common clock cycles are recognized as I/O CLOCKS and shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the
negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth
valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid
I/O clock cycle, until the moment at which the analog signal must be converted. The TLC545/546 continues sampling
the analog input until the eighth valid falling edge of the I/O clock. The control circuitry or software must then
immediately lower the I/O clock signal to initiate the hold function at the desired point in time and to start conversion.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
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