TLC5510A [TI]
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS; 8位高速模拟 - 数字转换器
| 型号： | TLC5510A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS |
| 文件： | 总15页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
5-V Single-Supply Operation
features
Low Power Consumption
TLC5510 . . . 127.5 mW Typ
TLC5510A . . . 150 mW Typ
Analog Input Range
– TLC5510 . . . 2 V Full Scale
– TLC5510A . . . 4 V Full Scale
(includes reference resistor dissipation)
8-Bit Resolution
TLC5510 is Interchangeable With Sony
CXD1175
Integral Linearity Error
±0.75 LSB Max (25°C)
±1 LSB Max (–20°C to 75°C)
applications
Differential Linearity Error
±0.5 LSB Max (25°C)
Digital TV
Medical Imaging
±0.75 LSB Max (–20°C to 75°C)
Video Conferencing
High-Speed Data Conversion
QAM Demodulators
Maximum Conversion Rate
20 Mega-Samples per Second
(MSPS) Max
†
PW OR NS PACKAGE
(TOP VIEW)
description
TheTLC5510andTLC5510AareCMOS, 8-bit, 20
MSPS analog-to-digital converters (ADCs) that
utilize a semiflash architecture. The TLC5510 and
TLC5510A operate with a single 5-V supply and
typically consume only 130 mW of power.
Included is an internal sample-and-hold circuit,
parallel outputs with high-impedance mode, and
internal reference resistors.
OE
DGND
D1(LSB)
D2
DGND
1
24
23
22
21
20
19
18
17
16
15
14
13
REFB
2
REFBS
AGND
3
4
D3
AGND
5
D4
ANALOG IN
6
D5
V
7
DDA
D6
REFT
8
The semiflash architecture reduces power
consumption and die size compared to flash
converters. By implementing the conversion in a
2-step process, the number of comparators is
significantly reduced. The latency of the data
output valid is 2.5 clocks.
D7
REFTS
9
D8(MSB)
V
10
11
DDA
V
V
DDD
DDA
CLK 12
V
DDD
†
Available in tape and reel only and ordered
as the shown in the Available Options table
below.
The TLC5510 uses the three internal reference
resistors to create a standard, 2-V, full-scale
conversion range using V
. Only external jumpers are required to implement this option and eliminates the
DDA
need for external reference resistors. The TLC5510A uses only the center internal resistor section with an
externally applied 4-V reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25°C
and a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications include
a differential gain of 1% and differential phase of 0.7 degrees.
The TLC5510 and TLC5510A are characterized for operation from –20°C to 75°C.
AVAILABLE OPTIONS
PACKAGE
MAXIMUM FULL-SCALE
T
A
SOP (NS)
INPUT VOLTAGE
TSSOP (PW)
(TAPE AND REEL ONLY)
TLC5510IPW
–
TLC5510INSLE
TLC5510AINSLE
2 V
4 V
–20°C to 75°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
functional block diagram
Resistor
Reference
Divider
OE
REFB
270 Ω
NOM
Lower Sampling
Comparators
(4-Bit)
REFT
Lower Encoder
(4-Bit)
D1(LSB)
D2
REFBS
Lower Data
Latch
80 Ω
NOM
D3
AGND
AGND
D4
Lower Sampling
Comparators
(4-Bit)
Lower Encoder
(4-Bit)
V
DDA
D5
D6
320 Ω
NOM
Upper Data
Latch
D7
REFTS
ANALOG IN
Upper Sampling
Comparators
(4-Bit)
Upper Encoder
(4-Bit)
D8(MSB)
Clock
Generator
CLK
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
EQUIVALENT OF EACH DIGITAL INPUT
EQUIVALENT OF EACH DIGITAL OUTPUT
V
DDA
V
DDD
V
DDD
D1–D8
OE, CLK
ANALOG IN
AGND
DGND
DGND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
Terminal Functions
TERMINAL
NAME NO.
AGND
I/O
DESCRIPTION
20, 21
19
Analog ground
Analog input
Clock input
ANALOG IN
CLK
I
I
12
DGND
D1–D8
OE
2, 24
3–10
1
Digital ground
O
I
Digital data out. D1 = LSB, D8 = MSB
Output enable. When OE = low, data is enabled. When OE = high, D1–D8 is in high-impedance state.
V
V
14, 15, 18
11, 13
23
Analog supply voltage
Digital supply voltage
DDA
DDD
REFB
I
I
Reference voltage in bottom
REFBS
22
Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected to
ground.
REFT
17
16
Reference voltage in top
REFTS
Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V
reference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected to
V
DDA
.
†
absolute maximum ratings
Supply voltage, V
Reference voltage input range, V
Analog input voltage range, V
Digital input voltage range, V
Digital output voltage range, V
Operating free-air temperature range, T
Storage temperature range, T
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DDA DDD
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
REFT REFB
I(ANLG)
I(DGTL)
DDA
DDA
DDD
DDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
O(DGTL)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
4.75
NOM
MAX
5.25
5.25
100
4
UNIT
V
V
–AGND
–AGND
5
5
0
DDA
V
Supply voltage
4.75
DDD
AGND–DGND
TLC5510A
–100
mV
V
‡
Reference input voltage (top), V
ref(T)
V
+2
REFB
0
‡
Reference input voltage (bottom), V
TLC5510A
V
–4
V
ref(B)
REFT
Analog input voltage range, V
I(ANLG)
V
REFB
4
V
REFT
V
High-level input voltage, V
V
IH
Low-level input voltage, V
1
V
IL
Pulse duration, clock high, t
(see Figure 1)
25
25
ns
ns
w(H)
(see Figure 1)
Pulse duration, clock low, t
w(L)
‡
The reference voltage levels for the TLC5510 are derived through an internal resistor divider between V
derived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, the
reference voltage is externally applied across the center divider resistor.
and ground and therefore are not
DDA
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
electricalcharacteristicsatV =5V,V
DD
=2.5V,V
=0.5V,f
=20MHz,T =25°C(unless
(CLK) A
REFT
REFB
otherwise noted)
digital I/O
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
High-level input current
Low-level input current
High-level output current
Low-level output current
V
V
= MAX,
V
V
V
V
= V
= 0
5
5
IH
DD
IH
DD
µA
= MAX,
IL
DD
IL
OE = GND,
OE = GND,
= MIN,
= MIN,
V
V
= V
DD
= 0.4 V
–0.5 V
–1.5
2.5
OH
OL
DD
DD
OH
mA
OL
High-level high-impedance-state
output leakage current
I
OE = V
OE = V
,
,
V
= MAX
= MIN
V
= V
= 0
16
16
OZH
DD
DD
OH
DD
µA
Low-level high-impedance-state
output leakage current
I
V
DD
V
OL
OZL
DD
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
power
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
= 20 MHz, National Television System Committee (NTSC)
(CLK)
ramp wave input, reference resistor dissipation is separate
I
I
Supply current
18
27
mA
DD
TLC5510
V
ref
= REFT – REFB = 2 V
= REFT – REFB = 4 V
5.2
7.5
15
10.5
21
mA
mA
Reference voltage current
ref
TLC5510A
V
ref
10.4
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
static performance
†
PARAMETER
TEST CONDITIONS
MIN
0.57
1.9
TYP
0.61
2.02
2.29
270
16
MAX
0.65
2.15
2.4
UNIT
Self-bias (1), at REFB
Short REFB to REFBS, Short REFT to REFTS
Self-bias (2), REFT – REFB
Self-bias (3), at REFT
V
Short REFB to AGND,
Short REFT to REFTS
rms
2.18
190
R
C
Reference voltage resistor
Analog input capacitance
Between REFT and REFB
350
Ω
ref
i
V
= 1.5 V + 0.07 V
pF
I(ANLG)
T
= 25°C
±0.4 ±0.75
f
= 20 MHz,
A
(CLK)
V = 0.5 V to 2.5 V
TLC5510
TLC5510A
TLC5510
TLC5510A
T
= –20°C to 75°C
T = 25°C
A
±1
±0.4 ±0.75
±1
I
A
Integral nonlinearity (INL)
f
= 20 MHz,
(CLK)
V = 0 to 4 V
T
= –20°C to 75°C
T = 25°C
A
I
A
LSB
±0.3
±0.3
–43
±0.5
±0.75
±0.5
f
= 20 MHz,
(CLK)
V = 0.5 V to 2.5 V
T
= –20°C to 75°C
T = 25°C
A
I
A
Differential nonlinearity (DNL)
f
= 20 MHz,
(CLK)
V = 0 to 4 V
T
A
= –20°C to 75°C
±0.75
–68
I
TLC5510
TLC5510A
TLC5510
V
= REFT – REFB = 2 V
–18
–36
–20
mV
mV
mV
ref
E
E
Zero-scale error
Full-scale error
ZS
V
= REFT – REFB = 4 V
–86 –136
ref
V
= REFT – REFB = 2 V
0
0
20
40
ref
FS
TLC5510A
V
= REFT – REFB = 4 V
–40
mV
ref
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
operatingcharacteristicsatV =5V,V
DD
=2.5V,V
=0.5V,f
=20MHz,T =25°C(unless
REFT
REFB
(CLK) A
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TLC5510
V
V
= 0.5 V – 2.5 V
= 0 V – 4 V
20 MSPS
20 MSPS
MHz
I(ANLG)
f
Maximum conversion rate
f = 1-kHz ramp
I
conv
TLC5510A
I(ANLG)
BW
Analog input bandwidth
Digital output delay time
Differential gain
At – 1 dB
14
18
1%
0.7
30
4
t
C
≤ 10 pF (see Note 1 and Figure 1)
L
30
ns
d(D)
NTSC 40 Institute of Radio Engineers (IRE)
modulation wave, = 14.3 MSPS
f
Differential phase
degrees
ps
conv
t
t
Aperture jitter time
Sampling delay time
AJ
ns
d(s)
t
Enable time, OE↓ to valid data
C
C
= 10 pF
= 10 pF
5
7
ns
ns
en
L
L
t
Disable time, OE↑ to high impedance
dis
T
= 25°C
45
43
45
46
43
42
39
39
46
44
A
Input tone = 1 MHz
Input tone = 3 MHz
Input tone = 6 MHz
Input tone = 10 MHz
Full range
= 25°C
T
A
Full range
= 25°C
Spurious free dynamic range (SFDR)
dB
dB
T
A
Full range
= 25°C
T
A
Full range
T
A
= 25°C
SNR
Signal-to-noise ratio
includes probe and jig capacitance.
Full range
NOTE 1:
C
L
t
t
w(L)
w(H)
CLK (clock)
t
d(s)
ANALOG IN
(input signal)
N+2
N+1
N+4
N
N+3
D1–D8
(output data)
N–3
N–2
N–1
N
N+1
t
d(D)
Figure 1. I/O Timing Diagram
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
PRINCIPLES OF OPERATION
functional description
The TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each.
AsshowninFigure2, inputvoltageV (1)issampledwiththefallingedgeofCLK1totheuppercomparatorsblock
I
and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with the
rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown
in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.
Input voltage V (2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and
I
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears with
the rising edge of CLK5.
V (1)
I
V (2)
I
V (3)
I
V (4)
I
ANALOG IN
(sampling points)
CLK1
CLK2
S(2)
CLK3
S(3)
CLK4
S(4)
CLK5
CLK (clock)
S(1)
C(1)
C(2)
C(3)
C(4)
Upper Comparators Block
Upper Data
UD(0)
UD(1)
RV(1)
UD(2)
RV(2)
UD(3)
RV(3)
RV(0)
Lower Reference Voltage
S(1)
H(1)
C(1)
S(3)
H(3)
C(3)
Lower Comparators Block (A)
Lower Data (A)
LD(–1)
LD(1)
H(0)
C(0)
S(2)
H(2)
C(2)
S(4)
H(4)
Lower Comparators Block (B)
Lower Data (B)
LD(–2)
LD(0)
LD(2)
OUT(–2)
OUT(–1)
OUT(0)
OUT(1)
D1–D8 (data output)
Figure 2. Internal Functional Timing Diagram
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
PRINCIPLES OF OPERATION
internal referencing
TLC5510
The three internal resistors shown with V
can generate a 2-V reference voltage. These resistors are brought
DDA
out on V
, REFTS, REFT, REFB, REFBS, and AGND.
DDA
To use the internally generated reference voltage, terminal connections should be made as shown in Figure 3.
This connection provides the standard video 2-V reference for the nominal digital output.
TLC5510
18
V
DDA
(analog supply)
R1
320 Ω NOM
REFTS
16
17
REFT
REFB
R
ref
270 Ω NOM
23
22
REFBS
AGND
R2
80 Ω NOM
21
Figure 3. External Connections for a 2-V Analog Input Span Using the Internal-Reference Resistor Divider
TLC5510A
For an analog input span of 4 V, 4 V is supplied to REFT, and REFB is grounded and terminal connections should
be made as shown in Figure 4. This connection provides the 4-V reference for the nominal zero to full-scale
digital output with a 4 V analog input at ANALOG IN.
pp
TLC5510A
18
V
DDA
(analog supply)
R1
320 Ω NOM
16
17
REFTS
REFT
4 V
R
ref
270 Ω NOM
REFB
23
22
REFBS
R2
80 Ω NOM
21
AGND
Figure 4. External Connections for 4-V Analog Input Span
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
PRINCIPLES OF OPERATION
functional operation
The output code change with input voltage is shown in Table 1.
Table 1. Functional Operation
DIGITAL OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
MSB
LSB
V
255
0
•
0
0
0
0
0
0
0
•
ref(B)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
128
127
•
•
•
•
•
•
•
•
•
0
1
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
•
•
•
•
•
•
•
•
•
V
ref(T)
0
1
1
1
1
1
1
1
1
APPLICATION INFORMATION
The following notes are design recommendations that should be used with the device.
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and
production process. Breadboards should be copper clad for bench evaluation.
Since AGND and DGND are connected internally, the ground lead in must be kept as noise free as possible.
A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and
digital ground plane should be used on PCB layouts when additional logic devices are used. The AGND
and DGND terminals of the device should be tied to the analog ground plane.
V
to AGND and V
to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively,
DDD
DDA
and placed as close as possible to the affected device terminals. A ceramic-chip capacitor is recommended
for the 0.01-µF capacitor. Care should be exercised to ensure a solid noise-free ground connection for the
analog and digital ground terminals.
V
, AGND, and ANALOG IN should be shielded from the higher frequency terminals, CLK and D0–D7.
DDA
When possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB for
shielding.
In testing or application of the device, the resistance of the driving source connected to the analog input
should be 10 Ω or less within the analog frequency range of interest.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
APPLICATION INFORMATION
DV
DD
5 V
C12
TLC5510
AV
DD
5 V
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
Clock
V
V
V
CLK
DDD
DDD
V
REF
ADJ
FB3
FB2
FB7
V
DDA
DDA
C8
C7
C11
R5
D8 (MSB)
JP1 JP2
REFTS
REFT
D7
D6
D5
C1
D1
J1
C3
TP1
Video
Input
8
Q1
C9
R3
7
V
DDA
C11
C6
FB1
R4
R2
6
ANALOG IN D4
R1
C5
C2
5
AGND
AGND
D3
D2
D3
D2
4
C4
JP3 JP4
– 5 V
3
TP3
REFBS D1 (LSB)
C10
2
REFB
DGND
DGND
OE
1
Output
Enable
NOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes D2 and D3
which compensate for D1 and Q1 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference.
LOCATION
DESCRIPTION
C1, C3–C4, C6–C12 0.1-µF capacitor
C2
10-pF capacitor
47-µF capacitor
Ferrite bead
C5
FB1, FB2, FB3, FB7
Q1
R1, R3
R2
2N3414 or equivalent
75-Ω resistor
500-Ω resistor
R4
10-kΩ resistor, clamp voltage adjust
300-Ω resistor, reference-voltage fine adjust
R5
Figure 5. TLC5510 Evaluation and Test Schematic
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
APPLICATION INFORMATION
DV
DD
5 V
C4
TLC5510A
CLK
AV
DD
5 V
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
Clock
V
V
V
DDD
V
REF
ADJ
FB3
FB2
FB7
V
DDA
DDA
DDD
C8
C7
C11
R5
D8 (MSB)
REFTS
REFT
D7
D6
D5
C1
D1
J1
C3
TP1
Video
Input
8
Q1
C9
R3
7
C11
FB1
V
DDA
C6
R4
R2
6
ANALOG IN D4
R1
C5
C2
5
AGND
AGND
D3
D2
4
– 5 V
3
REFBS D1 (LSB)
2
REFB
DGND
DGND
OE
1
Output
Enable
NOTE A: R5 allows adjustment of the reference voltage to 4 V. R4 adjusts for the desired Q1 quiescent operating point.
LOCATION
DESCRIPTION
C1, C3–C4, C6–C11 0.1-µF capacitor
C2
10-pF capacitor
47-µF capacitor
Ferrite bead
C5
FB1, FB2, FB3, FB7
Q1
R1, R3
R2
2N3414 or equivalent
75-Ω resistor
500-Ω resistor
R4
10-kΩ resistor, clamp voltage adjust
300-Ω resistor, reference-voltage fine adjust
R5
Figure 6. TLC5510A Evaluation and Test Schematic
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
APPLICATION INFORMATION
AV
DD
5 V
4.7 µF
0.1 µF
+
1 kΩ
10 kΩ POT
CLOCK
1 kΩ
TLC5510
4.7 µF
CLOCK
OE
49.9 Ω
+
_
THS3001
ANALOG IN
49.9 Ω
D1
D2
D3
D4
D5
D6
D7
D8
100 pF
AV
SS
– 5V
681 Ω
681 Ω
To Processor
0.1 µF
4.7 µF
+
†
FB1
V
V
V
DDA
DDA
DDA
0.1 µF
+
+
+
0.1 µF
0.1 µF
FB3
+
DV
DD
4.7 µF
4.7 µF
4.7 µF
4.7 µF
5 V
V
V
DDD
DDD
REFTS
REFT
4.7 µF
0.1 µF
+
0.1 µF
REFBS
REFB
0.1 µF
4.7 µF
0.1 µF
+
DGND
DGND
4.7 µF
AGND
AGND
†
FB – Ferrite Bead
Figure 7. TLC5510 Application Schematic
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
APPLICATION INFORMATION
AV
DD
5 V
4.7 µF
0.1 µF
+
1 kΩ
10 kΩ POT
CLOCK
1 kΩ
TLC5510A
CLOCK
ANALOG IN
4.7 µF
OE
+
49.9 Ω
AD8001
49.9 Ω
AV
_
D1
D2
D3
D4
D5
D6
D7
D8
100 pF
SS
– 5 V
681 Ω
681 Ω
To Processor
0.1 µF
4.7 µF
+
†
FB1
V
V
V
DDA
DDA
DDA
DV
DD
+
+
0.1 µF
+
0.1 µF
0.1 µF
FB3
+
5 V
4.7 µF
4.7 µF
4.7 µF
4.7 µF
V
V
DDD
DDD
REFTS
REFT
V
ref
4 V
0.1 µF
4.7 µF
0.1 µF
REFBS
REFB
0.1 µF
DGND
DGND
4.7 µF
AGND
AGND
†
FB – Ferrite Bead
Figure 8. TLC5510A Application Schematic
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095K – SEPTEMBER 1994 – REVISED MAY 1999
MECHANICAL DATA
NS (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
14
16
20
24
DIM
10,50
10,50
12,90
15,30
A MAX
0,51
0,35
1,27
14
M
0,25
8
9,90
9,90
12,30
14,70
A MIN
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
7
0,25
0°–10°
A
1,05
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
4040062/B 2/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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