TLC5540 [TI]
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER; 8位高速模拟数字转换器
| 型号： | TLC5540 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总17页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
PW OR NS PACKAGE
(TOP VIEW)
features
8-Bit Resolution
OE
DGND
D1(LSB)
D2
DGND
1
24
23
22
21
20
19
18
17
16
15
14
13
Differential Linearity Error
– ±0.3 LSB Typ, ±1 LSB Max (25°C)
– ±1 LSB Max
REFB
2
REFBS
AGND
3
4
Integral Linearity Error
– ±0.6 LSB, ±0.75 LSB Max (25°C)
– ±1 LSB Max
D3
AGND
5
D4
ANALOG IN
6
D5
V
7
DDA
Maximum Conversion Rate of
40 Megasamples Per Second (MSPS) Max
D6
REFT
8
D7
REFTS
9
Internal Sample and Hold Function
5-V Single Supply Operation
D8(MSB)
V
10
11
DDA
V
V
DDD
DDA
CLK 12
V
Low Power Consumption . . . 85 mW Typ
Analog Input Bandwidth . . . ≥75 MHz Typ
Internal Reference Voltage Generators
DDD
AVAILABLE OPTIONS
PACKAGE
applications
T
A
Quadrature Amplitude Modulation (QAM)
and Quadrature Phase Shift Keying (QPSK)
Demodulators
TSSOP (PW)
SOP (NS)
TLC5540CPW
TLC5540IPW
–0°C to 70°C
–40°C to 85°C
TLC5540CNSLE
TLC5540INSLE
Digital Television
Charge-Coupled Device (CCD) Scanners
Video Conferencing
Digital Set-Top Box
Digital Down Converters
High-Speed Digital Signal Processor
Front End
description
The TLC5540 is a high-speed, 8-bit analog-to-digital converter (ADC) that converts at sampling rates up to
40 megasamples per second (MSPS). Using a semiflash architecture and CMOS process, the TLC5540 is able
to convert at high speeds while still maintaining low power consumption and cost. The analog input bandwidth
of 75 MHz (typ) makes this device an excellent choice for undersampling applications. Internal resistors are
provided to generate 2-V full-scale reference voltages from a 5-V supply, thereby reducing external
components. The digital outputs can be placed in a high impedance mode. The TLC5540 requires only a single
5-V supply for operation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
functional block diagram
Resistor
Reference
Divider
OE
REFB
270 Ω
NOM
Lower Sampling
Comparators
(4 Bit)
REFT
Lower Encoder
(4 Bit)
D1(LSB)
D2
REFBS
Lower Data
Latch
80 Ω
NOM
D3
AGND
AGND
D4
Lower Sampling
Comparators
(4 Bit)
Lower Encoder
(4 Bit)
V
DDA
D5
D6
320 Ω
NOM
Upper Data
Latch
D7
REFTS
ANALOG IN
Upper Sampling
Comparators
(4 Bit)
Upper Encoder
(4 Bit)
D8(MSB)
Clock
Generator
CLK
schematics of inputs and outputs
EQUIVALENT OF ANALOG INPUT
EQUIVALENT OF EACH DIGITAL INPUT
EQUIVALENT OF EACH DIGITAL OUTPUT
V
DDA
V
DDD
V
DDD
D1–D8
OE, CLK
ANALOG IN
AGND
DGND
DGND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
Terminal Functions
TERMINAL
NAME NO.
AGND
I/O
DESCRIPTION
20, 21
19
Analog ground
Analog input
Clock input
ANALOG IN
CLK
I
I
12
DGND
D1–D8
OE
2, 24
3–10
1
Digital ground
O
I
Digital data out. D1:LSB, D8:MSB
Output enable. When OE = L, data is enabled. When OE = H, D1–D8 is high impedance.
V
V
14, 15, 18
11, 13
23
Analog V
DDA
DD
Digital V
DDD
DD
REFB
I
I
ADC reference voltage in (bottom)
REFBS
22
Reference voltage (bottom). When using the internal voltage divider to generate a nominal 2-V reference,
theREFBSterminalisshortedtotheREFBterminalandtheREFTSterminalisshortedtotheREFTterminal
(see Figure 13 and Figure 14).
REFT
17
16
Reference voltage in (top)
REFTS
Reference voltage (top). When using the internal voltage divider to generate a nominal 2-V reference, the
REFTS terminal is shorted to the REFT terminal and the REFBS terminal is shorted to the REFB terminal
(see Figure 13 and Figure 14).
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Reference voltage input range, V
Analog input voltage range, V
Digital input voltage range, V
Digital output voltage range, V
Operating free-air temperature range, T : TLC5540C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DDA DDD
, V
, V
, V
. . . . . . . . . . . . . . . AGND to V
I(REFT) I(REFB) I(REFBS) I(REFTS)
I(ANLG)
I(DGTL)
DDA
DDA
DDD
DDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
O(DGTL)
A
TLC5540I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
recommended operating conditions
MIN
4.75
NOM
MAX
5.25
5.25
100
UNIT
V
V
–AGND
–AGND
5
5
0
DDA
V
Supply voltage
4.75
DDD
AGND–DGND
–100
mV
V
Reference input voltage (top), V
V
+1.8
I(REFB)
0
V
+2
V
DDA
I(REFT)
I(REFB)
0.6
Reference input voltage (bottom), V
V
–1.8
V
I(REFB)
(see Note 1)
I(REFT)
Analog input voltage range, V
I(ANLG)
V
V
V
I(REFB)
I(REFT)
Full scale voltage, V
– V
1.8
4
5
1
V
I(REFT)
High-level input voltage, V
I(REFB)
V
IH
Low-level input voltage, V
V
IL
Pulse duration, clock high, t
12.5
12.5
0
ns
ns
°C
°C
w(H)
w(L)
Pulse duration, clock low, t
TLC5540C
TLC5540I
70
85
Operating free-air temperature, T
A
–40
NOTE 1: 1.8 V ≤ V
– V
< V
I(REFB) DD
I(REFT)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
electrical characteristics at V
(unless otherwise noted)
= 5 V, V
= 2.6 V, V
= 0.6 V, f = 40 MSPS, T = 25°C
DD
I(REFT)
I(REFB)
s
A
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±1
UNIT
T
A
= 25°C
±0.6
E
E
Linearity error, integral
L
T
A
= MIN to MAX
= 25°C
±1
f = 40 MSPS,
s
I
LSB
V = 0.6 V to 2.6 V
T
A
±0.3 ±0.75
±1
Linearity error, differential
D
T
A
= MIN to MAX
Self bias (1), V
Self bias (1), V
Self bias (2), V
Self bias (2), V
Short REFB to REFBS
Short REFT to REFTS
Short REFB to AGND
Short REFT to REFTS
0.57
2.47
0.61
2.63
AGND
2.29
7.5
0.65
2.80
RB
RT
RB
RT
See Figure 13
See Figure 14
V
2.18
5.2
2.4
12
I
Reference-voltage current
V
– V
= 2 V
I(REFB)
mA
Ω
ref
I(REFT)
R
C
Reference-voltage resistor Between REFT and REFB terminals
165
270
4
350
ref
i
Analog input capacitance
Zero-scale error
V
V
= 1.5 V + 0.07 V
rms
pF
I(ANLG)
E
E
–18
–25
–43
0
–68
25
5
ZS
– V
= 2 V
mV
µA
I(REFT)
I(REFB)
Full-scale error
FS
I
I
I
I
High-level input current
Low-level input current
High-level output current
Low-level output current
V
V
= 5.25 V,
= 5.25 V,
V
V
V
V
= V
= 0
IH
DD
IH
DD
5
IL
DD
IL
OE = GND,
OE = GND,
= 4.75 V,
= 4.75 V,
V
V
= V
DD
= 0.4 V
–0.5 V
–1.5
2.5
OH
OL
DD
DD
OH
mA
OL
High-level
I
high-impedance-state
output leakage current
OE = V
OE = V
,
,
V
= 5.25,
= 4.75,
V
= V
= 0
16
OZH(lkg)
DD
DD
DD
DD
OH
OL
DD
µA
Low-level
high-impedance-state
output leakage current
I
I
V
V
16
27
OZL(lkg)
‡
f = 40 MSPS,
NTSC ramp wave input,
See Note 2
s
L
Supply current
17
mA
DD
C
25 pF,
†
‡
Conditions marked MIN or MAX are as stated in recommended operating conditions.
National Television System Committee
NOTE 2: Supply current specification does not include I
.
ref
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
operating characteristics at V
otherwise noted)
= 5 V, V
= 2.6 V, V
= 0.6 V, f = 40 MSPS, T = 25°C (unless
DD
RT
RB
s
A
†
PARAMETER
TEST CONDITIONS
= MIN to MAX
A
MIN
TYP
MAX
UNIT
MSPS
MSPS
MHz
ns
f
f
Maximum conversion rate
Minimum conversion rate
T
40
s
T
A
= MIN to MAX
5
75
9
s
BW
Analog input full-power bandwidth
Delay time, digital output
Disable time, output high to Hi-Z
Disable time, output low to Hi-Z
Enable time, Hi-Z to output high
Enable time, Hi-Z to output low
Differential gain
At – 3 dB,
V
= 2 V
I(ANLG)
≤ 10 pF (see Note 3)
pp
t
t
t
t
t
C
C
C
C
C
15
20
20
15
15
pd
L
L
L
L
L
≤ 15 pF,
≤ 15 pF,
≤ 15 pF,
≤ 15 pF,
I
I
I
I
= –4.5 mA
= 5 mA
ns
PHZ
PLZ
PZH
PZL
OH
OL
OH
OL
ns
= –4.5 mA
= 5 mA
ns
ns
1%
0.7
30
4
‡
NTSC 40 IRE modulation wave,
f = 14.3 MSPS
s
Differential phase
degrees
ps
t
t
Aperture jitter time
AJ
Sampling delay time
ns
d(s)
f = 1 MHz
47
47
I
f = 3 MHz
I
44
42
f = 20 MSPS
s
f = 6 MHz
I
46
SNR
Signal-to-noise ratio
f = 10 MHz
I
45
dB
f = 3 MHz
I
45.2
44
f = 40 MSPS f = 6 MHz
s
I
f = 10 MHz
I
42
f = 1 MHz
7.64
7.61
7.47
7.16
7
I
f = 3 MHz
I
f = 20 MSPS
s
f = 6 MHz
I
ENOB
Effective number of bits
Bits
f = 10 MHz
I
f = 3 MHz
I
f = 40 MSPS
s
f = 6 MHz
6.8
43
I
f = 1 MHz
I
f = 3 MHz
35
41
42
I
f = 20 MSPS
s
f = 6 MHz
I
41
THD
Total harmonic distortion
dBc
dBc
f = 10 MHz
I
38
f = 3 MHz
I
40
f = 40 MSPS
s
f = 6 MHz
I
38
f = 20 MSPS
s
46
Spurious free dynamic range
f = 3 MHz
I
f = 40 MSPS
s
42
†
‡
Conditions marked MIN or MAX are as stated in recommended operating conditions.
Institute of Radio Engineers
NOTE 3:
C includes probe and jig capacitance.
L
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
t
t
w(L)
w(H)
CLK (Clock)
ANALOG IN
(Input Signal)
N+2
N+1
N–2
N+4
N
N+3
D1–D8
(Output Data)
N–3
N–1
N
N+1
t
pd
Figure 1. I/O Timing Diagram
Reference Level
(2.5 V)
OE
2.4 V
0.4 V
Hi-Z
Active
Active
Data Output
t
t
t
t
PZH
PZL
PHZ
PLZ
Figure 2. I/O Timing Diagram
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
ANALOG INPUT BANDWIDTH
SAMPLING FREQUENCY
0.5
200
150
V
T
A
= 5 V
DD
= 25°C
0
–0.5
–1
–1.5
–2
100
50
0
–2.5
–3
–3.5
–4
V
= 5 V, V
= 2.6 V, V = 0.6 V
RB
CC
CLK = 40 MHz
ANALOG IN = 100 k – 100 MHz Sine Wave
V = 2 V
RT
–4.5
–5
I
(PP)
0.1
1
10
100
0
5
10
20
25
30
35
40
15
f – Input Frequency – MHz
I
f
s
– Sampling Frequency – MHz
Figure 3
Figure 4
SIGNAL-TO-NOISE RATIO
vs
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
INPUT FREQUENCY
50
45
8
f
= 20 MHz
= 40 MHz
s
f
= 20 MHz
= 40 MHz
s
s
7
6
f
40
35
30
s
f
5
4
3
2
1
0
25
20
15
10
5
V
DD
V
RB
= 5 V, V = 1 V
I
= 2.6 V, V
V
DD
V
RB
= 5 V, V = 1 V
I
= 2.6 V, V
(PP)
= 0.6 V
(PP)
= 0.6 V
RT
RT
0
0
5
10
15
0
5
10
15
f – Input Frequency – MHz
I
f – Input Frequency – MHz
I
Figure 5
Figure 6
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
AMBIENT TEMPERATURE
DIFFERENTIAL NONLINEARITY
8
1
V = V
= 0.6 V – 2.6 V, 500 Hz
V
DD
V
RT
= 5 V, V = 1 V
, 3 MHz Sine Wave
I
ramp
= 2.6 V, V
I
(PP)
= 0.6 V, f = 20 MHz
0.8
V
= 0.6 V, V
= 5 V
DD
= 2.6 V, V
RT
RB
RB
s
f
s
= 40 MHz
0.6
0.4
T
= 25°C
A
7.5
0.2
7
6.5
6
0
–0.2
–0.4
–0.6
–0.8
–1
–40 –20
0
20
40
60
80
100
0
40
80
120
160
200
240
T
A
– Ambient Temperature – °C
Digital Output Code
Figure 7
Figure 8
INTEGRAL NONLINEARITY
FFT SPECTRUM
1
0
–10
V = V
ramp
= 0.6 V – 2.6 V, 500 Hz
I
V = 2 V
, 1 MHz Sine Wave
I
(PP)
= 2.6 V, V
0.8
V
= 2.6 V, V
= 0.6 V, V
= 5 V
DD
RT
RB
V
= 0.6 V
RT
= 20 MHz, T = 25°C
RB
f
= 40 MHz, T = 25°C
s
A
f
s
A
–20
–30
–40
–50
–60
0.6
0.4
0.2
0
–0.2
–70
–80
–0.4
–0.6
–0.8
–1
–90
–100
0
1
2
3
4
5
6
7
8
9
10
0
40
80
120
160
200
240
Digital Output Code
f – Frequency – MHz
Figure 9
Figure 10
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
APPLICATION INFORMATION
grounding and power supply considerations
A signal ground is a low-impedance path for current to return to the source. Inside the TLC5540 A/D converter,
the analog ground and digital ground are connected to each other through the substrate, which has a very small
resistance (~30 Ω) to prevent internal latch-up. For this reason, it is strongly recommended that a printed circuit
board (PCB) of at least 4 layers be used with the TLC5540 and the converter DGND and AGND pins be
connected directly to the analog ground plane to avoid a ground loop. Figure 11 shows the recommended
decoupling and grounding scheme for laying out a multilayer PC board with the TLC5540. This scheme ensures
that the impedance connection between AGND and DGND is minimized so that their potential difference is
negligible and noise source caused by digital switching current is eliminated.
TLC5540
V
GND
13 24
V
AGND
DDD
DDA
11
0.1 µF
2
14
0.1 µF
15
18 20 21
0.1 µF
0.1 µF 0.1 µF
Signal Plane
Analog Ground Plane
Analog Supply Plane
Digital Supply Plane
Signal Plane
Figure 11. AV , DV , AGND, and DGND Connections
DD
DD
printed circuit board (PCB) layout considerations
When designing a circuit that includes high-speed digital and precision analog signals such as a high speed
ADC, PCB layout is a key component to achieving the desired performance. The following recommendations
should be considered during the prototyping and PCB design phase:
Separate analog and digital circuitry physically to help eliminate capacitive coupling and crosstalk. When
separate analog and digital ground planes are used, the digital ground and power planes should be several
layers from the analog signals and power plane to avoid capacitive coupling.
Full ground planes should be used. Do not use individual etches to return analog and digital currents or
partial ground planes. For prototyping, breadboards should be constructed with copper clad boards to
maximize ground plane.
The conversion clock, CLK, should be terminated properly to reduce overshoot and ringing. Any jitter on
the conversion clock degrades ADC performance. A high-speed CMOS buffer such as a 74ACT04 or
74AC04 positioned close to the CLK terminal can improve performance.
Minimize all etch runs as much as possible by placing components very close together. It also proves
beneficial to place the ADC in a corner of the PCB nearest to the I/O connector analog terminals.
It is recommended to place the digital output data latch (if used) as close to the TLC5540 as possible to
minimize capacitive loading. If D0 through D7 must drive large capacitive loads, internal ADC noise may
be experienced.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
PRINCIPLES OF OPERATION
functional description
The TLC5540 uses a modified semiflash architecture as shown in the functional block diagram. The four most
significant bits (MSBs) of every output conversion result are produced by the upper comparator block CB1. The
four least significant bits (LSBs) of each alternate output conversion result are produced by the lower
comparator blocks CB-A and CB-B in turn (see Figure 12).
The reference voltage that is applied to the lower comparator resistor string is one sixteenth of the amplitude
of the refence applied to the upper comparator resistor string. The sampling comparators of the lower
comparator block require more time to sample the lower voltages of the reference and residual input voltage.
By applying the residual input voltage to alternate lower comparator blocks, each comparator block has twice
as much time to sample and convert as would be the case if only one lower comparator block were used.
V (1)
I
V (2)
I
V (3)
I
V (4)
I
ANALOG IN
(Sampling Points)
CLK1
CLK2
S(2)
CLK3
S(3)
CLK4
S(4)
CLK (Clock)
S(1)
C(1)
C(2)
C(3)
C(4)
Upper Comparators Block (CB1)
Upper Data
UD(0)
UD(1)
RV(1)
UD(2)
RV(2)
UD(3)
RV(3)
RV(0)
Lower Reference Voltage
S(1)
H(1)
C(1)
S(3)
H(3)
C(3)
Lower Comparators Block (CB-A)
Lower Data (A)
LD(–1)
LD(1)
H(0)
C(0)
S(2)
H(2)
C(2)
S(4)
H(4)
Lower Comparators Block (CB-B)
LD(–2)
LD(0)
LD(2)
Lower Data (B)
t
pd
OUT(–2)
OUT(–1)
OUT(0)
OUT(1)
D1–D8 (Data Output)
Figure 12. Internal Functional Timing Diagram
This conversion scheme, which reduces the required sampling comparators by 30 percent compared to
standard semiflash architectures, achieves significantly higher sample rates than the conventional semiflash
conversion method.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
PRINCIPLES OF OPERATION
functional description (continued)
TheMSBcomparatorblockconvertsonthefallingedgeofeachappliedclockcycle. TheLSBcomparatorblocks
CB-A and CB-B convert on the falling edges of the first and second following clock cycles, respectively. The
timing diagram of the conversion algorithm is shown in Figure 12.
analog input operation
The analog input stage to the TLC5540 is a chopper-stabilized comparator and is equivalently shown below:
φ2
S2
φ1
To Encoder Logic
To Encoder Logic
V
DDA
C
C
s
s
φ2
φ2
S3
φ1
φ1
φ1
φ2
ANALOG IN
S1
ref(N)
V
S(N)
To Encoder Logic
C
s
Figure 13. External Connections for Using the Internal Reference Resistor Divider
Figure 13 depicts the analog input for the TLC5540. The switches shown are controlled by two internal clocks,
φ1 and φ2. These are nonoverlapping clocks that are generated from the CLK input. During the sampling period,
φ1, S1isclosedandtheinputsignalisappliedtoonesideofthesamplingcapacitor, C . Alsoduringthesampling
s
period, S2 through S(N) are closed. This sets the comparator input to approximately 2.5 V. The delta voltage
is developed across C . During the comparison phase, φ2, S1 is switched to the appropriate reference voltage
s
for the bit value N. S2 is opened and V
– VC toggles the comparator output to the appropriate digital 1 or
ref(N)
s
0. The small resistance values for the switch, S1, and small value of the sampling capacitor combine to produce
the wide analog input bandwidth of the TLC5540. The source impedance driving the analog input of the
TLC5540 should be less than 100 Ω across the range of input frequency spectrum.
reference inputs – REFB, REFT, REFBS, REFTS
The range of analog inputs that can be converted are determined by REFB and REFT, REFT being the
maximum reference voltage and REFB being the minimum reference voltage. The TLC5540 is tested with
REFT = 2.6 V and REFB = 0.6 V producing a 2-V full-scale range. The TLC5540 can operate with
REFT – REFB = 5 V, but the power dissipation in the reference resistor increases significantly (93 mW
nominally). It is recommended that a 0.1 µF capacitor be attached to REFB and REFT whether using externally
or internally generated voltages.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
PRINCIPLES OF OPERATION
internal reference voltage conversion
Three internal resistors allow the device to generate an internal reference voltage. These resistors are brought
out on terminals V , REFTS, REFT, REFB, REFBS, and AGND. Two different bias voltages are possible
DDA
without the use of external resistors.
Internal resistors are provided to develop REFT = 2.6 V and REFB = 0.6 V (bias option one) with only two
external connections. This is developed with a 3-resistor network connected to V
. When using this feature,
DDA
connect REFT to REFTS and connect REFB to REFBS. For applications where the variance associated with
is acceptable, this internal voltage reference saves space and cost (see Figure 14).
V
DDA
A second internal bias option (bias two option) is shown in Figure 15. Using this scheme REFB = AGND and
REFT = 2.28 V nominal. These bias voltage options can be used to provide the values listed in the following
table.
Table 1. Bias Voltage Options
BIAS VOLTAGE
BIAS OPTION
V
V
V – V
RT RB
RB
RT
1
2
0.61
2.63
2.28
2.02
2.28
AGND
To use the internally-generated reference voltage, terminal connections should be made as shown in
Figure 14 or Figure 15. The connections in Figure 14 provide the standard video 2-V reference.
TLC5540
18
V
DDA
5 V (Analog)
R1
320 Ω NOM
REFTS
16
17
2.63 V dc
0.1 µF
0.1 µF
REFT
REFB
R
ref
270 Ω NOM
23
22
0.61 V dc
REFBS
AGND
R2
80 Ω NOM
21
Figure 14. External Connections Using the Internal Bias One Option
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
PRINCIPLES OF OPERATION
TLC5540
18
V
DDA
5 V (Analog)
R1
320 Ω NOM
REFTS
16
17
2.28 V dc
0.1 µF
REFT
REFB
R
ref
270 Ω NOM
23
22
0 V dc
REFBS
AGND
R2
80 Ω NOM
21
Figure 15. External Connections Using the Internal Bias Two Option
functional operation
Table 2 shows the TLC5540 functions.
Table 2. Functional Operation
DIGITAL OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
MSB
LSB
V
255
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
ref(T)
•
•
•
•
•
•
•
•
128
127
•
•
•
•
•
•
•
•
•
1
0
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
•
•
•
•
•
•
•
•
•
V
ref(B)
0
0
0
0
0
0
0
0
0
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5540
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER
SLAS105C – JANUARY 1995 – REVISED MAY 1999
MECHANICAL DATA
NS (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
14
16
20
24
DIM
10,50
10,50
12,90
15,30
A MAX
0,51
0,35
1,27
14
M
0,25
8
9,90
9,90
12,30
14,70
A MIN
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
7
0,25
0°–10°
A
1,05
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
4040062/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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