TLC555C [TI]
TLC555 LinCMOS⢠Timer;
| 型号： | TLC555C |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLC555 LinCMOS⢠Timer |
| 文件： | 总42页 (文件大小：1429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC555
SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
TLC555 LinCMOS™ Timer
Like the NE555, the TLC555 has a trigger level equal
to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of
the supply voltage. These levels can be altered by
use of the control voltage terminal (CONT). When the
trigger input (TRIG) falls below the trigger level, the
flip-flop is set and the output goes high. If TRIG is
above the trigger level and the threshold input
(THRES) is above the threshold level, the flip-flop is
reset and the output is low. The reset input (RESET)
can override all other inputs and can be used to
initiate a new timing cycle. If RESET is low, the flip-
flop is reset and the output is low. Whenever the
output is low, a low-impedance path is provided
between the discharge terminal (DISCH) and GND.
All unused inputs must be tied to an appropriate logic
level to prevent false triggering.
1 Features
1
•
Very low power consumption:
1-mW typical at VDD = 5 V
–
•
•
•
Capable of operation in astable mode
CMOS output capable of swinging rail to rail
High output current capability
–
–
Sink: 100-mA typical
Source: 10-mA typical
•
•
Output fully compatible with CMOS, TTL, and
MOS
Low supply current reduces spikes during output
transitions
•
•
Single-supply operation from 2 V to 15 V
Functionally interchangeable with the NE555; has
same pinout
Device Information(1)
•
•
ESD protection exceeds 2000 V per MIL-STD-
883C, method 3015.2
PART NUMBER
PACKAGE
BODY SIZE (NOM)
4.90 mm × 3.91 mm
9.81 mm × 6.38 mm
6.20 mm × 5.30 mm
5.00 mm × 4.40 mm
4.90 mm × 3.91 mm
9.81 mm × 6.38 mm
8.89 mm × 8.89 mm
9.60 mm × 6.67 mm
4.90 mm × 3.91 mm
SOIC (8)
Available in Q-temp automotive
PDIP (8)
SOP (8)
TLC555C
–
–
–
High-reliability automotive applications
Configuration control and print support
Qualification to automotive standards
TSSOP (14)
SOIC (8)
PDIP (8)
LCCC (20)
CDIP (8)
SOIC (8)
TLC555I
2 Applications
TLC555M
TLC555Q
•
•
•
•
•
•
•
Precision timing
Pulse generation
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Sequential timing
Time delay generation
Pulse width modulation
Pulse position modulation
Linear ramp generator
Simplified Schematic
RESET
4
CONT
5
V
DD
8
R
3 Description
R1
6
THRES
3
The TLC555 is a monolithic timing circuit fabricated
using the TI LinCMOS™ process. The timer is fully
compatible with CMOS, TTL, and MOS logic and
operates at frequencies up to 2 MHz. Because of its
high input impedance, this device supports smaller
timing capacitors than those supported by the NE555
or LM555. As a result, more accurate time delays and
oscillations are possible. Power consumption is low
across the full range of power-supply voltage.
OUT
R
S
1
R
2
TRIG
R
1
7
DISCH
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC555
SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
www.ti.com
Table of Contents
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
Power Supply Recommendations...................... 26
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 Recommended Operating Conditions....................... 6
6.3 Thermal Information.................................................. 6
8
9
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1 Receiving Notification of Documentation Updates 28
11.2 Community Resources.......................................... 28
11.3 Trademarks........................................................... 28
11.4 Electrostatic Discharge Caution............................ 28
11.5 Glossary................................................................ 28
6.4 Electrical Characteristics: VDD = 2 V for TLC555C,
VDD = 3 V for TLC555I............................................... 7
6.5 Electrical Characteristics: VDD = 5 V......................... 8
6.6 Electrical Characteristics: VDD = 15 V....................... 9
6.7 Operating Characteristics........................................ 11
6.8 Typical Characteristics............................................ 12
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision H (August 2016) to Revision I
Page
•
•
•
•
Added MIN value for input voltage in Absolute Maximum Ratings ........................................................................................ 6
Added discharge pin in Absolute Maximum Ratings.............................................................................................................. 6
Changed MIN supply voltage based on part number in Recommended Operating Conditions............................................. 6
Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for
TLC555I.................................................................................................................................................................................. 7
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added trigger, threshold capacitance TYP value in Electrical Characteristics: VDD = 5 V ..................................................... 8
Changed VOH test condition current to –1 mA in Electrical Characteristics: VDD = 5 V.......................................................... 8
Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 5 V .................................................... 9
Added trigger, threshold capacitance TYP value in Electrical Characteristics: VDD = 15 V ................................................... 9
Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 15 V ................................................ 10
Added Operating Characteristics to the Specifications section............................................................................................ 11
Added Supply Current vs Supply Voltage chart to the Typical Characteristics section ....................................................... 12
Added Control Impedance vs Temperature chart to the Typical Characteristics section .................................................... 12
Added Output Low Resistance vs Temperature chart to the Typical Characteristics section.............................................. 12
Added Output High Resistance vs Temperature chart to the Typical Characteristics section............................................. 12
Added Propagation Delay vs Control Voltage chart, VDD = 2 V to the Typical Characteristics section ............................... 12
Added Propagation Delay vs Control Voltage chart, VDD = 5 V to the Typical Characteristics section ............................... 12
Changed trigger high hold time to 1 µs in the Monostable Operation section ..................................................................... 15
Changed minimum monostable pulse width to 1 µs in the Monostable Operation section.................................................. 15
Changed Output Pulse Duration vs Capacitance chart scale down to 0.001 ms in the Monostable Operation section...... 15
Added more astable frequency formulas to the Astable Operation section ......................................................................... 17
Changed scale on Free-Running Frequency vs Timing Capacitance chart up to 2 MHz in the Astable Operation section 18
Added CONT pin table note to the Function Table in the Device Functional Modes section .............................................. 19
Changed the application curve chart in the Pulse-Width Modulation section ...................................................................... 22
Changed the application curve charts in the Pulse-Position Modulation section................................................................. 23
Added clamping diodes to Sequential Timer Circuit in the Sequential Timer section.......................................................... 24
2
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SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
Revision History (continued)
•
Added Designing for Improved ESD Performance section to the Application Information section...................................... 25
Changes from Revision G (November 2008) to Revision H
Page
•
Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 6
Deleted Dissipation Ratings table .......................................................................................................................................... 6
•
•
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SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
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5 Pin Configuration and Functions
D, P, PS, and JG Packages
8-Pin SOIC, PDIP, SOP, CDIP
Top View
VDD
GND
TRIG
1
2
3
4
8
7
6
5
DISCH
THRES
CONT
OUT
RESET
Pin Functions: D, P, PS, and JG Packages
PIN
SOIC, PDIP,
I/O
DESCRIPTION
NAME
SOP, CDIP
CONT
DISCH
GND
5
7
I
O
—
—
O
I
Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.
Open collector output to discharge timing capacitor.
Ground.
1
NC
—
3
No internal connection.
OUT
High current timer output signal.
RESET
THRES
TRIG
VDD
4
Active low reset input forces output and discharge low.
End of timing input. THRES > CONT sets output low and discharge low.
Start of timing input. TRIG < 1/2 CONT sets output high and discharge open.
Power-supply voltage.
6
I
2
I
8
—
4
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SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
PW Package
14-Pin TSSOP
Top View
FK Package
20-Pin LCCC
Top View
VDD
GND
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
TRIG
NC
DISCH
NC
NC
TRIG
NC
4
5
6
7
8
18 NC
17
DISCH
16 NC
15
14 NC
OUT
THRES
NC
OUT
NC
THRES
NC
RESET
CONT
8
Pin Functions: PW and FK
PIN
I/O
DESCRIPTION
NAME
CONT
DISCH
GND
TSSOP
LCCC
12
8
12
1
I
Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.
17
O
—
Open-collector output to discharge timing capacitor.
Ground.
2
1, 3, 4, 6, 8,
9, 11, 13, 14,
16, 18, 19
2, 4, 6,
9, 11, 13
NC
—
No internal connection.
OUT
5
7
7
O
I
High current timer output signal.
RESET
THRES
TRIG
VDD
10
15
5
Active low reset input forces output and discharge low.
End of timing input. THRES > CONT sets output low and discharge low.
Start of timing input. TRIG < 1/2 CONT sets output high and discharge open.
Power-supply voltage.
10
3
I
I
14
20
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)Continuous total power dissipation and lead temperature
parameters from Absolute Maximum Ratings
MIN
–0.3
–0.3
–0.3
MAX
18
UNIT
(2)
Supply, VDD
Voltage
Current
Input, any input
VDD
18
V
Discharge
Sink, discharge or output
Source, output, IO
150
15
mA
°C
C-suffix
I-suffix
0
70
–40
–40
–55
–65
–65
85
Operating, TA
Q-suffix
M-suffix
FK package
125
125
150
150
Temperature
Case, for 60 seconds
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network GND.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
MAX
15
UNIT
TLC555C
TLC555I
TLC555M
TLC555Q
TLC555C
TLC555I
TLC555M
TLC555Q
3
15
Supply voltage, VDD
V
5
15
5
15
0
70
–40
–55
–40
85
Operating free-air
temperature, TA
°C
125
125
6.3 Thermal Information
TLC555
D
FK
(LCCC)
JG
P
PS
(SOP)
PW
THERMAL METRIC(1)
UNIT
(SOIC)
(CDIP)
8 PINS
120
(PDIP)
(TSSOP)
14 PINS
135
8 PINS
113
58
20 PINS
n/a
8 PINS
58
8 PINS
120
72
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
37
81
48
61
55
36
110
35
69
77
Junction-to-top characterization
parameter
ψJT
11
54
n/a
n/a
4.3
45
103
31
26
35
32
68
12
77
°C/W
°C/W
°C/W
Junction-to-board characterization
parameter
ψJB
Junction-to-case (bottom) thermal
resistance
RθJC(bot)
n/a
n/a
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
6.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
TLC555C
TLC555I
MIN
0.95
1.6
TYP
MAX
1.65
2.4
UNIT
1.33
25°C
VIT
Threshold voltage
V
TLC555C
TLC555I
0.85
1.5
1.75
2.5
Full range
25°C
TLC555C
TLC555I
10
10
IIT
Threshold current
Trigger voltage
Trigger current
pA
V
TLC555C
TLC555I
75
Max
150
0.67
1
TLC555C
TLC555I
0.4
0.71
0.3
0.95
1.29
1.05
1.39
25°C
VI(TRIG)
TLC555C
TLC555I
Full range
25°C
0.61
TLC555C
TLC555I
10
10
II(TRIG)
pA
V
TLC555C
TLC555I
75
Max
150
1.1
1.1
TLC555C
TLC555I
0.4
0.4
0.3
0.3
1.5
1.5
2
25°C
VI(RESET) Reset voltage
TLC555C
TLC555I
Full range
Max
1.8
TLC555C
TLC555I
66.7%
66.7%
0.03
Control voltage (open-circuit) as a
percentage of supply voltage
TLC555C
0.2
0.2
IOL = 1 mA, 25°C
IOL = 1 mA, Full range
25°C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
TLC555C
TLC555I
0.03
Discharge switch on-stage
voltage
V
nA
V
0.25
0.375
0.1
0.1
Discharge switch off-stage
current
0.5
Max
120
1.9
1.5
2.5
1.5
2.5
IOH = –300 µA, 25°C
2.85
VOH
High-level output voltage
Low-level output voltage
Supply current(2)
IOH = –300 µA,
Full range
0.07
0.07
0.3
0.3
IOL = 1 mA, 25°C
IOL = 1 mA, Full range
25°C
VOL
V
0.35
0.4
250
250
400
500
IDD
µA
pF
Full range
80
90
Power dissipation
capacitance(3)(4)
CPD
25°C
(1) Full range is 0°C to 70°C the for TLC555C, and –40°C to 85°C for the TLC555I. For conditions shown as Max, use the appropriate
value specified in the Recommended Operating Conditions table.
(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
(3) CPD is used to determine the dynamic power consumption.
(4) PD = VDD2 fo (CPD + CL) where fo = output frequency, CL = output load capacitance, VDD = supply voltage
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6.5 Electrical Characteristics: VDD = 5 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
2.8
3.3
3.8
3.9
VIT
Threshold voltage
V
TLC555C, TLC555I,
TLC555M, TLC555Q
Full range
25°C
2.7
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
150
IIT
Threshold current
Trigger voltage
Trigger current
pA
V
Max
TLC555I
TLC555M, TLC555Q
5000
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
1.36
1.26
1.66
1.96
2.06
VI(TRIG)
TLC555C, TLC555I,
TLC555M, TLC555Q
Full range
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
150
II(TRIG)
pA
Max
TLC555I
TLC555M, TLC555Q
5000
Trigger, threshold capacitance
(each pin)
TLC555C, TLC555I,
TLC555M, TLC555Q
CI
25°C
2.1
1.1
pF
V
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
0.4
0.3
1.5
1.8
VI(RESET) Reset voltage
TLC555C, TLC555I,
TLC555M, TLC555Q
Full range
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
150
II(RESET)
Reset current
pA
Max
TLC555I
TLC555M, TLC555Q
5000
Control voltage (open circuit) as a
percentage of supply voltage
TLC555C, TLC555I,
TLC555M, TLC555Q
Max
66.7%
0.14
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 10 mA, 25°C
0.5
0.6
Discharge switch on-stage
voltage
V
nA
V
IOL = 10 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
0.1
Discharge switch off-stage
current
TLC555C
0.5
120
120
Max
TLC555I
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOH = –1 mA, 25°C
4.1
4.1
4.8
VOH
High-level output voltage
Low-level output voltage
IOH = –1 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 8 mA, 25°C
0.21
0.4
TLC555C
0.5
0.5
0.6
VOL
V
IOL = 8 mA,
Full range
TLC555I
TLC555M, TLC555Q
(1) Full range is 0°C to 70°C the for TLC555C, –40°C to 85°C for the TLC555I, –40°C to 125°C for the TLC555Q, and –55°C to 125°C for
the TLC555M. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.
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Electrical Characteristics: VDD = 5 V (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 5 mA, 25°C
0.13
0.3
TLC555C
0.4
0.4
IOL = 5 mA,
Full range
TLC555I
TLC555M, TLC555Q
0.45
VOL
Low-level output voltage
V
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 3.2 mA, 25°C
0.08
170
115
0.3
TLC555C
0.35
0.35
0.4
IOL = 3.2 mA,
Full range
TLC555I
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
350
IDD
Supply current(2)
µA
pF
TLC555C
500
600
700
Full range
25°C
TLC555I
TLC555M, TLC555Q
Power dissipation
capacitance(3)(4)
TLC555C, TLC555I,
TLC555M, TLC555Q
CPD
(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
(3) CPD is used to determine the dynamic power consumption.
(4) PD = VDD2 fo (CPD + CL) where fo = output frequency, CL = output load capacitance, VDD = supply voltage
6.6 Electrical Characteristics: VDD = 15 V
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
9.45
10
10.55
VIT
Threshold voltage
V
TLC555C, TLC555I,
TLC555M, TLC555Q
Full range
25°C
9.35
10.65
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
150
IIT
Threshold current
Trigger voltage
Trigger current
pA
V
Max
TLC555I
TLC555M, TLC555Q
5000
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
4.65
4.55
5
5.35
5.45
VI(TRIG)
TLC555C, TLC555I,
TLC555M, TLC555Q
Full range
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
150
II(TRIG)
pA
Max
TLC555I
TLC555M, TLC555Q
5000
Trigger, threshold capacitance
(each pin)
TLC555C, TLC555I,
TLC555M, TLC555Q
CI
25°C
1.8
1.1
pF
V
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
0.4
0.3
1.5
1.8
VI(RESET) Reset voltage
TLC555C, TLC555I,
TLC555M, TLC555Q
Full range
25°C
TLC555C, TLC555I,
TLC555M, TLC555Q
10
TLC555C
75
150
II(RESET)
Reset current
pA
Max
TLC555I
TLC555M, TLC555Q
5000
(1) Full range is 0°C to 70°C for TLC555C, –40°C to 85°C for TLC555I, –40°C to 125°C for the TLC555Q, and –55°C to 125°C for
TLC555M. For conditions shown as Max, use the appropriate value specified in the Recommended Operating Conditions table.
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Electrical Characteristics: VDD = 15 V (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
Control voltage (open circuit) as a
percentage of supply voltage
TLC555C, TLC555I,
TLC555M, TLC555Q
Max
66.7%
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 100 mA, 25°C
0.77
1.7
1.8
Discharge switch on-stage
voltage
V
IOL = 100 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
0.1
Discharge switch off-stage
current
TLC555C
0.5
120
120
nA
Max
TLC555I
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOH = –10 mA, 25°C
12.5
12.5
13.5
13.5
14.2
14.2
14.2
14.6
14.9
1.28
IOH = –10 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOH = –5 mA, 25°C
VOH
High-level output voltage
V
IOH = –5 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOH = –1 mA, 25°C
IOH = –1 mA,
Full range
TLC555C, TLC555I,
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 100 mA, 25°C
3.2
TLC555C
3.6
3.7
3.8
IOL = 100 mA,
Full range
TLC555I
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 50 mA, 25°C
0.63
0.12
360
140
1
TLC555C
1.3
1.4
1.5
VOL
Low-level output voltage
V
IOL = 50 mA,
Full range
TLC555I
TLC555M, TLC555Q
TLC555C, TLC555I,
TLC555M, TLC555Q
IOL = 10 mA, 25°C
0.3
TLC555C
0.4
0.4
IOL = 10 mA,
Full range
TLC555I
TLC555M, TLC555Q
0.45
TLC555C, TLC555I,
TLC555M, TLC555Q
25°C
600
IDD
Supply current(2)
µA
pF
TLC555C
800
900
Full range
25°C
TLC555I
TLC555M, TLC555Q
1000
Power dissipation
capacitance(3)(4)
TLC555C, TLC555I,
TLC555M, TLC555Q
CPD
(2) These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
(3) CPD is used to determine the dynamic power consumption.
(4) PD = VDD2 fo (CPD + CL) where fo = output frequency, CL = output load capacitance, VDD = supply voltage
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6.7 Operating Characteristics
VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5 V to 15 V, CT = 0.1 μF
MIN
TYP
MAX
UNIT
Initial error of timing interval(1)
1%
3%
(2)
RA = RB = 1 kΩ to 100 kΩ
VDD = 5 V to 15 V, CT = 0.1 μF
RA = RB = 1 kΩ to 100 kΩ
Supply voltage sensitivity of timing interval
0.1
0.5
%/V
(2)
tr
Output pulse rise time
RL = 10 MΩ, CL = 10 pF
20
15
75
60
ns
ns
tf
Output pulse fall time
RL = 10 MΩ, CL = 10 pF
(2)
fmax
Maximum frequency in a-stable mode
RA = 470 Ω, CT = 200 pF RB = 200 Ω
1.2
2.1
MHz
(1) Timing interval error is defined as the difference between the measured value and the average value of a random sample from each
process run.
(2) RA, RB, and CT are as defined in Figure 12.
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6.8 Typical Characteristics
600
500
400
300
200
100
0
100
70
IO(on) ³ 1 mA
L » 0
VDD = 2 V, IO = 1 mA
C
40
20
TA = 25°C
VDD = 5 V, IO = 10 mA
10
7
tPHL
VDD = 15 V, IO = 100 mA
4
2
1
(1)
tPLH
-75
-50
-25
0
25
50
75
100
125
0
2
4
6
8
10
12
14
16
18
20
Temperature (°C)
Supply Voltage (V)
(1) The effects of the load resistance on these values must be
taken into account separately.
Figure 1. Discharge Switch On-State Resistance vs
Free-Air Temperature
Figure 2. Propagation Delay Times to Discharge Output
From Trigger and Threshold Shorted Together
vs Supply Voltage
300
250
200
150
100
50
90
-55èC
-40èC
0èC
25èC
70èC
85èC
125èC
VDD = 2V
VDD = 3V
VDD = 5V
VDD = 15V
80
70
60
50
40
30
20
0
0
2
4
6
8
10
12
14
16
-75
-50
-25
0
25
50
75
100
125
Supply Voltage (V)
Temperature (èC)
D001
D002
Figure 3. Supply Current vs Supply Voltage
Figure 4. Control Impedance vs Temperature
90
80
70
60
50
40
30
20
10
0
450
VDD = 2V, IO = 1mA
VDD = 3V, IO = 1mA
VDD = 5V, IO = 10mA
VDD = 15V, IO = 100mA
VDD = 2V, IO = 300mA
VDD = 3V, IO = 300mA
VDD = 5V, IO = 1mA
VDD = 15V, IO = 10mA
400
350
300
250
200
150
100
50
-75
-50
-25
0
25
50
75
100
125
-75
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D003
D004
Figure 5. Output Low Resistance vs Temperature
Figure 6. Output High Resistance vs Temperature
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Typical Characteristics (continued)
100
100
50
TPLH VDD = 2V
TPHL VDD = 2V
TPLH VDD = 5V
TPHL VDD = 5V
50
30
20
30
20
10
10
5
5
3
2
3
2
1
1
0.5
0.5
0.3
0.2
0.3
0.2
0.1
0.1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Control Voltage (V)
Control Voltage (V)
D007
D009
Figure 7. Propagation Delay vs Control Voltage
VDD = 2 V
Figure 8. Propagation Delay vs Control Voltage
VDD = 5 V
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7 Detailed Description
7.1 Overview
The TLC555 is a precision timing device used for general-purpose timing applications up to 2.1 MHz. All inputs
are level sensitive not edge triggered inputs.
7.2 Functional Block Diagram
RESET
4
CONT
5
V
DD
8
R
R1
6
THRES
3
OUT
R
S
1
R
2
TRIG
R
1
7
DISCH
GND
Pin numbers are for all packages except the PW and FK package. RESET can override TRIG, which can override
THRES (when CONT pin is 2/3 VDD).
The resistance of “R" resistors vary with VDD and temperature. The resistors match each other very well across VDD
and temperature for a temperature stable control voltage ratio.
7.3 Feature Description
7.3.1 Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the internal latch; the output goes high, and
discharge pin (DISCH) becomes open drain. Capacitor C then is charged through RA until the voltage across the
capacitor reaches the threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the
output of the threshold comparator resets the internal latch, the output goes low, the discharge pin goes low
which quickly discharges capacitor C.
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Feature Description (continued)
V
DD
(5 V to 15 V)
5
8
R
A
CONT
V
DD
4
7
RESET
DISCH
3
OUT
Output
6
2
THRES
TRIG
Input
GND
C
1
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 1 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 1 µs, which limits the minimum monostable pulse width
to 1 µs. The output pulse duration is approximately tw = 1.1 × RAC. Figure 11 is a plot of the time constant for
various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply
voltage, VDD. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is
constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
capacitor C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low
as long as the reset pulse is low. To prevent false triggering, when RESET is not used it must be connected to
VDD
.
10000
5000
1kW
10kW
100kW
1MW
2000
1000
500
10MW
200
100
50
20
10
5
Input Voltage
2
1
0.5
0.2
0.1
0.05
Output Voltage
0.02
0.01
0.005
0.002
0.001
0.01
0.1 0.2 0.5
1
2 3 5 710 20 50 100
1000
Capacitor Voltage
Capacitance (nF)
D006
Figure 11. Output Pulse Duration vs Capacitance
Time − 0.1 ms/div
CL = 0.01 µF
RA = 9.1 kΩ
See Figure 9
Figure 10. Typical Monostable Waveforms
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Feature Description (continued)
7.3.2 Astable Operation
As shown in Figure 12, adding a second resistor, RB, to the circuit of Figure 9 and connecting the trigger input to
the threshold input causes the timer to self-trigger and run as a multi-vibrator. The capacitor C charges through
RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and
RB.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈ 0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the monostable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
V
DD
(5 V to 15 V)
0.01 mF
Open
(see Note A)
5
8
R
R
A
CONT
V
DD
4
7
RESET
DISCH
3
OUT
Output
6
2
B
t
THRES
TRIG
H
Output Voltage
t
L
GND
C
1
Decoupling CONT voltage to ground with a capacitor can improve
operation. This should be evaluated for individual applications.
Figure 12. Circuit for Astable Operation
Capacitor Voltage
Time − 0.5 ms/div
RB = 3 kΩ
RA = 5 kΩ
See Figure 12
C = 0.15 µF
Figure 13. Typical Astable Waveforms
Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and
low-level duration tL for frequencies below 100 kHz can be calculated as follows:
tH = 0.693 R + R
(
C
)
A
B
(1)
(2)
t = 0.693 R
C
( )
B
L
Other useful relationships are shown below:
period = t + t = 0.693 R + 2RB
(
C
)
H
L
A
(3)
(4)
(5)
(6)
(7)
1.44
R +2R
frequency »
C
)
B
(
A
tL
RB
Output driver duty cycle =
=
tH + tL RA + 2RB
tH
RB
Output waveform duty cycle =
= 1-
tH + tL
RA + 2RB
tL
RB
Low-to-high ratio =
=
tH RA + RB
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Feature Description (continued)
The formulas (1-7) do not account for any propagation delay times from the TRIG and THRES inputs to DISCH
output. These delay times add directly to the period and overcharge the capacitor which creates differences
between calculated and actual values that increase with frequency. In addition, the internal on-state resistance
ron during discharge adds to RB to provide another source of timing error in the calculation when RB is very low.
The equations below provide better agreement with measured values. The formulas Equation 8 represent the
actual low and high times when used at higher frequencies because propagation delay and discharge on
resistance is added to the formulas. Because the formulas are complex, a calculation tool, TLC555 Design
Calculator can be used to calculate the component values.
é
ù
ú
ú
û
æ
ç
è
ö
÷
ø
-tPLH
tc(H) = CT (RA + R ) In 3 - exp
+ t
ê
B
PHL
CT (RB + ron
)
ê
ë
é
ù
ú
ú
û
æ
ö
÷
ø
-tPHL
tc(L) = CT (RB + ron ) In 3 - exp
+ t
ê
ç
PLH
CT (RA + RB )
ê
ë
è
(8)
t
c(L)
t
c(H)
V
DD
t
PHL
2/3 V
DD
1/3 V
DD
GND
t
PLH
Figure 14. Trigger and Threshold Voltage Waveform
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Feature Description (continued)
2000
1000
500
1kW
10kW
100kW
1MW
200
100
50
10MW
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1 0.2 0.5 1 2 3 5 710 20 50 100
Capacitance (nF)
1000
10000
D012
Figure 15. Free-Running Frequency vs Timing Capacitance
Resistance = RA + 2 × RB
7.3.3 Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 16 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during
the timing cycle.
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9
Figure 16. Divide-by-Three Circuit Waveforms
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7.4 Device Functional Modes
Table 1 shows the device truth table.
Table 1. Function Table
RESET
THRESHOLD
TRIGGER VOLTAGE(1)
OUTPUT
DISCHARGE SWITCH
VOLTAGE(1)
VOLTAGE(1)
Irrelevant
Irrelevant(2)
>MAX
<MIN
>MAX
>MAX
>MAX
Irrelevant
<MIN
L
H
L
On
Off
On
>MAX
>MAX
<MIN
As previously established
(1) For conditions shown as MIN or MAX, use the appropriate value specified under Electrical Characteristics: VDD = 5 V.
(2) CONT pin open or 2/3 VDD
.
COMPONENT COUNT
Transistors
Resistors
39
5
THRES
VDD
CONT
OUT
DISCH
GND
TRIG
RESET
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Figure 17. Equivalent Schematic
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLC555 timer device uses resistor and capacitor charging delay to provide a programmable time delay or
operating frequency. The Typical Applications section presents a simplified discussion of the design process.
Reset mode forces output and discharge low and provides a small reduction in supply current.
8.2 Typical Applications
8.2.1 Missing-Pulse Detector
The circuit shown in Figure 18 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is re-triggered continuously
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,
missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output
pulse as shown in Figure 19.
V
DD
(5 V to 15 V)
R
A
4
8
RESET
V
DD
Input
3
Output
OUT
2
5
TRIG
7
6
DISCH
CONT
THRES
0.01mF
GND
1
C
2N3906
Figure 18. Circuit for Missing-Pulse Detector
8.2.1.1 Design Requirements
Input fault (missing pulses) must be input high. An input stuck low cannot be detected because the timing
capacitor (C) remains discharged.
8.2.1.2 Detailed Design Procedure
Choose RA and C so that RA × C > [maximum normal input high time].
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Typical Applications (continued)
8.2.1.3 Application Curve
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
VDD = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 18
Figure 19. Timing Waveforms for Missing-Pulse Detector
8.2.2 Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 20 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 21 shows the resulting duty cycle versus control voltage transfer function. Attempting to
run under 10% duty cycle could result in inconsistent output pulses. Attempting to run close to 100% duty cycle
will result in frequency division by 2, then 3, then 4.
V
DD
(5 V to 15 V)
R
A
4
8
RESET
V
DD
3
7
6
2
5
OUT
Clock
Input
Output
TRIG
DISCH
THRES
Modulation
Input
CONT
(see Note A)
GND
1
C
A. The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of
modulation source voltage and impedance on the bias of the timer.
Figure 20. Circuit for Pulse-Width Modulation
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Typical Applications (continued)
8.2.2.1 Design Requirements
The clock input must have VOL and VOH levels that are less than and greater than 1/3 VDD, respectively. Clock
input VOL time must be less than minimum output high time, therefore a high (positive) duty cycle clock is
recommended. Minimum recommended modulation voltage is 1 V. Lower CONT voltage can greatly increase
threshold comparator’s propagation delay and storage time. The application must be tolerant of a nonlinear
transfer function; the relationship between modulation input and pulse width is not linear because the capacitor
charge is RC based with an negative exponential curve.
8.2.2.2 Detailed Design Procedure
Choose RA and C so that RA × C is same or less than clock input period. Figure 21 shows the non linear
relationship between control voltage and output duty cycle. Duty cycle is function of control voltage and clock
period relative to RC time constant.
8.2.2.3 Application Curve
100
Clock period = 1 RC
Clock period = 2.5 RC
80
60
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Control Voltage (V)
D015
Figure 21. Pulse-Width-Modulation vs Control Voltage
Clock Duty Cycle 98%, VDD = 5 V
8.2.3 Pulse-Position Modulation
As shown in Figure 22, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and thereby the time delay of a free-running oscillator. Figure 23 and Figure 24
shows the output frequency and duty cycle versus control voltage.
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Typical Applications (continued)
V
DD
(5 V to 15 V)
R
R
4
8
A
RESET
TRIG
V
DD
3
OUT
Output
2
5
7
6
DISCH
THRES
Modulation
Input
(see Note A)
B
CONT
GND
C
A. The modulating signal can be direct or capacitively coupled to CONT. For direct coupling, consider the effects of
modulation source voltage and impedance on the bias of the timer.
RA = 3 kΩ
Figure 22. Circuit for Pulse-Position Modulation
8.2.3.1 Design Requirements
RB = 309 kΩ
C = 1 nF
Both DC- and AC-coupled modulation input changes the upper and lower voltage thresholds for the timing
capacitor. Both frequency and duty cycle vary with the modulation voltage. Control voltage below 1 V could result
in output glitches instead of a steady output pulse stream
8.2.3.2 Detailed Design Procedure
The nominal output frequency and duty cycle for control voltage set to 2/3 of VDD can be determined using
formulas in Astable Operation section.
8.2.3.3 Application Curves
4
3.5
3
100
80
60
40
20
0
2.5
2
1.5
1
0.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Control Voltage (V)
Control Voltage (V)
D013
D014
Figure 23. Pulse-Position-Modulation Frequency
vs Control Voltage, VDD = 5 V
Figure 24. Pulse-Position-Modulation Duty Cycle
vs Control Voltage, VDD = 5 V
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Typical Applications (continued)
8.2.4 Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 25
shows a sequencer circuit with possible applications in many systems, and Figure 26 shows the output
waveforms.
V
DD
33 kW
R
33 kW
R
A
B
4
8
4
8
V
DD
OUT
4
8
V
DD
1N4148
1N4148
R
C
33 kW
RESET
V
RESET
RESET
DD
OUT
3
3
7
6
3
7
2
2
2
OUT
TRIG
TRIG
TRIG
0.001 mF
0.001 mF
7
6
S
DISCH
DISCH
DISCH
THRES
5
5
5
CONT
CONT
CONT
6
THRES
THRES
GND
GND
GND
1
1
1
0.01
mF
0.01
mF
0.01
mF
C
C
C
B
C
A
C
C
R
C
= 14.7 mF
= 100 kW
C
= 10 mF
= 100 kW
A
Output A
Output B
Output C
R
A
C
B
= 4.7 mF
R
B
= 100 kW
NOTE: S closes momentarily at t = 0.
Figure 25. Sequential Timer Circuit
8.2.4.1 Design Requirements
The sequential timer application chains together multiple monostable timers. The joining components are the
33-kΩ resistors and 0.001-µF capacitors. The output high to low edge passes a 10-µs start pulse to the next
monostable. A diode is needed to prevent over voltage on the trigger input when on the previous output's low to
high edge.
8.2.4.2 Detailed Design Procedure
The timing resistors and capacitors can be chosen using this formula: tw = 1.1 × R × C.
24
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TLC555
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SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
Typical Applications (continued)
8.2.4.3 Application Curve
t A
w
t A = 1.1 R C
A A
w
Output A
Output B
Output C
t B
w
t B = 1.1 R C
w B B
t C = 1.1 R C
C C
w
t C
w
t = 0
t − Time − 1 s/div
See Figure 25
Figure 26. Sequential Timer Waveforms
8.2.5 Designing for Improved ESD Performance
The TLC555 internal HBM and CDM protection allows for safe assembly in ESD controlled environments. In
applications that may expose pins of the TLC555 to ESD, additional protection is highly recommended. The test
board schematic below has bypass capacitors, current-limiting resistors, and voltage clamping TVS diodes to
provide additional protection for commonly exposed pins [Reset, Trig, and Output] against ESD.
C5
50V
1000pF
D1
BAT54WSTR
R1
100k
TP1
R2
C9
Reset
2.20k
C1
50V
1000pF
R3
10.0k
50V
1000pF
D6
BAT54WSTR
D2
BAT54WSTR
TP3
U1
VDD
R9
R4
10.0
3
Output
10.0
R5
10.0k
RESET
DISCH
THRES
TRIG
C10
50V
1000pF
D7
BAT54WSTR
5
1
C8
100V
0.01uF
C6
50V
C7
1000pF
TLC555CP
50V
1000pF
D4
BAT54WSTR
R6
100k
TP2
Trig
J1
C4
R7
10.0k
50V
0.1uF
D3
SMBJ15A-13-F
Vcc
J2
C11
50V
10uF
C12
50V
0.1uF
C3
50V
R8
10.0k
D5
BAT54WSTR
1000pF
GND
Figure 27. ESD Test Schematic
Copyright © 1983–2019, Texas Instruments Incorporated
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www.ti.com
Typical Applications (continued)
The table below gives the ESD protection levels recorded for different supply voltages and external components
populated. Using only passive components to protect the TLC555 with a single 15-V supply is not recommended
because the higher voltage allows for an unacceptable amount of current to flow through the device.
Table 2. ESD test result table
(1)
Supply Voltage
Just passive components populated. D1..D7 not populated(1)
All components populated
5 V
8 kV
12 kV
12 kV
15 V
Not recommended
(1) Sample results. Results may vary with populated components, board layout, and samples used.
9 Power Supply Recommendations
The TLC555 requires a voltage supply greater than or equal to 2 V, 3 V, or 5 V based the coldest ambient
temperature supported and a supply voltage less than or equal to 15 V. Adequate power supply bypassing is
necessary to protect associated circuitry and provide stable output pulses. Minimum recommended is 0.1-μF
ceramic in parallel with 1-μF electrolytic. Place the bypass capacitors as close as possible to the TLC555 and
minimize the trace length.
26
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TLC555
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SLFS043I –SEPTEMBER 1983–REVISED JULY 2019
10 Layout
10.1 Layout Guidelines
Standard PCB rules apply to routing the TLC555. The 0.1-μF ceramic capacitor in parallel with a 1-μF electrolytic
capacitor must be as close as possible to the TLC555. The capacitor used for the time delay must also be placed
as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity
and signal integrity.
Figure 28 is the basic layout for various applications.
•
•
•
•
•
C1—based on time delay calculations
C2—0.01-μF bypass capacitor for control voltage pin
C3—0.1-μF bypass ceramic capacitor
C4—1-μF electrolytic bypass capacitor
R1—based on time-delay calculations
10.2 Layout Example
C4
C3
GND
TRIG
OUT
VDD
DISCH
THRES
CONT
R1
C1
RESET
C2
Figure 28. Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
LinCMOS, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Product Folder Links: TLC555
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC555CD
TLC555CDG4
TLC555CDR
TLC555CDRG4
TLC555CP
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TL555C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL555C
TL555C
TL555C
TLC555CP
TLC555CP
P555
D
8
2500
2500
50
Green (RoHS
& no Sb/Br)
D
8
Green (RoHS
& no Sb/Br)
P
8
Green (RoHS
& no Sb/Br)
TLC555CPE4
TLC555CPS
TLC555CPSR
TLC555CPW
TLC555CPWR
TLC555CPWRG4
TLC555ID
P
8
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
PS
PS
PW
PW
PW
D
8
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SO
8
2000
90
Green (RoHS
& no Sb/Br)
P555
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
14
14
14
8
Green (RoHS
& no Sb/Br)
P555
2000
2000
75
Green (RoHS
& no Sb/Br)
P555
Green (RoHS
& no Sb/Br)
P555
Green (RoHS
& no Sb/Br)
TL555I
TL555I
TL555I
TL555I
TLC555IP
TLC555IDG4
TLC555IDR
D
8
75
Green (RoHS
& no Sb/Br)
D
8
2500
2500
50
Green (RoHS
& no Sb/Br)
TLC555IDRG4
TLC555IP
D
8
Green (RoHS
& no Sb/Br)
P
8
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC555IPE4
TLC555QDR
ACTIVE
PDIP
SOIC
SOIC
P
D
D
8
8
8
50
Green (RoHS
& no Sb/Br)
NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
TLC555IP
ACTIVE
ACTIVE
2500
2500
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
-40 to 125
TL555Q
TL555Q
TLC555QDRG4
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
OTHER QUALIFIED VERSIONS OF TLC555 :
Automotive: TLC555-Q1
•
Military: TLC555M
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC555CDR
TLC555CPWR
TLC555IDR
SOIC
TSSOP
SOIC
D
PW
D
8
14
8
2500
2000
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
6.4
6.9
6.4
6.4
6.4
5.2
5.6
5.2
5.2
5.2
2.1
1.6
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
TLC555QDR
TLC555QDRG4
SOIC
D
8
SOIC
D
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC555CDR
TLC555CPWR
TLC555IDR
SOIC
TSSOP
SOIC
D
PW
D
8
14
8
2500
2000
2500
2500
2500
340.5
367.0
340.5
350.0
350.0
338.1
367.0
338.1
350.0
350.0
20.6
35.0
20.6
43.0
43.0
TLC555QDR
TLC555QDRG4
SOIC
D
8
SOIC
D
8
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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