TLC556CDRG4 [TI]
DUAL LinCMOSE TIMERS; 双LinCMOSE定时器
| 型号： | TLC556CDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL LinCMOSE TIMERS |
| 文件： | 总18页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
D, J, OR N PACKAGE
(TOP VIEW)
Very Low Power Consumption . . . 2 mW
Typ at V = 5 V
DD
Capable of Operation in Astable Mode
1 DISCH
1 THRES
1 CONT
1 RESET
1 OUT
V
1
2
3
4
5
6
7
14
13
12
11
10
9
DD
CMOS Output Capable of Swinging Rail to
Rail
2 DISCH
2 THRES
2 CONT
2 RESET
2 OUT
High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ
1 TRIG
GND
Output Fully Compatible With CMOS, TTL,
and MOS
2 TRIG
8
Low Supply Current Reduces Spikes
During Output Transitions
FK PACKAGE
(TOP VIEW)
Single-Supply Operation From 2 V to 15 V
Functionally interchangeable With the
NE556; Has Same Pinout
description
3
2
1
20 19
18
2 THRES
1 CONT
4
5
6
7
8
The TLC556 series are monolithic timing circuits
fabricatedusingtheTILinCMOS process, which
provides full compatibility with CMOS, TTL, and
MOS logic and operates at frequencies up to
2 MHz. Accurate time delays and oscillations are
possible with smaller, less-expensive timing
capacitors than the NE556 because of the high
input impedance. Power consumption is low
across the full range of power supply voltages.
NC
NC
1 RESET
NC
17
2 CONT
NC
16
15
14
2 RESET
1 OUT
9 10 11 12 13
NC–No internal connection
Like the NE556, the TLC556 has a trigger level
approximately one-third of the supply voltage and
athresholdlevelapproximatelytwo-thirdsofthesupplyvoltage. Theselevelscanbealteredbyuseofthecontrol
voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high.
If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is
reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing
cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a
low-impedance path is provided between the discharge terminal and ground.
Whilethe CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE556.
These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures
at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in
handling these devices, as exposure to ESD may result in degradation of the device parametric performance.
All unused inputs should be tied to an appropriate logic level to prevent false triggering.
The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from
–40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of –55°C
to 125°C.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
AVAILABLE OPTIONS
PACKAGE
T
V
CHIP FORM
(Y)
A
DD
SMALL OUTLINE
(D)
CHIP CARRIER
(FK)
CERAMIC DIP
PLASTIC DIP
(N)
RANGE
RANGE
(J)
O°C
to
70°C
2 V
to
18 V
TLC556CD
TLC556lD
TLC556MD
TLC556CN
TLC556IN
TLC556MN
TLC556Y
–4O°C
to
85°C
3 V
to
18 V
–55°C
to
5 V
to
TLC556MFK
TLC556MJ
125°C
18 V
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC556CDR).
FUNCTION TABLE
RESET
VOLTAGE
TRIGGER
THRESHOLD
DISCHARGE
SWITCH
OUTPUT
†
†
†
VOLTAGE
Irrelevant
< MIN
VOLTAGE
Irrelevant
Irrelevant
>MAX
< MIN
> MAX
>MAX
> MAX
L
H
L
On
Off
>MAX
On
> MAX
< MIN
As previously established
†
For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics.
functional block diagram (each timer)
CONT
RESET
4
V
DD
3
14
R
R1
2
6
5
THRES
R 1
OUT
S
R
TRIG
R
1
DISCH
7
GND
RESET can override TRIG and THRES.
TRIG can override THRES.
Pin numbers shown are for the D, J, or N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
TLC556Y chip information
These chips, properly assembled, display characteristics similar to the TLC556 (see electrical table). Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T
J
max = 150°C
TOLERANCES ARE ±10%
61
ALL DIMENSIONS ARE IN MILS
NO BACKSIDE METALLIZATION
PIN (7) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP
97
FUNCTIONAL BLOCK DIAGRAM (EACH TIMER)
CONT
RESET
(4)
V
DD
(14)
(3)
R
R1
R
(2)
(6)
(5)
THRESH
1
OUT
S
R
TRIG
R
(1)
DISCH
(7)
GND
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
TLC556C
TLC556I
TLC556M
UNIT
V
Supply voltage, V
DD
Input voltage range, V
(see Note 1)
I
18
18
18
–0.3 to V
150
–0.3 to V
150
–0.3 to V
150
V
DD
DD
DD
Sink current, discharge or output
mA
mA
Source current, output
15
15
15
Continuous total power dissipation
Operating free-air temperature range
Storage temperature range
See Dissipation Rating Table
0 to 70
–40 to 85
–55 to 125
–65 to 150
260
°C
°C
–65 to 150
–65 to 150
Case temperature for 60 seconds
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds
FK package
J package
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
D or N package
260
260
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING FACTOR = 70°C
T
≤ 25°C
T
A
T
= 85°C
T = 125°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING POWER RATING
A
D
FK
J
950 mW
1375 mW
1375 mW
1150 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
608 mW
880 mW
880 mW
736 mW
494 mW
715 mW
715 mW
598 mW
N/A
275 mW
275 mW
N/A
N
recommended operating conditions
MIN
MAX
UNIT
Supply voltage, V
DD
2
0
15
70
V
TLC556C
TLC556I
TLC556M
Operating free-air temperature range, T
–40
–55
85
°C
A
125
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
TLC556I
= 2 V for TLC556C, V
= 3 V for
DD
DD
TLC556C
TYP
TLC556I
TYP
2
TEST
CONDITIONS
†
T
A
PARAMETER
Input threshold voltage
Threshold current
Trigger voltage
UNIT
MIN
0.95
0.85
MAX
1.65
1.75
MIN
1.6
MAX
25°C
Full range
25°C
1.33
2.4
2.5
V
IT
V
pA
V
1.5
10
75
10
150
1
MAX
25°C
0.4
0.3
0.67
0.95
1.05
0.71
0.61
1.29
1.39
V
(trigger)
(trigger)
Full range
25°C
10
75
10
150
1.1
I
Trigger current
pA
V
MAX
25°C
0.4
0.3
1.1
1.5
1.8
0.4
0.3
1.5
1.8
V
Reset voltage
(reset)
(reset)
Full range
25°C
10
75
10
I
Reset current
pA
MAX
150
Control voltage (open circuit) as
a percentage of supply voltage
MAX
66.7%
0.04
66.7%
0.03
25°C
Full range
25°C
0.2
0.2
Discharge switch on-state volt-
age
I
= 1 mA
V
nA
V
OL
0.25
0.375
0.1
0.5
1.9
0.1
120
1.9
Discharge switch off-state cur-
rent
MAX
25°C
1.5
1.5
1.5
2.5
V
V
High-level output voltage
Low-level output voltage
Supply current
I
I
= –300 µA
OH
OH
Full range
25°C
0.07
130
0.3
0.35
500
800
0.07
130
0.3
0.4
= 1 mA
V
OL
OL
Full range
25°C
500
I
See Note 2
µA
DD
Full range
1000
†
Full range is 0°C to 70°C for TLC556C and –40°C to 85°C for TLC556I.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
= 5 V
DD
TLC556C
TYP
TLC556I
TLC556M
TYP
TEST
CONDITIONS
†
PARAMETER
UNIT
V
T
A
MIN
2.8
MAX
3.8
MIN
TYP
MAX
3.8
MIN
2.8
MAX
3.8
25°C
Full range
25°C
3.3
2.8
2.7
3.3
3.3
Input threshold
voltage
V
IT
2.7
3.9
3.9
2.7
3.9
10
75
10
150
10
5000
1.66
Threshold current
Trigger voltage
Trigger current
Reset voltage
Reset current
pA
V
MAX
25°C
1.36
1.26
1.66
1.96
2.06
1.36
1.26
1.66
1.96
2.06
1.36
1.26
1.96
2.06
V
(trigger)
(trigger)
Full range
25°C
10
75
10
150
1.1
10
5000
1.1
I
pA
V
MAX
25°C
0.4
0.3
1.1
1.5
1.8
0.4
0.3
1.5
1.8
0.4
0.3
1.5
1.8
V
(reset)
(reset)
Full range
25°C
10
75
10
10
I
pA
MAX
150
5000
Control voltage (open
circuit) as a
percentage of supply
voltage
MAX
66.7%
0.15
66.7%
0.15
66.7%
25°C
Full range
25°C
0.5
0.6
0.5
0.6
0.15
0.6
0.5
Discharge switch
on-state voltage
I
= 10 mA
V
nA
V
OL
0.1
0.5
4.8
0.1
2
0.1
Discharge switch
off-state current
MAX
120
4.8
25°C
4.1
4.1
4.1
4.1
4.8
4.1
4.1
High-level output
voltage
V
V
I
I
I
I
= –1 mA
= 8 mA
OH
OH
OL
OL
OL
Full range
25°C
0.21
0.13
0.08
340
0.4
0.5
0.21
0.13
0.08
340
0.4
0.5
0.21
0.13
0.08
340
0.4
0.6
Full range
25°C
0.3
0.3
0.3
Low-level output
voltage
= 5 mA
V
OL
Full range
25°C
0.4
0.4
0.45
0.3
0.3
0.3
= 3.2 mA
Full range
25°C
0.35
700
1000
0.35
700
1200
0.4
700
1400
I
Supply current
See Note 2
µA
DD
Full range
†
Full range is 0°C to 70°C for TLC556C, –40°C to 85°C for TLC556I, and –55°C to 125°C for TLC556M.
NOTE 2:
These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics at specified free-air temperature, V
= 15 V
DD
TLC556C
TYP
TLC556I
TLC556M
TYP
TEST
CONDITIONS
†
T
PARAMETER
UNIT
V
A
MIN
9.45
9.35
MAX
10.55
10.65
MIN
TYP
MAX
MIN
9.45
9.35
MAX
10.55
10.65
10
9.45
9.35
10
10.55
10.65
10
25°C
Full range
25°C
V
Input threshold voltage
Threshold current
Trigger voltage
Trigger current
Reset voltage
IT
10
75
5
10
150
5
10
5000
5
pA
V
MAX
4.65
4.55
5.35
5.45
4.65
4.55
5.35
5.45
4.65
4.55
5.35
5.45
25°C
V
(trigger)
(trigger)
Full range
25°C
10
75
10
150
1.1
10
5000
1.1
I
pA
V
MAX
0.4
0.3
1.1
1.5
1.8
0.4
0.3
1.5
1.8
0.4
0.3
1.5
1.8
25°C
V
(reset)
Full range
25°C
10
75
10
10
I
Reset current
pA
(reset)
MAX
150
5000
Control voltage (open
circuit) as a percent-
age of supply voltage
MAX
66.7%
0.8
66.7%
0.8
66.7%
0.8
1.7
1.8
1.7
1.8
1.7
1.8
25°C
Full range
25°C
Discharge switch on-
state voltage
I
= 100 mA
V
OL
0.1
0.5
0.1
2
0.1
120
Discharge switch off-
state current
nA
MAX
12.5
12.5
13.5
13.5
14.2
14.2
14.2
12.5
12.5
13.5
13.5
14.2
14.2
14.2
12.5
12.5
13.5
13.5
14.2
14.2
14.2
25°C
I
I
I
I
I
I
= –10 mA
= –5 mA
= –1 mA
= 100 mA
= 50 mA
= 10 mA
OH
OH
OH
OL
OL
OL
Full range
25°C
14.6
14.9
1.28
0.63
0.12
0.72
14.6
14.9
1.28
0.63
0.12
0.72
14.6
14.9
1.28
0.63
0.12
0.72
High-level output
voltage
V
OH
V
Full range
25°C
Full range
25°C
3.2
3.6
1
3.2
3.7
1
3.2
3.8
1
Full range
25°C
Low-level output
voltage
V
OL
V
Full range
25°C
1.3
0.3
0.4
1.2
1.6
1.4
0.3
0.4
1.2
1.8
1.5
0.3
0.45
1.2
2
Full range
25°C
I
Supply current
See Note 2
mA
DD
Full range
†
Full range is 0°C to 70°C for TLC556C, –40°C to 85°C for TLC556I, and –55°C to 125°C for TLC556M.
NOTE 2:
These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
electrical characteristics, V
= 5 V, T = 25°C
A
DD
PARAMETER
Input threshold voltage
TEST CONDITIONS
MIN
TYP
3.3
MAX
UNIT
V
V
IT
2.8
3.8
Threshold current
10
pA
V
V
Trigger voltage
1.36
0.4
1.66
10
1.96
(trigger)
(trigger)
I
Trigger current
pA
V
V
Reset voltage
1.1
1.5
0.5
(reset)
I
Reset current
10
pA
V
(reset)
Discharge switch on-state voltage
Discharge switch off-state current
High-level output voltage
I
= 10 mA
0.15
0.1
OL
nA
V
V
V
I
I
I
I
= –1 mA
= 8 mA
4.1
4.8
OH
OH
OL
OL
OL
0.21
0.13
0.08
3.40
0.4
0.3
0.3
700
Low-level output voltage
= 5 mA
V
OL
= 2.1 mA
I
Supply current
See Note 2
µA
DD
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.
operating characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
DD
A
PARAMETER
TEST CONDITIONS
MIN
TYP
1%
0.1
20
MAX
3%
0.5
75
UNIT
†
V
= 5 V to 15 V,
R = R = 1 kΩ to 100 kΩ
A B
Initial error of timing interval
DD
Supply voltage sensitivity of timing interval
Output pulse rise time
C
= 0.1 µF,
See Note 3
%/V
ns
T
t
t
r
R
= 10 MΩ,
C
= 10 pF
L
L
Output pulse fall time
15
60
f
R
C
= 470 Ω,
= 200 pF,
R
= 200 Ω,
A
T
B
f
Maximum frequency in astable mode
1.2
2.1
MHz
max
See Note 3
†
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
NOTE 3: R , R , and C are as defined in Figure 3.
A
B
T
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES (TO DISCHARGE
OUTPUT FROM TRIGGER AND THRESHOLD
SHORTED TOGETHER)
DISCHARGE SWITCH ON-STATE RESISTANCE
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
600
100
I
C
T
≥ 1 mA
70
O(on)
≈ 0
V
DD
= 2 V, I = 1 mA
O
L
500
= 25°C
A
40
V
= 5 V, I = 10 mA
O
DD
400
300
20
V
= 15 V, I = 100 mA
O
DD
10
7
t
PHL
‡
200
100
4
t
PLH
2
1
0
–75 –50 –25
0
25
50
75 100 125
0
2
4
6
8
10 12 14 16 18 20
T
A
– Free-Air Temperature – °C
V
DD
– Supply Voltage – V
‡
The effects of the load resistance on these values must be
taken into account separately.
Figure 1
Figure 2
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
0.1 µF
t
L
t
H
R
R
A
B
V
DD
0.1 µF
t
PHL
CONT
V
DD
R
L
RESET
2/3 V
DD
TLC556
DISCH
Output
OUT
1/3 V
DD
THRES
TRIG
C
L
GND
GND
C
T
t
PLH
CIRCUIT
TRIGGER AND THRESHOLD VOLTAGE WAVEFORM
Figure 3. Astable Operation
Connecting the trigger input to the threshold input, as shown in Figure 3, causes the timer to run as a
multivibrator. The capacitor C charges through R and R to the threshold voltage level (approximately 0.67
T
A
B
V
) and then discharges through R only to the value of the trigger voltage level (approximately 0.33 V ).
DD
B DD
The output is high during the charging cycle (t ) and low during the discharge cycle (t ). The duty cycle is
H
L
controlled by the values of R , and R , and C , as shown in the equations below.
A
B
T
t
C
C
(R
R
R ) In 2 (In 2
0.693)
H
T
T
A
B
t
In 2
t
L
B
Period
t
C
(R
t
2R ) In 2
B
H
L
T
A
t
R
B
L
B
Output driver duty cycle
1
t
R
2R
H
L
A
B
t
R
H
Output waveform duty cycle
t
t
R
2R
H
L
A
B
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay from the trigger and threshold inputs to the
discharge output. These delay times add directly to the period and create differences between calculated and
actual values that increase with frequency. In addition, the discharge output resistance r adds to R to provide
on
B
another source of error in the calculation when R is very low or r is very high.
B
on
The equations below provide better agreement with measured values.
t
PLH
t
t
C
(R
R ) In
3
exp
exp
t
H
L
T
A
B
PHL
C
(R
r
)
on
T
B
t
PHL
C
(R
r
) In
on
3
t
T
B
PLH
C
(R
R )
T
A
B
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
The preceding equations and those given earlier are similar in that a time constant is multiplied by the logarithm
of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and
In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic
t
t
H
H
<1 and
L
terms can be substituted with good results. Duty cycles less than 50%
will require that
t
t
t
H
L
possibly R ≤ r . These conditions can be difficult to obtain.
A
on
In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT. An input
voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides
good results.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
(19,94)
0.785
(19,94)
0.910
(23,10)
0.975
(24,77)
C
0.755
(19,18)
0.755
(19,18)
0.930
(23,62)
0.280
(7,11)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, and GDIP1-T20
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997
MECHANICAL INFORMATION
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
SOIC
Drawing
5962-89503022A
5962-8950302CA
TLC556CD
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
1
1
None
None
POST-PLATE Level-NC-NC-NC
A42 SNPB Level-NC-NC-NC
D
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC556CDG4
TLC556CDR
TLC556CDRG4
TLC556CN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
N
14
14
14
14
50
2500
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TLC556CNE4
TLC556ID
ACTIVE
ACTIVE
PDIP
SOIC
N
D
14
14
25
50
None
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC556IDR
TLC556IN
ACTIVE
ACTIVE
SOIC
PDIP
D
N
14
14
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPD
Level-NC-NC-NC
TLC556INE4
TLC556MD
TLC556MDR
TLC556MFKB
TLC556MJ
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
LCCC
CDIP
CDIP
PDIP
N
D
D
FK
J
14
14
14
20
14
14
14
25
50
1
None
None
None
None
None
None
None
Call TI
Call TI
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
POST-PLATE Level-NC-NC-NC
ACTIVE
ACTIVE
1
ACTIVE
1
A42 SNPB
A42 SNPB
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
TLC556MJB
TLC556MN
ACTIVE
J
1
OBSOLETE
N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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dsp.ti.com
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Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
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Security
www.ti.com/opticalnetwork
www.ti.com/security
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www.ti.com/video
microcontroller.ti.com
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Video & Imaging
Wireless
www.ti.com/wireless
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Texas Instruments
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