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TLC5615CDGKRG4 [TI]

10-BIT DIGITAL-TO-ANALOG CONVERTERS; 10位数字 - 模拟转换器
TLC5615CDGKRG4
型号： TLC5615CDGKRG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

10-BIT DIGITAL-TO-ANALOG CONVERTERS
10位数字 - 模拟转换器

转换器 数模转换器 光电二极管
文件： 总21页 (文件大小：468K)
中文：  中文翻译
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
10-BIT DIGITAL-TO-ANALOG CONVERTERS  
FEATURES  
DESCRIPTION  
•
10-Bit CMOS Voltage Output DAC in an  
8-Terminal Package  
The TLC5615 is  
a
10-bit voltage output  
digital-to-analog converter (DAC) with a buffered  
reference input (high impedance). The DAC has an  
output voltage range that is two times the reference  
voltage, and the DAC is monotonic. The device is  
simple to use, running from a single supply of 5V. A  
power-on-reset function is incorporated to ensure  
repeatable start-up conditions.  
•
•
•
•
5V Single Supply Operation  
3-Wire Serial Interface  
High-Impedance Reference Inputs  
Voltage Output Range: 2 Times the Reference  
Input Voltage  
•
•
•
•
•
•
Internal Power-On Reset  
Digital control of the TLC5615 is over a three-wire  
serial bus that is CMOS compatible and easily  
interfaced to industry standard microprocessor and  
microcontroller devices. The device receives a 16-bit  
data word to produce the analog output. The digital  
inputs feature Schmitt triggers for high noise  
immunity. Digital communication protocols include  
the SPI™, QSPI™, and Microwire™ standards.  
Low Power Consumption: 1.75mW Max  
Update Rate of 1.21MHz  
Settling Time to 0.5LSB: 12.5µs Typ  
Monotonic Over Temperature  
Pin-Compatible With the Maxim MAX515  
The 8-terminal small-outline D package allows digital  
control of analog functions in space-critical  
applications. The TLC5615C is characterized for  
operation from 0°C to +70°C. The TLC5615I is  
characterized for operation from –40°C to +85°C.  
APPLICATIONS  
•
•
•
•
•
Battery-Powered Test Instruments  
Digital Offset and Gain Adjustment  
Battery Operated/Remote Industrial Controls  
Machine and Motion Control Devices  
Cellular Telephones  
D, P, OR DGK PACKAGE  
(TOP VIEW)  
DIN  
SCLK  
CS  
V
DD  
1
2
3
4
8
7
6
5
OUT  
REFIN  
AGND  
DOUT  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SPI, QSPI are trademarks of Motorola, Inc.  
Microwire is a trademark of National Semiconductor Corporation.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1996–2007, Texas Instruments Incorporated  
TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be  
more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
FUNCTIONAL BLOCK DIAGRAM  
_
+
DAC  
+
REFIN  
AGND  
OUT  
(Voltage Output)  
 2  
_
R
R
Power-ON  
Reset  
10-Bit DAC Register  
(LSB) (MSB)  
Control  
Logic  
CS  
2
0s  
4
SCLK  
Dummy  
10 Data Bits  
Bits  
DIN  
DOUT  
16-Bit Shift Register  
Terminal Functions  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
NO.  
1
DIN  
I
I
Serial data input  
SCLK  
CS  
2
Serial clock input  
Chip select, active low  
3
I
DOUT  
AGND  
REFIN  
OUT  
VDD  
4
O
Serial data output for daisy chaining  
Analog ground  
5
6
I
Reference input  
7
O
DAC analog voltage output  
Positive power supply  
8
PACKAGE/ORDERING INFORMATION  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI website at www.ti.com.  
2
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)(1)  
UNIT  
7V  
Supply voltage (VDD to AGND)  
Digital input voltage range to AGND  
Reference input voltage range to AGND  
Output voltage at OUT from external source  
Continuous current at any terminal  
–0.3V to VDD + 0.3V  
–0.3V to VDD + 0.3V  
VDD + 0.3V  
±20mA  
Operating free-air temperature range, TA  
TLC5615C  
TLC5615I  
0°C to +70°C  
–40°C to +85°C  
–65°C to +150°C  
+260°C  
Storage temperature range, Tstg  
Lead temperature 1,6mm (1/16 inch) from case for 10 seconds  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
MIN NOM  
MAX UNIT  
Supply voltage, VDD  
4.5  
2.4  
5
5.5  
V
V
High-level digital input voltage, VIH  
Low-level digital input voltage, VIL  
Reference voltage, Vref to REFIN terminal  
Load resistance, RL  
0.8  
V
2
2
2.048  
VDD–2  
V
kΩ  
°C  
°C  
TLC5615C  
TLC5615I  
0
70  
85  
Operating free-air temperature, TA  
40  
ELECTRICAL CHARACTERISTICS  
over recommended operating free-air temperature range, VDD = 5V ± 5%, Vref = 2.048V (unless otherwise noted)  
STATIC DAC SPECIFICATIONS  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
bits  
Resolution  
10  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
Integral nonlinearity, end point adjusted (INL)  
Differential nonlinearity (DNL)  
Zero-scale error (offset error at zero scale)  
Zero-scale-error temperature coefficient  
Gain error  
Vref = 2.048V,  
See  
See  
See  
See  
See  
See  
±1  
±0.5  
±3  
LSB  
Vref = 2.048V,  
Vref = 2.048V,  
Vref = 2.048V,  
Vref = 2.048V,  
Vref = 2.048V,  
±0.1  
3
LSB  
EZS  
EG  
LSB  
ppm/°C  
LSB  
±3  
Gain-error temperature coefficient  
Zero scale  
1
ppm/°C  
80  
80  
(7)(8)  
PSRR Power-supply rejection ratio  
See  
dB  
V
Gain  
Analog full scale output  
RL = 100kΩ  
2Vref(1023/1024)  
(1) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from  
the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code 1024.  
(2) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1LSB  
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)  
as a change in the digital input code. Tested from code 3 to code 1024.  
(3) Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).  
(4) Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax– Tmin).  
(5) Gain error is the deviation from the ideal output (Vref – 1LSB) with an output load of 10kΩ excluding the effects of the zero-scale error.  
(6) Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax– Tmin).  
(7) Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5V to 5.5V dc and measuring the proportion of this  
signal imposed on the zero-code output voltage.  
(8) Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5V to 5.5V dc and measuring the proportion of this signal  
imposed on the full-scale output voltage after subtracting the zero-scale change.  
3
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
VOLTAGE OUTPUT (OUT)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
VO  
Voltage output range  
RL= 10kΩ  
0
VDD–0.4  
0.5  
Output load regulation accuracy  
Output short circuit current  
Output voltage, low-level  
VO(OUT) = 2V,  
RL = 2kΩ  
LSB  
mA  
V
IOSC  
OUT to VDD or AGND  
20  
VOL(low)  
I
O(OUT)≤ 5mA  
0.25  
VOH(high) Output voltage, high-level  
IO(OUT)≤– 5mA  
4.75  
V
REFERENCE INPUT (REFIN)  
VI  
ri  
Input voltage  
0
VDD–2  
V
Input resistance  
Input capacitance  
10  
MΩ  
pF  
Ci  
5
8
DIGITAL INPUTS (DIN, SCLK, CS)  
VIH  
VIL  
IIH  
IIL  
High-level digital input voltage  
Low-level digital input voltage  
High-level digital input current  
Low-level digital input current  
Input capacitance  
2.4  
V
0.8  
±1  
±1  
V
VI = VDD  
VI = 0  
µA  
µA  
pF  
Ci  
DIGITAL OUTPUT (DOUT)  
VOH  
VOL  
Output voltage, high-level  
Output voltage, low-level  
IO = –2mA  
IO = 2mA  
VDD–1  
4.5  
V
V
0.4  
POWER SUPPLY  
VDD Supply voltage  
5
5.5  
V
VDD = 5.5V, No load,  
All inputs = 0V or VDD  
Vref = 0  
150  
250  
µA  
IDD  
Power supply current  
VDD= 5.5V, No load,  
All inputs = 0V or VDD  
Vref = 2.048V  
230  
350  
µA  
ANALOG OUTPUT DYNAMIC PERFORMANCE  
Vref = 1VPP at 1kHz + 2.048Vdc,  
code = 11 1111 1111(1)  
Signal-to-noise + distortion, S/(N+D)  
60  
dB  
(1) The limiting frequency value at 1VPP is determined by the output-amplifier slew rate.  
DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1)  
PARAMETER  
MIN  
NOM MAX  
UNIT  
ns  
tsu(DS)  
th(DH)  
Setup time, DIN before SCLK high  
Hold time, DIN valid after SCLK high  
Setup time, CS low to SCLK high  
Setup time, CS high to SCLK high  
Hold time, SCLK low to CS low  
Hold time, SCLK low to CS high  
Pulse duration, minimum chip select pulse width high  
Pulse duration, SCLK low  
45  
0
ns  
tsu(CSS)  
tsu(CS1)  
th(CSH0)  
th(CSH1)  
tw(CS)  
1
ns  
50  
1
ns  
ns  
0
ns  
20  
25  
25  
ns  
tw(CL)  
ns  
tw(CH)  
Pulse duration, SCLK high  
ns  
OUTPUT SWITCHING CHARACTERISTICS  
PARAMETER  
TEST CONDITIONS  
MIN NOM MAX UNIT  
50 ns  
tpd(DOUT)  
Propagation delay time, DOUT  
CL = 50pF  
4
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
OPERATING CHARACTERISTICS  
over recommended operating free-air temperature range, VDD = 5V ±5%, Vref = 2.048V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN TYP MAX UNIT  
ANALOG OUTPUT DYNAMIC PERFORMANCE  
CL = 100pF,  
SR  
Output slew rate  
RL = 10kΩ,  
0.3  
0.5  
V/µs  
TA= +25°C  
To 0.5LSB,  
RL = 10kΩ,  
(1)  
ts  
Output settling time  
Glitch energy  
CL = 100pF,  
12.5  
5
µs  
DIN = All 0s to all 1s  
nV-s  
REFERENCE INPUT (REFIN)  
(2)  
Reference feedthrough  
REFIN = 1VPP at 1kHz + 2.048Vdc  
REFIN = 0.2VPP + 2.048Vdc  
–80  
30  
dB  
Reference input  
bandwidth (f–3dB)  
kHz  
(1) Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of 000  
hex to 3FF hex or 3FF hex to 000 hex.  
(2) Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048Vdc + 1Vpp at 1kHz.  
PARAMETER MEASUREMENT INFORMATION  
CS  
t
t
t
h(CSH0)  
su(CSS)  
w(CS)  
t
t
t
t
h(CSH1)  
w(CH)  
w(CL)  
su(CS1)  
SCLK  
See Note A  
See Note C  
See Note A  
t
t
h(DH)  
su(DS)  
DIN  
t
pd(DOUT)  
Previous LSB  
See Note B  
MSB  
LSB  
DOUT  
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.  
B. Data input from preceeding conversion cycle.  
C. Sixteenth SCLK falling edge  
Figure 1. Timing Diagram  
5
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
TYPICAL CHARACTERISTICS  
OUTPUT SINK CURRENT  
vs  
OUTPUT PULLDOWN VOLTAGE  
OUTPUT SOURCE CURRENT  
vs  
OUTPUT PULLUP VOLTAGE  
30  
25  
20  
15  
10  
20  
18  
V
V
T
= 5 V  
V
V
T
= 5 V  
DD  
DD  
= 2.048 V  
= 2.048 V  
REFIN  
REFIN  
= 25°C  
= 25°C  
A
A
16  
14  
12  
10  
8
6
4
5
0
2
0
3.8 3.6 3.4 3.2  
3
1.2  
1.1  
5
4.8 4.6 4.4 4.2  
4
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9  
1
V
O
- Output Pullup Voltage - V  
V
O
- Output Pulldown Voltage - V  
Figure 2.  
Figure 3.  
SUPPLY CURRENT  
vs  
TEMPERATURE  
VREFIN TO V(OUT) RELATIVE GAIN  
vs  
INPUT FREQUENCY  
280  
240  
200  
160  
120  
80  
4
2
0
V
V
T
A
= 5 V  
DD  
= 0.2 V + 2.048 V dc  
REFIN  
PP  
= 25°C  
- 2  
- 4  
- 6  
- 8  
- 10  
- 12  
- 14  
V
V
T
A
= 5 V  
= 2.048 V  
= 25°C  
DD  
REFIN  
40  
0
- 60 - 40 - 20  
0
20 40 60 80 100 120 140  
1
100  
1 k  
10 k  
100 k  
t - Temperature - °C  
f - Input Frequency - Hz  
I
Figure 4.  
Figure 5.  
6
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
TYPICAL CHARACTERISTICS (continued)  
SIGNAL-TO-NOISE + DISTORTION  
vs  
INPUT FREQUENCY AT REFIN  
70  
60  
V
= 5 V  
= 25°C  
DD  
T
A
V
REFIN  
= 4 V  
PP  
50  
40  
30  
20  
10  
0
1 k  
10 k  
100 k  
300 k  
Frequency - Hz  
Figure 6.  
0.2  
0.15  
0.1  
0.05  
0
–0.05  
–0.1  
–0.15  
–0.2  
0
255  
511  
767  
1023  
Input Code  
Figure 7. Differential Nonlinearity With Input Code  
1
0.8  
0.6  
0.4  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1  
0
255  
511  
767  
1023  
Input Code  
Figure 8. Integral Nonlinearity With Input Code  
7
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TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
APPLICATION INFORMATION  
GENERAL FUNCTION  
The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital  
data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the  
same polarity as the reference input (see Table 1).  
An internal circuit resets the DAC register to all zeros on power up.  
DIN SCLK CS DOUT  
+
_
REFIN  
Resistor  
String  
DAC  
+
_
OUT  
R
R
AGND  
V
DD  
5 V  
0.1 µF  
Figure 9. TLC5615 Typical Operating Circuit  
Table 1. Binary Code Table (0V to 2VREFINOutput), Gain = 2  
INPUT(1)  
OUTPUT  
2ǒVREFINǓ1023  
1111  
1111  
:
11(00)  
1024  
:
2ǒVREFINǓ 513  
1000  
1000  
0111  
0000  
01(00)  
00(00)  
11(00)  
1024  
2ǒVREFINǓ 512  
0000  
+ V  
REFIN  
1024  
2ǒVREFINǓ 511  
1111  
:
1024  
:
1
1024  
0000  
0000  
0000  
0000  
01(00)  
00(00)  
2ǒVREFINǓ  
0 V  
(1) A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide.  
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TLC5615C, TLC5615I  
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SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
BUFFER AMPLIFIER  
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2kΩ load with a 100pF load  
capacitance. Settling time is 12.5µs typical to within 0.5LSB of final value.  
EXTERNAL REFERENCE  
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,  
the REFIN input resistance is 10MΩ and the REFIN input capacitance is typically 5pF independent of input  
code. The reference voltage determines the DAC full-scale output.  
LOGIC INTERFACE  
The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves  
the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic  
levels.  
SERIAL CLOCK AND UPDATE RATE  
Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:  
1
) t  
f
+
(SCLK)max  
t
ǒ
Ǔ
ǒ Ǔ  
w CL  
w CH  
or approximately 14MHz. The digital update rate is limited by the chip-select period, which is:  
ǒt  
ǓǓ) t  
t
+ 16   
) t  
p(CS)  
ǒ
Ǔ
ǒ
ǒ
Ǔ
w CH  
w CL  
w CS  
and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5µs limits  
the update rate to 80kHz for full-scale input step transitions.  
SERIAL INTERFACE  
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most  
significant bit first. The rising edge of the SLCK input shifts the data into the input register.  
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be  
clocked into the input register. All CS transitions should occur when the SCLK input is low.  
If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data  
sequence with the MSB first can be used as shown in Figure 10:  
12 Bits  
10 Data Bits  
x
x
MSB  
LSB  
2 Extra (Sub-LSB) Bits  
x = don’t care  
Figure 10. 12-Bit Input Data Sequence  
or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.  
16 Bits  
4 Upper Dummy Bits  
10 Data Bits  
x
x
MSB  
LSB  
2 Extra (Sub-LSB) Bits  
x = don’t care  
Figure 11. 16-Bit Input Data Sequence  
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TLC5615C, TLC5615I  
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SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.  
When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer  
requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT  
terminal (see Figure 1).  
The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data  
converter transfers.  
The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The  
hardware connections are shown in Figure 12 and Figure 13.  
The SPI and Microwire interfaces transfer data in 8-bit bytes; therefore, two write cycles are required to input  
data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC  
input register in one write cycle.  
SK  
SO  
I/O  
SI  
SCLK  
DIN  
Microwire  
Port  
TLC5615  
CS  
DOUT  
NOTE A: The DOUT-SI connection is not required for writing to  
the TLC5615 but may be used for verifying data  
transfer if desired.  
Figure 12. Microwire Connection  
SCK  
SCLK  
DIN  
MOSI  
TLC5615  
SPI/QSPI  
Port  
I/O  
CS  
DOUT  
MISO  
CPOL = 0, CPHA = 0  
NOTE A: The DOUT-MISO connection is not required for writing to the  
TLC5615 but may be used for verifying data transfer.  
Figure 13. SPI/QSPI Connection  
DAISY-CHAINING DEVICES  
DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the  
chain, providing that the setup time, tsu(CSS) (CS low to SCLK high), is greater than the sum of the setup time,  
tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements section).  
The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled  
output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT  
remains at the value of the last data bit and does not go into a high-impedance state.  
LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE-ENDED SUPPLIES  
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative.  
With a positive offset, the output voltage changes on the first code change. With a negative offset the output  
voltage may not change with the first code depending on the magnitude of the offset voltage.  
10  
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TLC5615C, TLC5615I  
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SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative  
supply rail is ground, the output cannot drive below ground and clamps the output at 0V.  
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage  
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.  
Output  
Voltage  
0 V  
DAC Code  
Negative  
Offset  
Figure 14. Effect of Negative Offset (Single Supply)  
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the  
dotted line if the output buffer could drive below the ground rail.  
For a DAC, linearity is measured between zero-input code (all inputs '0') and full-scale code (all inputs '1') after  
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not  
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is  
measured between full-scale code and the lowest code that produces a positive output voltage. For the  
TLC5615, the zero-scale (offset) error is ±3LSB maximum. The code is calculated from the maximum  
specification for the negative offset.  
POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT  
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.  
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected  
together at the low-impedance power-supply source. The best ground connection may be achieved by  
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents  
are well managed and there are negligible voltage drops across the ground plane.  
A 0.1µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads  
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the  
digital power supply.  
Figure 15 shows the ground plane layout and bypassing technique.  
Analog Ground Plane  
1
2
3
4
8
7
6
5
0.1 µF  
Figure 15. Power-Supply Bypassing  
SAVING POWER  
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output  
load when the system is not using the DAC.  
11  
Submit Documentation Feedback  
 
 
TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
AC CONSIDERATIONS  
Digital Feedthrough  
Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the  
DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital  
feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.  
Analog Feedthrough  
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog  
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to  
REFIN, and monitoring the DAC output.  
12  
Submit Documentation Feedback  
TLC5615C, TLC5615I  
www.ti.com  
SLAS142E–OCTOBER 1996–REVISED JUNE 2007  
Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from D Revision (August 2003) to E Revision ............................................................................................... Page  
•
•
Added ESD statement. ......................................................................................................................................................... 2  
Changed —moved package option table from front page.................................................................................................... 2  
13  
Submit Documentation Feedback  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-May-2007  
PACKAGING INFORMATION  
Orderable Device  
TLC5615CD  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC5615CDG4  
TLC5615CDGK  
TLC5615CDGKG4  
TLC5615CDGKR  
TLC5615CDGKRG4  
TLC5615CDR  
SOIC  
MSOP  
MSOP  
MSOP  
MSOP  
SOIC  
SOIC  
PDIP  
D
DGK  
DGK  
DGK  
DGK  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC5615CDRG4  
TLC5615CP  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLC5615CPE4  
TLC5615ID  
PDIP  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SOIC  
SOIC  
MSOP  
MSOP  
MSOP  
MSOP  
SOIC  
SOIC  
PDIP  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC5615IDG4  
TLC5615IDGK  
TLC5615IDGKG4  
TLC5615IDGKR  
TLC5615IDGKRG4  
TLC5615IDR  
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
DGK  
DGK  
DGK  
DGK  
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TLC5615IDRG4  
TLC5615IP  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
TLC5615IPE4  
PDIP  
P
50  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-May-2007  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
330  
330  
330  
330  
330  
(mm)  
12  
12  
0
TLC5615CDGKR  
TLC5615CDR  
TLC5615CDR  
TLC5615IDGKR  
TLC5615IDR  
DGK  
D
8
8
8
8
8
8
SITE 60  
SITE 60  
SITE 27  
SITE 60  
SITE 60  
SITE 27  
5.3  
6.4  
6.4  
5.3  
6.4  
6.4  
3.4  
5.2  
5.2  
3.4  
5.2  
5.2  
1.4  
2.1  
2.1  
1.4  
2.1  
2.1  
8
8
8
8
8
8
12  
12  
12  
12  
12  
12  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
D
DGK  
D
12  
12  
0
TLC5615IDR  
D
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
TLC5615CDGKR  
TLC5615CDR  
TLC5615CDR  
TLC5615IDGKR  
TLC5615IDR  
DGK  
D
8
8
8
8
8
8
SITE 60  
SITE 60  
SITE 27  
SITE 60  
SITE 60  
SITE 27  
346.0  
346.0  
342.9  
346.0  
346.0  
342.9  
346.0  
346.0  
336.6  
346.0  
346.0  
336.6  
29.0  
29.0  
D
20.64  
29.0  
DGK  
D
29.0  
TLC5615IDR  
D
20.64  
Pack Materials-Page 2  
MECHANICAL DATA  
MPDI001A – JANUARY 1995 – REVISED JUNE 1999  
P (R-PDIP-T8)  
PLASTIC DUAL-IN-LINE  
0.400 (10,60)  
0.355 (9,02)  
8
5
0.260 (6,60)  
0.240 (6,10)  
1
4
0.070 (1,78) MAX  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
0.015 (0,38)  
Gage Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.021 (0,53)  
0.430 (10,92)  
MAX  
0.010 (0,25)  
M
0.015 (0,38)  
4040082/D 05/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001  
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this  
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily  
performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should  
provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask  
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services  
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the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.  
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service  
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
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Data Converters  
DSP  
Applications  
Audio  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/audio  
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Military  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
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interface.ti.com  
logic.ti.com  
Logic  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/lpw  
Telephony  
Low Power  
Wireless  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2007, Texas Instruments Incorporated  

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