TLC5902HTQFP [TI]
LED DRIVER; LED驱动器
| 型号： | TLC5902HTQFP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LED DRIVER |
| 文件： | 总22页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
80 mA × 16 Bits and 120 mA × 8 Bits
Protection
Drive Capability and Output Counts
– WDT Function
– TSD Function
5 mA to 80 mA/10 mA to 120 mA Constant
Current Output Range
Clock Synchronized 8-Bit Parallel Input
Anode Common LED Type Applied
Constant Currency Accuracy of ±4%
(Maximum Error Between Bits)
CMOS Input Signal Level
(Schmitt-Triggered Input for All Input
Terminals)
Constant Current Output Terminals
– 0.4 V (Output Current 0 to 40 mA)
– 0.7 V (Output Current 40 to 80 mA)
4.5 V to 5.5 V Power Supply Voltage
15 V Maximum Output Voltage
256 Gray Scale Display With Pulse Width
Control 256 Steps
15 MHz Maximum Data Transfer Rate
Brightness Adjustment
4 MHz Maximum Gray Scale Clock
Frequency
– Output Current Adjustment for 32 Steps
(Adjustment for Brightness Deviation
Between LEDs)
– 8 Steps Brightness Control by 8 Times
Speed Gray Scale Control Clock
(Brightness Adjustment for Panel)
–20°C to 85°C Operating Free-Air
Temperature Range
100-Pin HTQFP Package
(PD = 4.7 W, T = 25°C)
A
description
The TLC5902 is a constant current driver that incorporates shift register, data latch, and constant current
circuitry with a current value adjustable and 256 gray-scale display that uses pulse width control. The output
current can be selected as maximum 80 mA with 16 bits or 120 mA with 8 bits. The current value of the constant
current output is set by one external resister. After this device is mounted on a printed-circuit board (PCB), the
brightness deviation between LEDs (ICs) can be adjusted using an external data input, and the brightness
control for the panel can be adjusted using the brightness adjustment circuitry. Moreover, the device
incorporates watchdog timer (WDT) circuitry, which turns the constant current output off when the scan signal
is stopped during dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns constant
current output off when the junction temperature exceeds the limit.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
HTQFP PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DIN4
DIN5
DIN6
DIN7
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DOUT5
DOUT6
DOUT7
NC
VCCANA
NC
TS_ENA
VCCLOG
NC
MODE
GNDLOG
BC_ENA
NC
OUT0
TEST1
NC
GNDLED
NC
GNDANA
WD_CAP
PV
IREF
CC
OUT15
TEST2
NC
GNDLED
NC
NC
OUT14
OUT13
NC
NC
GNDLED
NC
NC
OUT12
NC
OUT1
OUT2
NC
GNDLED
NC
NC
NC
OUT3
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
functional block diagram
Shift Register and Data Latch
BC_ENA
RSEL
Brightness Control
Register
DOUT0
DOUT7
DIN0
DIN7
ENABLE
DCLK
DCLK
Controller
16 × 8 Bits
Shift Register
Data Latch
LATCH
MODE
GSCLK
BLANK
GSOUT
BOUT
8 Bits
Gray Scale
Counter
16 × 8 Bits
Comparator
TS_ENA
TSD
WDT
DOWN
WDT
WD_CAP
16 Bits
Current Reference
Circuit
Constant Current Driver
IREF
OUT0
OUT15
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
functional block diagram for shift register and data latch
BC_ENA
To
8 Bits Gray Scale Counter
Current Reference
Circuitry
1 × 8 Bits Shift Register
(Brightness Control)
1 × 8 Bits Latch
(Brightness Control)
DIN(0–7)
RSEL
16 × 8 Bits
Shift Register
DOUT(0–7)
ENABLE
DCLK
(Gray Scale Data))
DCLK
Controller
Q0
Q7
Q15
MODE
16 × 8 Bits
Data Latch
(Gray Scale Data))
LATCH
Q0
Q15
Comparator
Comparator
Comparator
Constant Current Driver
Control Line
Data (8 Bits)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
equivalent input and output schematic diagrams
Input
VCCLOG
INPUT
GNDLOG
DOUT (0–7), GSOUT, BOUT
VCCLOG
OUTPUT
GNDLOG
DOWN
DOWN
GNDLOG
OUTn
OUTn
GNDLED
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
Brightness control enable. When BC_ENA is low, the brightness control function is disabled. At
this time, the brightness control latch is reset to 1Fh. Output current value is 100% of setting value
by an external resistor and the frequency division ratio of GSCLK is 1/1.
BC_ENA
85
I
Blank (Light off). When BLANK is high, all the output of the constant current driver is turned off.
Allthe output is turned on (LED on) synchronizing tothefallingedgeofGCLKafternextrisingedge
of GCLK when BLANK goes from high to low.
BLANK
BOUT
68
57
I
O
Blank signal delay. BOUT is output with the addition of delay time to BLANK.
package
surface
CONDUCTIVE
PAD
Heat sink pad
Clock input for data transfer. The input data of DIN is synchronized to the rising edge of DCLK, and
transferred to DOUT. DCLK is valid at the rising edge after ENABLE goes low.
DCLK
65
I
I
70,71,72,73,
76,77,78,79
DIN7–DIN0
DOUT7–DOUT0
DOWN
Input for shift register for both gray scale data and brightness control. It is 8 bits parallel data.
Output for shift register for both gray scale data and brightness control.
47,48,49,51,
52,53,54,55
O
Shutdown. DOWN is configured as an open collector. It goes low when the constant current output
is shut down by the WDT or TSD function.
60
O
I
ENABLE
GNDANA
64
43
Data transfer enable. When ENABLE is high, data is not transferred.
Analog ground. (Internally connected to GNDLOG and GNDLED)
5,10,15,20,29,
36,90,96
GNDLED
GNDLOG
GSCLK
LED driver ground (Internally connected to GNDANA and GNDLOG)
Logic ground. (Internally connected to GNDANA and GNDLED)
84
69
56
Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the
number of GSCLK counted is equal to the data latched.
I
GSOUT
O
Clock delay for gray scale. GSOUT is output with addition of delay time to GSCLK
Constant current control setting. LED current is set to the desired value by connecting an external
resistor between IREF and GND. The 38 times current is compared to current across external
resistor sink on output terminal.
IREF
40
I
Latch. WhenLATCHishigh, dataonshiftregistergoesthroughthelatch. WhenLATCHislow,data
is latched. Accordingly, if data on the shift register is changed during LATCH high, this new value
is latched.
LATCH
MODE
61
83
I
I
8/16 bits select. When the MODE is high, the 16 bits output is selected. When the MODE is low,
the 8 bits output is selected.
87,93,94,100,
3,7,8,12,13,17,
18,22,26,32,
33,39
OUT0–OUT15
O
Constant current output
PV
CC
41
LED driver power supply voltage
Shift register latch switching. When RSEL is low, the shift register and latch for gray scale are
selected. When RSEL is high, the shift register and latch for brightness control are selected.
RSEL
66
I
I
I
TEST1, TEST2
TS_ENA
88,38
80
TEST. Factory test terminal. TEST should be connected to GND for normal operation.
TSD (Thermal shutdown) enable. When TS_ENA is high, TSD is enabled. When TS_ENA is low,
TSD is disabled.
VCCANA
VCCLOG
45
81
Analog power supply voltage
Logic power supply voltage
WDT detection time adjustment. The capacitor for WDT detection time adjustment is connected
between WD_CAP and GND. When WD_CAP is directly connected to GND, the WDT function
is disabled.
WD_CAP
WD
42
62
I
I
WDT scan input. By applying a scan signal to this terminal, the scan signal can be monitored and
constant current output can be turned off. LED is protected from damage from burning when the
scan signal is stopped during the constant period. The scan signal should be applied to this
terminal by connecting W_CAP to GND even though no WDT function is used.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
Function Tables
Truth Table (Data)
BC_ENA ENABLE DCLK
RSEL LATCH MODE
DOUT0 – DOUT7
OPERATION/FUNCTION
L
X
X
X
X
X
No change
Data latch for brightness control is set to 1Fh.
Data transfer for gray scale and brightness
control does not occur.
X
H
X
X
X
X
No change
Shift register for
brightness control
Data of DIN0 to DIN7 is clocked into the shift
register for brightness control.
X
X
L
L
↑
↑
H
L
X
X
X
H
Data for shift register
before 16 bytes (written
before 16 times)
Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.
Shift register for gray
scale before 8 bytes
(written before 8 times)
Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.
X
L
↑
L
X
L
Shift register for brightness control goes through
data latch for brightness control.
H
X
H
X
X
X
X
X
X
H
L
H
H
L
X
X
X
No change
No change
No change
Shift register for gray scale goes through data
latch for gray scale.
The value for the shift register selected by RSEL
is latched.
X
Truth Table (Display/Protection)
BLANK GSCLK MODE WDT WD_CAP TS_ENA OUT0~15
OPERATION/
FUNCTION
DOWN
H
X
X
X
X
X
Off
Hi–Z
16 bits operation mode. The output is turned on if
allthegrayscaledataisnotzeroonthefallingedge
of GCLK after the next rising edge of GCLK when
BLANKgoesfromhightolow. Eachoutputturnsoff
on the falling edge of GSCLK, corresponding to
each gray scale data.
L
↓
H
X
X
X
Hi–Z
8 bits operation mode. The output is turned on if all
the gray scale data is not zero on the falling edge
of GCLK after the next rising edge of GCLK when
BLANKgoesfromhightolow. Eachoutputturnsoff
on the falling edge of GSCLK corresponding to
each gray scale data.
L
L
↓
L
X
X
X
X
Hi–Z
L
Recover when
the level of
WDT changes.
Turn off if the level of WDT is not changed within
time set by capacitor connected to WD_CAP.
X
X
CLK
capacitor
L
L
X
X
X
X
CLK
CLK
L
X
X
WDT function is disabled.
WDT function is disabled.
Hi–Z
Hi–Z
H
Set TS_ENA to
low for recovery
L
X
X
X
X
H
Turn off if junction temperature exceeds the limit.
L
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
†
absolute maximum ratings (see Note 1)
Logic supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC(LOG)
Supply voltage for constant current circuit, PV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Analog supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC(ANA)
Output current (DC), I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 mA
OL(C)
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Output voltage range, V(
Output voltage range, V(
Continuous total power dissipation at (or below) T = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W
Operating free air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 85°C
0.3 V
0.3 V
CC(LOG)
. . . . . . . . . . . . . . . . . . . . . –0.3 V to V
GSOUT) CC(LOG)
, V(
and V(
and V(
OUTn)
OUTn)
BOUT)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 0.3 V
DOWN)
A
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GNDLOG terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
recommended operating conditions
dc characteristics over recommended ranges of operating free-air temperature,
V
= V
= PV
= 4.5 V to 5.5 V (unless otherwise noted)
CC(LOG)
CC(ANA)
CC
MIN
NOM
MAX
UNIT
Logic supply voltage, V
CC(LOG)
4.5
4.5
5
5.5
5.5
5.5
0.3
V
Supply voltage for constant current circuit,
PV
5
5
0
V
V
V
CC
Analog power supply, V
4.5
CC(ANA)
Voltage between V , V(
CC
V
V
= V
– V
DEF1)
DEF1
CC(LOG)
= GND(LOG) – GND(ANA)
CC(LOG)
CC(ANA)
–0.3
(see Note 3)
– PV , V
– PV
CC CC(ANA)
CC
V
(DEF2)
Voltage between GND, V(
(see Note 3)
DEF2)
GND(LOG) – GND(LED), GND(ANA) –
GND(LED)
–0.3
0
0.3
V
High-level input voltage, V
IH
0.8 V
V
V
V
CC(LOG)
GND(LOG)
CC(LOG)
0.2 V
CC(LOG)
Low-level input voltage, V
Á
IL
V
= 4.5 V, DOUT0 to DOUT7,
CC(LOG)
BOUT, GSOUT
High-level output current, I
–1
1
O(H)
mA
V
= 4.5 V, DOUT0 to DOUT7,
CCLOG
BOUT, GSOUT
Low-level output current, I
O(L)
V
= 4.5 V, DOWN
5
mA
mA
CC(LOG)
OUT0 to OUT15
Constant output current, I
5
80
OL(C)
NOTE 3: Each voltage is supplied by single power supply, not a separated power supply.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
recommended operating conditions (continued)
ac characteristics over recommended ranges of operating free-air temperature,
V
= V
= PV = 4.5 V to 5.5 V (unless otherwise noted)
CC(LOG)
CC(ANA)
CC
MIN
TYP
MAX
15
UNIT
At single operation
DCLK clock frequency, f
MHz
(DCLK)
At cascade operation
10
DCLK pulse duration (high or low level), t
/t
20
ns
w(h) w(l)
Frequency division ratio 1/1
4
MHz
GSCLK clock frequency, f
(GSCLK)
Frequency division ratio 1/1, T = 25°C,
A
8
MHz
V
= V
= PV
= 5 V
CCLOG
CCANA
CC
GSCLK pulse duration (high or low level), t
/t
75
ns
MHz
ns
w(h) w(l)
WDT clock frequency, f
(WDT)
5
WDT pulse duration (high or low level), t
LAT pulse duration (high or low level), t
/t
w(h) w(l)
50
50
LATCH
ns
w(h)
Rise/fall time, t /t
r f
100
ns
DINn – DCLK
10
15
20
15
10
10
20
15
30
20
20
20
LATCH – DCLK
BLANK – GSCLK
ENABLE – DCLK
LATCH – GSCLK
RSEL – DCLK
Setup time, t
ns
su
RSEL – LATCH
DINn – DCLK
LATCH – DCLK
ENABLE – DCLK
RSEL – DCLK
Hold time, t
ns
n
RSEL – LATCH
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
electrical characteristics, MIN/MAX: V
= V
= PV
= 4.5 V to 5.5 V, T = –20°C to 85°C
CC A
CC(LOG)
CCANA
TYP: V
= V
= PV
= 5 V, T = 25°C (unless otherwise noted)
CC(LOG)
CC(ANA)
CC A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
= –1 mA, DOUT0 to DOUT7,
V
OH
CC(LOG)
–0.5V
V
V
High–level output voltage
V
OH
GSOUT, BOUT
I
= 1 mA, DOUT0 to DOUT7, GSOUT,
OL
BOUT
0.5
Low–level output voltage
Input current
V
OL
I
= 5 mA DOWN
0.5
OL
V = V or GND(LOG)
CC(LOG)
I
I
±1
µA
I
I
Input signal is static, TS_ENA = H,
WD_CAP = OPEN
1
(OG)
Supply current (logic)
Supply current (analog)
mA
mA
Data transfer,
GSCLK = 1 MHz
DCLK = 15 MHz,
I
18
30
(LOG)
LED turns on,
LED turns off,
R
R
= 590 Ω
= 590 Ω
3
3
5
5
(IREF)
(IREF)
I
(ANA)
R
R
= 1180 Ω, LED turns off
15
30
20
40
(IREF)
(IREF)
= 590 Ω,
LED turns off
V
= 1 V,
R
= 1180 Ω,
= 590 Ω,
= 1.24 V,
= 1.24 V,
= 590 Ω,
O
(IREF)
(IREF)
(IREF)
(IREF)
I
Supply current (constant current driver)
mA
25
50
40
80
35
70
45
90
10
(PVCC)
16 bits output turns on
V
O
= 1 V,
R
16 bits output turns on
V
R
= 1 V,
V
O
I
I
I
35
70
mA
mA
µA
OL(C1)
OL(C2)
lkg
= 1180 Ω
(IREF)
= 1 V,
Constant output current
V
R
V
O
= 590 Ω
(IREF)
V
O
= 15 V,
R
(IREF)
Constant output leakage current
LED turn off
V
V
= V
= 1.24 V,
= PV
= 5 V,
CC(LOG)
(IREF)
CC(ANA)
CC
= 590 Ω,
∆I
OL(C)
Constant output current error between bit
R
±1%
±4%
(IREF)
All bits turns on,
V
= 1 V
O
Changes in constant output current
depend on supply voltage
I∆
I∆
V
V
= 1.24 V
= 1.24 V,
±1%
±1%
160
±4%
±2%
170
8
V
V
OL(C1)
(IREF)
Changes in constant output current
depend on output voltage
R
= 1180 Ω,
(IREF)
(IREF)
OL(C2)
1 bit output turns on, V = 1 V to 3 V
O
TSD detection temperature (thermal
shutdown circuit)
T(
T(
Junction temperature
No external capacitor
150
1
°C
tsd)
WDT detection time (watch–dog timer
circuit)
3
ms
V
wdt)
V(
IREF)
Voltage reference
BC_ENA = L,
R
= 590 Ω
1.24
(IREF)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
switching characteristics, C = 15 pF
L
PARAMETER
TEST CONDITIONS
DOUT
MIN
TYP
12
MAX
UNIT
30
OUT
250
13
t
Rise time
Fall time
ns
r
f
GSOUT
30
30
20
BOUT
13
DOUT
8
OUT
150
10
t
ns
ns
GSOUT
25
25
BOUT
10
OUTn+1 – OUTn
BLANK ↑ – OUT0
GSCLK ↓ – OUT0
DCLK ↑ – DOUT
GSCLK – GSOUT
BLANK – BOUT
8
15
350
350
30
500
500
50
t
d
Propagation delay time
15
10
10
25
50
25
50
timing requirements
100%
90%
V
OR V
100%
IH
OH
V
V
OR V
IH
OH
50%
0%
10%
0%
OR V
IL
OL
V
IL
OR V
OL
t
t
f
r
t
d
V
V
OR V
100%
IH
OH
100%
V
V
IH
50%
0%
50%
0%
OR V
IL
OL
IL
t
t
w(l)
w(h)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
PRINCIPLES OF OPERATION
constant current output selection by user (80 mA × 16 bits or 120 mA × 8 bits)
When MODE terminal is set to high, output is selected as 80 mA × 16 bits. When MODE terminal is set to low,
output is selected as 120 mA × 8 bits. By this setting, the internal shift register and latch are changed. Note that
two constant output terminals should be tied, such as OUT0 to OUT1 and OUT2 to OUT3 when 8-bit output is
selected.
MODE
OUTPUT
H
L
80 mA x 16 bits
120 mA x 8 bits
setting for constant current value
On the constant current output terminals (OUT0 to OUT15), approximately 38 times the current that flows
through the external resistor, R (connectedbetweenIREFandGND), canflow. Theexternalresistorvalue
(IREF)
is calculated using the following equation.
I
(mA)
R
38 1.24(V)
(k )
(OUTn)
(IREF)
(1)
More current flows if IREF is connected to GND directly.
shift register latch for gray scale data
The shift register latch for gray scale data is set as 8 × 8 bits configuration each at 8 bit mode, and as 16 x 8
bits configuration each at 16-bit mode. By setting RSEL to low, the shift register latch for gray scale data is
8
selected. Data structure shows that DIN0 corresponds to LSB, and DIN7 to MSB. This results in 2 = 256 steps
gray scale. The latched data is compared to GSCLK (clock for gray scale) counts, and constant current output
continues to turn on until these values are equal.
shift register latch for brightness control
The shift register latch for brightness control is configured with 1 × 8 bits each. The data input terminal and latch
terminal are common to shift register latch for gray scale data. By setting RSEL to low, the shift register latch
for gray scale data is selected, and by setting RSEL to high, the shift register latch for brightness control is
selected. If the brightness control function is not used, BC_ENA terminal should be pulled low. Since the
brightness control latch is reset to initial value of 00011111h, it is not necessary to write data to shift register latch
for brightness control. When power is up, latch data is undetermined. Data should be written to shift register
latch when the brightness control function is used. Also, rewriting the latch value for brightness control is
inhibited when the LED is turned on.
RSEL
SHIFT REGISTER LATCH SELECTED
Shift register latch for gray scale data
Shift register latch for brightness control
L
H
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
PRINCIPLES OF OPERATION
write data to both shift register latches
The shift register latch is selected using the RSEL terminal. The data input method is the same for both shift
register latches. The data is applied to DIN0 to DIN7 of 8-bits data input terminal, and transferred synchronizing
to DCLK. The data of DIN0 to DIN7 is transferred to the direction from OUT0 to OUT15 synchronizing to DCLK.
The shift register for brightness control is 1-bit length resulting in one time of DCLK input. The shift register for
gray scale data is 8-bits length at 8-bit mode resulting in eight times of DCLK, and 16-bit length at 16-bit mode
resulting in 16 times of DCLK input. At the number of DCLK input for each case, output data appear on DOUT0
to DOUT7. When LATCH goes from low to high, data is latched internally. Then, when LATCH goes low, data
is held. RSEL switching should be done when DCLK and LATCH are low.
brightness control latch configuration
The brightness control latch is configured as DIN0 corresponds to LSB, and DIN7 to MSB. The lower 5 bits are
assigned for output current adjustment, and the upper 3 bits are for a frequency division ratio setting of GSCLK.
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
MSB
LSB
†
0
0
0
1
1
1
1
1
Frequency division ratio setting of GSCLK
BC_ENA is low.
Output current setting
†
output current adjustment – brightness adjustment between ICs
By using the lower 5 bits of the brightness control latch, output current can be adjusted to 32 steps. When output
current is set to 100% by the external resistor at 11111h of the latched value, it is adjusted as 1 step or 32 steps
of 1.6% current ratio between 100 and 51.6%. By using this function, the brightness control between modules
(ICs) can be adjusted, sending the desired data externally even if ICs are mounted on PCB. When BC_ENA
is pulled low, the latch is reset to the initial value of 00011111h, and the output current is set to 100%.
CODE
CURRENT RATIO (%)
20 (mA)
80 (mA)
V (TYP)
IREF
0.64
MSB 00000 LSB
51.6
10.3
41.3
11110
98.4
100
19.7
20.0
78.7
80.0
1.22
1.24
†
11111
†
BC_ENA is low.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
PRINCIPLES OF OPERATION
frequency division ratio setting for GSCLK(clock for gray scale) – panel brightness adjustment
By using the upper 3 bits of the brightness control latch, GSCLK can be divided into 1/1 to 1/8. If GSCLK is set
to 8 times the speed (256 × 8 = 2048) of the frequency during the horizontal scanning time, the brightness can
be adjusted to 8 steps by selecting the frequency division ratio. Thus, the total panel brightness can be adjusted
at once and applied to the brightness of day or night. When BC_ENA is pulled low, GSCLK is not divided. When
BC_ENA is pulled high, the brightness can be adjusted as shown in the following table.
FREQUENCY DIVISION RATIO
RELATIVE BRIGHTNESS RATIO
(%)
CODE
†
MSB 000 LSB
1/1
1/2
1/3
1/4
1/5
1/6
1/7
1/8
12.5
25.0
37.5
50.0
62.5
75.0
87.5
100
001
010
011
100
101
110
111
†
BC_ENA is low.
constant output current operation
The constant current output turns on (sink constant current) if all the gray-scale data latched into the gray-scale
latch is not zero on the falling edge of GCLK, after the next rising edge of GCLK when BLANK goes from high
to low. After that, the number of the falling edge is counted by the 8-bit gray scale counter. Output counted that
corresponds to gray-scale data is turned off (stop to sink constant current). If the shift register for gray scale is
updated during LATCH high, data on the gray-scale data latch is also updated, affecting the number of gray
scale of constant current output. Accordingly, during the on state of constant current output, LATCH is kept to
low and the gray-scale data latch is held. When unconnected constant current output terminals exist, operation
is complete after writing zero (data for LED turn off) to the corresponding gray-scale data latch. If this action is
not completed, the supply current (I
) in the constant current driver portion increases.
PVCC
protection
ThisdeviceincorporatesWDTandTSDfunctions. InWDTorTSDfunctions, thecurrentoutputisstopped(Logic
portion is still operating). By monitoring the DOWN terminal, these failures are detected immediately. Since
DOWN output is configured as an open collector, outputs of multiple ICs are brought together.
WDT
When the scan signal is stopped during a fixed period in dynamic scanning operation, the constant current
output is turned off, preventing the LED from burning damage. The time detected can be set using the external
capacitor (C1). The typical value is approximately 3 ms without a capacitor, 33 ms with a 1000 pF capacitor,
and 300 ms with a 0.01 µF capacitor. Once the scan signal is applied again, the abnormal status is released
and normal operation is resumed. During static operation, the WDT function is disabled, connecting WD_CAP
to GND. The scan signal should be applied to the WDT terminal even though the WDT function is not used.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
PRINCIPLES OF OPERATION
WDT Operational Time
T (ms) 3+0.03 × C1 (pF)
3000
300
33
TLC5902
Scan Signal
WDT
WD_CAP
C1
Figure 2. WDT Usage Example
3
3
10
4
10
5
10
0
C1 – External Capacitor – pF
Figure 1. WDT Operational Time
TSD (thermal shutdown)
When the junction temperature exceeds the limit, TSD functions and turns the constant current output off. When
TSD is used, TS_ENA is pulled high. When TSD is not used, TS_ENA is pulled low. To recover to normal
operation, the power supply is turned off or TS_ENA is pulled low.
noise reduction
concurrent switching noise reduction
The concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time.
To prevent this noise, the device has delay output terminals such as GSOUT and BOUT for GSCLK and BLANK
respectively. Connecting these outputs to GSCLK and BLANK terminals of the next stage IC allows differences
in the switching time between ICs to be made. When GSCLK is output to GSOUT through the device, duty is
changed, so that the number of stages to be connected will be limited to a maximum of 10 at GSCLK = 4 MHz.
output slope
The on and off time of constant current output at an output current of 80 mA is approximately 150 ns and 250 ns
respectively. It is effective in reducing concurrent switching noise that occurs when multiple outputs turn on or
off at the same time.
delay between constant current output
The constant current output has a delay time of approximately 8 ns between output. It means approximately
120 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for reduction of
concurrent switching noise as well as output slope. This delay time has the same value at 8-bits or 16-bits
operation mode.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
PRINCIPLES OF OPERATION
noise reduction (continued)
power supply
VCCLOG, VCCANA, and PVCC are supplied by a single power supply to minimize voltage differences between
these terminals.
The bypass capacitor is located between power supply and GND to eliminate the variation of power supply
voltage.
GND
Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.
heat sink pad
The heat sink pad should be connected to GND to eliminate the noise influence since it is connected to the
bottom side of the IC chip. Also, the desired thermal effect is obtained by connecting this pad to the PCB pattern
with better thermal conductivity.
3.2
4.7
2.4
1.48
0
0
–20
25
85
T
A
– Free-Air Temperature – °C
3
NOTES: A. IC is mounted on PCB. PCB size: 102 × 76 × 1.6 [mm ], four layers with internal two layer having plane. The thermal pad is soldered
2
to PCB pattern of 10 mm . For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.
VCCLOG = VCCANA = PVCC = 5 V, I
= 80 mA, I is typical value
CC
OL(C)
B. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.
Figure 3. Power Rating
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
PRINCIPLES OF OPERATION
90
80
70
60
50
40
30
20
Conditions : VO
1 V, V(IREF)
V(IREF)(V)
1.24 V
38
I
OL(C)(mA)
R
(IREF)(k
47
R(IREF)(k )
IOL(C)(mA)
NOTE: The output current is at 16 bit output.
When 8-bit output, it will be the current of sum of two
outputs. This sum current should be set up with the range
of 10 mA to 120 mA. The resistor, R , should be located
IRF
as close as possible to IREF terminal to eliminate the noise
influence.
10
0
0.1
1
10
R
– kΩ
(IREF)
Figure 4. Current on Constant Current Output vs External Resistor
100
90
R
R
R
80
70
= 590
= 670
Ω
Ω
IREF
IREF
= 780
= 940
60
50
Ω
Ω
IREF
R
R
R
IREF
IREF
IREF
= 1.18 k
Ω
Ω
40
30
= 1.57 k
20
10
0
R
R
= 2.35 k
= 4.70 k
Ω
IREF
IREF
Minimum voltage applied
Ω
0
0.1
0.2
0.3 0.4
0.5
O – Output Voltage –V
NOTE: VCCLOG = VCCANA = PVCC = 5 V, T = 25°C.
0.6
0.7 0.8
0.9
1.0
V
A
Figure 5. Current on Constant Current Output vs Voltage Applied To Constant Current Output Terminal
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RSEL
ENABLE
t
(ENABLE–DCLK)
1/f(DCLK)
su
t (ENABLE–DCLK)
h
DCLK
t
su
(DIN–DCLK)
t (DIN–DCLK) t
w(l)
(DCLK)
D0E_A
t
(DCLK)
h
w(h)
D0F_A
D7F_A
D0F_B
D7F_B
D00_A
D70_A
D01_A
D02_A
D00_B
D01_B
D71_B
D0E_B
D7E_B
D00_C
D70_C
D01_C
D71_C
D02_C
D72_C
DIN0
DIN7
D71_A
D72_A
D7E_A
D70_B
t (LATCH–DCLK)
h
t
(LATCH–DCLK)
su
LATCH
t
d
(DCLK–DOUT)
t
(LATCH)
w(h)
D00_A
D01_A
D71_A
D0E_A
D7E_A
D0F_A
D00_B
DOUT0
DOUT7
D70_A
D7F_A
D70_B
Figure 6. Timing Diagram (Shift Register for Gray Scale Data)
BC_ENA
RSEL
t
h
)
(RSEL–LATCH
ENABLE
t
h
(RSEL–DCLK)
t
su
(RSEL–DCLK)
DCLK
DIN0
D00_A
D01_A
D02_A
D72_A
D03_A
D04_A
D05_A
D75_A
D06_A
D76_A
D07_A
D77_A
D08_A
D78_A
D09_A
D79_A
D0A_A
D7A_A
D00_B
D70_B
D01_B
D71_B
DIN7
D70_A D71_A
(RSEL–LATCH )
D73_A D74_A
t
su
LATCH
#
D02_A
D05_A
D06_A
BCL_0
Default Value ”1”
Default Value ”0”
#
D72_A
D75_A
D05_A
D75_A
D76_A
BCL_7
DOUT0
D06_A
D76_A
D0n–2_N
D0n–1_N
D02_A
D07_A
D00_A
D0n–1_N
D7n–1_N
D0n_N
DOUT7
D7n–2_N
D77_A
D70_A
D7n–1_N
D72_A
D7n_N
#
Internal brightness control latch
Figure 7. Timing Diagram (Brightness Control Register)
LATCH
BLANK
t
su
(LATCH–GSCLK)
t (BLANK–GSCLK)
su
t
(BLANK–BOUT)
d
t (BLANK–OUT0)
d
1/f(GSCLK)
(GSCLK)
GSCLK
WDT
t
(GSCLK)
t
t (GSCLK–OUT0)
d
w(h)
w(l)
t (GSCLK–OUT0)
d
1/f(WDT)
t
(WDT)
t
(WDT)
w(h)
w(l)
t
wd
OFF
ON(Note1)
ON(Note1)
OFF
(Note1)
(Note1)
OFF
(Note1)
(Note1)
OUT0
t (OUTn+1–OUTn)
d
OUT15
OFF
OFF
OFF
DOWN
BOUT
HI–z
t (GSCLK–GSOUT)
d
GSOUT
NOTE 1: ON or OFF, or ON time is varied depending on the gray scale data and BLANK.
Figure 8. Timing Diagram (Constant Current Output)
TLC5902
LED DRIVER
SLLS382 – DECEMBER 1999
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
M
0,50
75
0,08
0,17
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
0,25
0,15
15,80
0°–7°
0,05
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
Thispadiselectricallyandthermallyconnectedtothebacksideofthedieandpossiblyselectedleads. Thedimensionsofthethermal
pad are 2 mm × 2 mm (maximum). The pad is centered on the bottom of the package.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments Incorporated.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1999, Texas Instruments Incorporated
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