TLC5911PZPG4 [TI]

LED DISPLAY DRIVER, PQFP100, GREEN, PLASTIC, HTQFP-100;


型号：	TLC5911PZPG4
厂家：	TEXAS INSTRUMENTS
描述：	LED DISPLAY DRIVER, PQFP100, GREEN, PLASTIC, HTQFP-100 驱动信息通信管理接口集成电路
文件：	总33页 (文件大小：594K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLLS402 − DECEMBER 1999

Drive Capability and Output Counts

− 80 mA (Current Sink) x 16 Bits

Protection

− Watchdog Timer (WDT) Function (Turn

Output Off When Scan Signal Stopped)

− Thermal Shutdown (TSD) Function (Turn

Output Off When Junction Temperature

Exceeds Limit)

Constant Current Output Range

− 5 to 80 mA (Current Value Setting for All

Output Terminals Using External Resistor

and Internal Brightness Control Register)

LOD

Constant Current Accuracy

− LED Open Detection (Detection for LED

Disconnection)

−

4 % (Maximum Error Between Bits)

Voltage Applied to Constant Current Output

Terminals

− Minimum 0.4 V (Output Current 5 mA to

‡

Data Input/Output

− Port A (for Data Display)

− Clock Synchronized 10 Bit Parallel Input

(Schmitt-Triggered Input)

− Clock Synchronized 10 Bit Parallel

Output (3-State Output)

− Port B (for Dot Correction Data)

− Clock Synchronized 7 Bit Parallel Input

(Schmitt-Triggered Input)

40 mA)

− Minimum 0.7 V (Output Current 40 mA to

80 mA)

1024 Gray Scale Display

− Pulse Width Control 1024 Steps

†

Brightness Adjustment

− All Output Current Adjustment for 64

Steps (Adjustment for Brightness

Deviation Between LED Modules)

− Output Current Adjustment by Output

(OUT0 to OUT15) for 128 Steps

(Adjustment for Brightness Deviation

Between Dots)

− Brightness Control by 16 Steps

Frequency Division Gray Scale Control

Clock (Brightness Adjustment for Panel)

− Clock Synchronized 7 Bit Parallel Output

Input/Output Signal Level

− CMOS Level

Power Supply Voltage

− 4.5 V to 5.5 V (Logic, Analog and

Constant Current)

− 3 V to 5.5 V (Interface)

Maximum Output Voltage . . . 15 V

Data Transfer Rate . . . 20 MHz (Max)

Gray Scale Clock Generation

− Gray Scale Control Clock Generation by

Internal PLL or External Input Selectable

Gray Scale Clock Frequency

− 16 MHz (Max) Using Internal PLL

− 8 MHz (Max) Using External Clock

Clock Invert/Noninvert Selectable at

Cascade Operation

− Clock Invert Selectable to Reduce

Changes in Duty Ratio

Operating Free-Temperature Range

−20°C to 85°C

100-Pin Package HTQFP (P = 4.7 W,

T = 25°C)

†

‡

Adjustable for these functions independently.

Allows to write all the data at port A by setting.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS402 − DECEMBER 1999

description

The TLC5911 is a constant current driver incorporating shift register, data latch, and constant current circuitry

with a current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display

using pulse width control. The output current is maximum 80 mA with 16 bits, and the current value of constant

current output can be set by one external resistor. The device has two channel I/O ports. The brightness

deviation between LED modules (ICs) can be adjusted by external data input from the display data port, and

the brightness control for the panel can be accomplished by the brightness adjustment circuitry. Independent

of these functions, the device incorporates the shift register and data latch to correct the deviation between

LEDs by adjusting the output current using data from the dot correction data port. Moreover, the device

incorporates WDT circuitry, which turns constant current output off when the scan signal stops during the

dynamic scanning operation, and TSD circuitry, which turns constant current output off when the junction

temperature exceeds the limit. Also the LED open detection (LOD) circuitry is used to make error signal output

at the LED disconnection.

pin assignments

PZP PACKAGE

(TOP VIEW)

GNDLED

OUT0

OUT1

GNDLED

OUT2

OUT3

GNDLED

OUT4

OUT5

GNDLED

OUT6

VCOIN

RBIAS

MAG0

MAG1

MAG2

PDOUT

GSPOL

GSCLK

BLANK

XENABLE

XOE

OUT7

GNDLED

OUT8

DCLK

XLATCH

DCCLK

XDCLAT

RSEL0

RSEL1

LEDCHK

WDTRG

XDOWN1

XDOWN2

BOUT

OUT9

GNDLED

OUT10

OUT11

GNDLED

OUT12

OUT13

GNDLED

OUT14

OUT15

GNDLED

XGSOUT

XPOUT

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SLLS402 − DECEMBER 1999

functional block diagram

XOE

BCENA

DCLK

DPOL

DOUT(9−0)

XDPOUT

DCLK

Control

XENABLE

DIN(9−0),

XLATCH

1 x 10 bit B.C.

Data Shift Register

Data Latch

16 x 10 bit

Data Shift Register

RSEL(1−0)

..........

16 x 10 bit

Data Latch

DCDIN(6−0),

XDCLAT,

DCCLK

..........

XPOUT

XGSOUT

MAG(2−0), GSPOL,

GSCLK, RBIAS,

VCOIN, PDOUT

10 bit

Clock Countor

16 x 10 bit

Data Comparator

PLL

BLANK

BOUT

OUT0

ꢦ ꢦ ꢦ

OUT15

..........

16 bit

LED Driver+LOD

WDCAP

WDTRG

WDT

TSD

XDOWN1

XDOWN2

LEDCHK

XDOWN2TST

..........

TSENA

16 bit

Current Controller

..........

IREF

16 x 7 bit

D.C. Data Latch

DCENA

..........

16 x 7 bit

D.C. Data Shift Register

DCDOUT(6−0)

Legend:

B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels.

D.C. (Dot Control): Adjustment for brightness deviation between dots.

NOTE: All the input terminals are with Schmitt triggered inverter except RBIAS, VCOIN, PDOUT, IREF and WDCAP.

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SLLS402 − DECEMBER 1999

functional block diagram for shift register and data latch

XOE

10 16

DATA

S/R

DATA

LATCH

DATA

Comparator

†

DCLK

DPOL

XENABLE

DCLK

Controller

DCCLK

DOUT(9−0)

HI−Z

DIN(9−0)

B.C.

S/R

B.C.

LATCH

Clock Counter

Current Controller

DCDIN(6−0)

XLATCH

XDCLAT

DCDOUT(6−0)

‡

7 16

RSEL(1−0)

D.C.

S/R

D.C.

LATCH

7 16

DATA

Comparator

7 16

Default

BCENA

DCENA

†

‡

Connecting to 16th 10-bit Bus

Connecting to 16th 7-bit Bus

Legend:

B.C. (Brightness Control): Adjustment for brightness deviation between LED modules, and between panels.

D.C. (Dot Control): Adjustment for brightness deviation between dots.

RSEL

CONNECTION

RSEL1

RSEL0

A − a, B − c

A − b, B − c

A − c

INHIBIT

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SLLS402 − DECEMBER 1999

equivalent input and output schematic diagrams

Input

VCCIF

DOUT0−9, DCDOUT0−6, XGSOUT, XPOUT, BOUT

VCCLOG

OUTPUT

INPUT

GNDLOG

OUTn

XDOWN1, XDOWN2

OUTn

GNDLOG

GNDLED

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Brightness control enable. When BCENA is low, the brightness control latch is set to the

default value. The output current value in this status is 100% of the value set by an external

resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high, writing to

brightness control latch is enabled.

BCENA

Blank (Light off). When BLANK is high, all output of the constant current driver are turned

off. When GSPOL is high, all the output is turned on (LED on) synchronizing to the falling

edge of GCLK after next rising edge of GSCLK when BLANK goes from high to low. When

GSPOL is low, all the output is turned on (LED on) synchronizing to the rising edge of GCLK

after next falling edge of GSCLK when BLANK goes from high to low.

BLANK

BOUT

BLANK buffered output

Clock input for data transfer. The input data is from DCDIN (port B) . The output data at

DCDOUT. All data on the shift register for dot correction data from DCDIN is shifted by 1 bit

and is synchronized to the rising edge of DCCLK.

DCCLK

DCDIN0 −

DCDIN6

86,87,88,

89,90,91,92

Input for 7 bit parallel data (port B). These terminals are used as shift register input for dot

correction data.

DCDOUT0 −

DCDOUT6

34,35,36,

37,38,39,40

Output for 7 bit parallel data (port B). These terminals are used as shift register output for

dot correction data.

Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.

At this time, the output current value is 100% of the value set by an external resistor.

DCENA

Clock input for data transfer. The input data is from DIN (port A) , all the data on the shift

synchronized to DCLK. Note that whether synchronizing to the rising or falling edge of DCLK

is dependent on the value of DPOL.

DCLK

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SLLS402 − DECEMBER 1999

Terminal Functions (Continued)

TERMINAL

NAME

I/O

DESCRIPTION

NO.

Input for 10 bit parallel data (port A). These terminals are inputs for shift register for gray

scale data, brightness control, and dot correction data. The register selected is determined

by RSEL0, 1.

76,77,78,79,80,

81,82,83,84,85

DIN0 − DIN9

Output for 10 bit parallel data (port A). These terminals are outputs for shift register for gray

scale data, brightness control, and dot correction data. The register selected is determined

by RSEL0, 1.

41,42,43,44,45,

46,47,48,49,50

DOUT0 − DOUT9

DPOL

Selects the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When

DPOL is low, the falling edge of DCLK is valid.

GNDANA

GNDLOG

Analog ground (Internally connected to GNDLOG and GNDLED)

Logic ground (Internally connected to GNDANA and GNDLED)

1,4,7,10,13,

16,19,22,25

GNDLED

LED driver ground (Internally connected to GNDANA and GNDLED)

Clock input for gray scale. When MAG0 through MAG2 are all low, GSCLK is used for pulse

width control. When MAG0 through MAG2 are not low, GSCLK is used for PLL timing control.

The gray scale display is accomplished by lighting the LED until the number of GSCLK or

PLL clocks counted is equal to the data latched.

GSCLK

Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid.

When GSPOL is low, the falling edge of GSCLK is valid.

GSPOL

IREF

Constant current value setting. LED current is set to the desired value by connecting an

external resistor between IREF and GND. The 38 times current is compared to current

across the external resistor sink on the output terminal.

I/O

LED disconnection detection enable. When LEDCHK is high, the LED disconnection

detection is enabled and XDOWN2 is valid. When LEDCHK is low, the LED disconnection

detection is disabled.

LEDCHK

PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is

set .

MAG0 − MAG2

73,72,71

No internal connection

2,3,5,6,8,9,11,

12,14,15,17,18,

20,21,23,24

OUT0 − DOUT15

Constant current output

PDOUT

RBIAS

I/O

Resistor connection for PLL feedback adjustment

Resistor connection for PLL oscillation frequency setting

Input/output port selection and shift register data latch switching.

When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to

port A, and the dot correction register latch is selected to port B.

When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to

port A, and the dot correction register latch is selected to port B.

RSEL0

RSEL1

When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port A

and no register latch is selected to port B.

TEST1 − TEST3

THERMAL PAD

TSENA

97,99,100

TEST. Factory test terminal. These terminals should be connected to GND.

Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.

TSD enable. When TSENA is high, TSD is enabled. When TSENA is low, TSD is disabled.

Analog power supply voltage

Package bottom

VCCANA

VCCLOG

Logic power supply voltage

VCCLED

LED driver power supply voltage

VCOIN

I/O

Capacitance connection for PLL feedback adjustment

WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor

between WDCAP and GND. When WDCAP is directly connected to GND, the WDT function

is disabled. In this case, WDTRG should be tied to high or low level.

WDCAP

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SLLS402 − DECEMBER 1999

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

WDTRG

NO.

WDT trigger input. By applying a scan signal to this terminal, the scan signal can be

monitored by turning the constant current output off and protecting the LED from the damage

of burning when the scan signal stops during the constant period designed.

Data latch for dot correction. When XDCLAT is high, data on the shift register for dot

correction data from DCDIN (port B) goes through latch. When XDCLAT is low, the data is

latched. Accordingly, if data on the shift register is changed during XDCLAT high, the new

value is latched (level latch).

XDCLAT

Shutdown. XDOWN1 is configured as open collector. It goes low when the constant current

output is shut down by the WDT or TSD function.

XDOWN1

LED disconnection detection output. XDOWN2 is configured as open collector. XDOWN2

goes low when a LED disconnection is detected.

XDOWN2

XDPOUT

DPOL output inverted

Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally

pulled up with 50 kΩ)

XDWN2TST

DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the

valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred.

XENABLE

XGSOUT

Clock output for gray scale. When MAG0 through MAG2 are all low, a clock with GSCLK

inverted appears on this terminal. When MAG0 through MAG2 are not low., PLLCLK

appears on this terminal.

Latch. When XLATCH is high, data on shift register from DIN (port A) goes through latch.

When XLATCH is low, data is latched. Accordingly, if the data on the shift register is changed

during XLATCH high, this new value is latched (level latch).

XLATCH

Data output enable. When XOE is low, the DOUT0−9 terminals are driven. When XOE is

high, the DOUT0−9 terminals go to a high-impedance state.

XOE

XPOUT

GSPOL output inverted

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SLLS402 − DECEMBER 1999

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Logic supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V

CC(LOG)

Supply voltage for constant current circuit, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V

Analog supply voltage, V

CC(LED)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V

CC(ANA)

Output current (DC), I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mA

OL(C)

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VCCLOG + 0.3 V

Output voltage range, V

, V

and V

− 0.3 V to VCCLOG+ 0.3 V

(DOUT) (DCDOUT) (BOUT) (XPOUT)

(XGSOUT)

Output voltage range, V and V

Storage temperature range, T

Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 W

Power dissipation rating at (or above) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38.2m W/°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 16 V

(XDOWNn)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

str

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GNDLOG terminal.

recommended operating conditions

dc characteristics

MIN

4.5

NOM

MAX

5.5

UNIT

Logic supply voltage, V

CC(LOG)

Supply voltage for constant current circuit, V

CC(LED)

5.5

Analog power supply, V

CC(ANA)

5.5

(DIFF1)

− V

CC(LOG)

CC(ANA)

CC(LED)

Voltage between V , V

CC (DIFF1)

−0.3

0.3

(DIFF2)

GND(LOG) − GND(ANA)

GND(LOG) − GND(LED)

GND(ANA) − GND(LED)

Voltage between GND, V

(DIFF2)

Voltage applied to constant current

output, V

OUT0 to OUT15 off

High−level input voltage, V

0.8 V

CC(LOG)

Low−level input voltage, V

GND(LOG)

0.2 V

CC(LOG)

= 4.5 V,

CC(LOG)

High−level output current, I

DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,

BOUT, XGSOUT, XPOUT

−1

= 4.5 V,

CC(LOG)

DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,

BOUT, XGSOUT, XPOUT

Low−level output current, I

= 4.5 V, XDOWN1, XDOWN2

°C

(CCLOG)

OUT0 to OUT15

Constant output current, I

OL(C)

Operating free−air temperature range, T

−20

PLL capacitance, C

(VCO)

µF

PLL resistor, R

At 16 MHz oscillation

kΩ

(BIAS)

(PD)

PLL resistor, R

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SLLS402 − DECEMBER 1999

recommended operating conditions (continued)

ac characteristics, V

= V = 4.5 V to5.5 V, TA =− 20 to85°C (unless otherwise noted)

CC(LED)

CC(LOG)

CC(ANA)

MIN

TYP

MAX

UNIT

At single operation

DCLK, DCCLK clock frequency, f

MHz

(DCLK) (DCCLK)

At cascade operation

DCLK, DCCLK pulse duration (high- or low-level), t

MHz

w(h) w(l)

GSCLK clock frequency, f

(GSCLK)

GSCLK pulse duration (high- or low-level), t

w(h) w(l)

PLLCLK clock frequency, f

(PLLCLK)

MHz

WDT clock frequency, f

(WDT)

WDT pulse duration (high- or low-level), t

w(h) w(l)

XLATCH, XDCLAT pulse duration (high-level), t

w(h)

Rise/fall time, t /t

r f

100

DINn − DCLK

DCDINn − DCCLK

BLANK − GSCLK

XENABLE − DCLK

XLATCH − DCLK

XLATCH − GSCLK

XDCLAT − DCCLK

RSEL − DCLK

RSEL − DCCLK

RSEL − XLATCH

RSEL − XDCLAT

Setup time, t

DINn − DCLK

DCDINn − DCCLK

XENABLE − DCLK

XLATCH − DCLK

XDCLAT − DCCLK

RSEL − DCLK

RSEL − DCCLK

RSEL − XLATCH

RSEL − XDCLAT

Hold time, t

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SLLS402 − DECEMBER 1999

electrical characteristics, LEDCHK = L, MIN/MAX: V

= V

= 4.5 V to 5.5 V,

CC(LOG)

CC(ANA)

CC(LED)

T = −20 to 85°C, TYP: V

= V

= 5 V, T = 25°C (unless otherwise noted)

CC(LOG)

CC(ANA)

CC(LED) A

PARAMETER

TEST CONDITIONS

= −1 mA, DOUTn, DCOUTn, XGSOUT,

MIN

TYP

MAX

UNIT

XPOUT, BOUT

CC(LOG)

−0.5

High-level output voltage

= 1 mA, DOUTn, DCOUTn, XGSOUT,

XPOUT, BOUT

0.5

Low-level output voltage

Input current

= 5 mA, XDOWN1, XDOWN2

0.5

V = V or GND(LOG)

CC(LOG)

µA

Input signal is static,

TSENA = H, WDCAP = OPEN,

No PLL is used

Input signal is static,

TSENA = H, WDCAP = OPEN,

PLL multiple ratio = 1042

Supply current (logic)

(LOG)

Data transfer,

DCLK = 20 MHz, GSCLK = 8 MHz

No PLL is used

Data transfer,

DCLK = 20 MHz, GSCLK = 15 kHz

PLL multiple ratio = 1042

BLANK = L, R

= 1200 Ω

= 600 Ω

= 1200 Ω

= 600 Ω

6.5

(IREF)

Supply current (analog)

(ANA)

(IREF)

LED turn off, R

(IREF)

Supply current

(constant current driver)

= 1 V, R = 1200 Ω

(IREF)

(LED)

all output bits turn on

= 1 V, R = 600 Ω

(IREF)

all output bits turn on

Constant output current

(includes error between bits)

= 1 V, V

= 1.2 V,

(IREF)

= 1200 W

OL(C1)

(IREF)

Constant output current

(includes error between bits)

= 0.7 V, V

= 1.2 V

(IREF)

= 600 W

OL(C2)

(IREF)

OUT0 to OUT15 (V

= 15 V)

0.1

µA

OUTn

XDOWN1, 2 (V

= 15 V)

XDOWNn

Constant output leakage current

OL(K)

DOUTn, DCDOUTn

(V = VCCLOG or GND)

µA

OUTn

CC(LOG) CC(ANA) CC(LED)

Constant output current error

between bit

∆I

OL(C)

= 1 V, R = 600 W

(IREF)

All output bits turn on

Changes in constant output current

depend on supply voltage

= 1 V, R = 600 W,

(IREF)

IREF

I∆

OL(C1)

= 1.2 V

Changes in constant output current

depend on output voltage

= 1 V to 3 V, R

= 600 Ω,

= 1.2 V, 1 bit output turn on

IREF

(IREF)

OL(C2)

TSD detection temperature

WDT detection temperature

Voltage reference

Junction temperature

No external capacitor

150

160

170

°C

(tsd)

(wdt)

BCENA = L, R

(IREF)

= 9.6 kΩ,

1.2

(IREF)

Voltage applied to LED

disconnection detection

0.2

0.3

0.4

(LEDDET)

= 22 kΩ, R

= 0.1 µF

= 30 kΩ,

(PD)

(BIAS)

(VCO)

PLL jitter

0.4%

(LLJITTER)

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switching characteristics, C = 15 pF, MIN/MAX: V

= V

= 4.5 V to 5.5 V, T

CC(LOG)

CC(ANA)

CC(LED)

= −20 to 85°C, TYP: V

= V

= 5 V, T = 25°C (unless otherwise noted)

CC(LOG)

CC(ANA) CC(LED)

PARAMETER

TEST CONDITIONS

MIN

TYP

110

130

MAX

UNIT

DOUTn, DCDOUTn

XGSOUT, BOUT, XPOUT

OUTn (see Figure 1)

DOUTn, DCDOUTn

Rise time

Fall time

XGSOUT, BOUT, XPOUT

OUTn (see Figure 1)

OUTn+1 − OUTn

BLANK↑ − OUT0

BLANK − BOUT

GSCLK − OUT0 (see Note 2)

GSCLK − XGSOUT

DCLK − DOUTn

Propagation delay time

DCLK − DCDOUTn

DCCLK − DCDOUTn

XOE↓ − DOUTn (see Note 3)

XOE↑ − DOUTn (see Note 3)

RSEL − DOUTn

LEDCHK − XDOWN2

1000

NOTES: 2. MAG0 to MAG2 are all low level.

3. Until DOUT is turned on (drive) or turned off (Hi-Z).

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PARAMETER MEASUREMENT INFORMATION

51 Ω

IREF

OUTn

GND

600 Ω

15 pF

Figure 1. Rise Time and Fall Time Test Circuit for OUTn

or V

100%

90%

10%

50%

or V

100%

50%

w(l)

w(h)

Figure 2. Timing Requirements

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PRINCIPLES OF OPERATION

setting for output constant current value

On the constant current output terminals (OUT0−15), approximately 38 times the current which flows through

the external resistor, R (connected between IREF and GND), can flow. The external resistor value is

(IREF)

calculated using the following equation:

(Ω) ≅ 38 × 1.2 (V) / I (A) where both BCENA and DCENA are low.

(IREF)

OL(C)

Note that more current flows if IREF is connected to GND directly.

constant output current operation

The constant current output turns on (sink constant current), if GSPOL is high and if all the gray scale data

latched into the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge

of the gray scale clock when BLANK goes from high to low. After that, the number of the falling edge is counted

by the 10-bit gray scale counter. Then, the output counted corresponding to the gray scale data is turned off

(stop to sink constant current). The gray scale clock can be selected, as discussed in later section, from GSCLK

or by internal PLL circuitry. If the shift register for the gray scale is updated during XLATCH high, the data on

the gray scale data latch is also updated affecting the number of the gray scale of constant current output.

Accordingly, during the on-state of the constant current output, XLATCH should be kept at a low level and the

gray scale data latch should be held.

input/output port and shift register selection

The TLC5911 supplies two parallel input ports such as DIN (10 bits : port A) and DCDIN (7 bits: port B). The

DIN and DCDIN ports also supply DCLK and DCCLK for the shift clock, XLATCH and XDCLAT for latch, and

DOUT and DCDOUT for output, respectively. The device has three kinds of shift register latchs such as the gray

scale data, brightness control, and dot correction. The port and shift registers can be selected by RSEL0 and

RSEL1. The selection of the shift registers will be done by RESL0 and RSEL1 as shown in Table 1. Note that

the RSELn setting is done at DCLK low and DPOL high (DCLK is high when DPOL is low). When only port A

is used, DCDIN, DCDOUT, DCCLK, and XDCLAT should be connected to GND.

Table 1. Shift Register Latch Selection

SELECTED SHIFT REGISTER LATCH

PORT A

PORT B

DCDIN, DCCLK, XDCLAT

Dot correction

RSEL1

RSEL0

DIN, DCLK, XLATCH, DOUT

Gray scale data displayed

Brightness control

DCDOUT

Dot correction

N/A (inhibit)

Dot correction

Dot correction (see Note 4)

N/A (inhibit)

Not connected

N/A (inhibit)

NOTE 4: Zero is output to DOUT7 through DOUT9.

shift register latch for gray scale data

The shift register latch for the gray scale data is configured with 16 × 10 bits. The gray scale data, configured

with 10 bits, represents the time when constant current output is being turned on, and the data range is 0 to 1023

(00h to 3FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on (light off). On

the other hand, when the gray scale data is 1023, the time is longest, and it turns on during the time of the 1023

clocks from the gray scale clock. The configuration of the shift register and the latch for gray scale data is shown

in Figure 3.

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PRINCIPLES OF OPERATION

Latch for Gray Scale Data

OUT15

Data

OUT14

OUT1

Data

OUT0

Data

XLATCH

(10 bits)

Shift Register for Gray Scale Data

16th byte

DIN9 MSB

DIN0 LSB

15th byte

DIN9 MSB

DIN0 LSB

2nd byte

DIN9 MSB

DIN0 LSB

1st byte

DIN9 MSB

DIN0 LSB

DCLK

DOUT0 to 9

DIN0 to 9

Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data

shift register latch for brightness control

The shift register latch for brightness control is configured with 1 × 10 bits. Using the shift register latch for the

brightness control, the division ratio of the gray scale clock can be set and the output current value on constant

current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not

initialized. When these functions are used, data should be written to the shift register latch prior to lighting-on

(BLANK=L). Also, it is prohibited from rewriting the latch value for the brightness control when the constant

current output is turned on. When these functions are not used, the latch value can be set to the default value

setting of BCENA at low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current

control to maintain compatibility with the TLC5901/02/03 family. The configuration of the shift register and the

latch for brightness control is shown in Figure 4.

Latch for Brightness Control

Gray Scale Clock Division Ratio Data Set

Current Data Adjusted On Constant Current Output

XLATCH

(see Note A)

MSB

LSB

MSB

LSB

Shift Register for Brightness Control

DCLK

DIN8

DIN7

DIN6

DIN5

DIN4

DIN3

DIN2

DIN1

DIN0

DIN9

DOUT0 to 9

DATA

DIN0 to 9

NOTE A: Indicates default value at BCENA low.

Figure 4. Relationship Between Shift Register and Latch for Brightness Control

shift register latch for dot correction

The shift register latch for dot correction is configured with 16 × 7 bits. Using the shift register latch for dot

correction, the current value on the constant current output can be set individually. When powered up, the latch

data is indeterminate and the shift register is not initialized. When these functions are used, data should be

written to the shift register latch prior to lighting-on (BLANK=L). Also, rewriting the latch value for dot correction

when the constant current output is turned on is inhibited. When these functions are not used, the latch value

can be set to the default value setting of DCENA at low level (connect to GND). The configuration of the shift

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PRINCIPLES OF OPERATION

Latch for Dot Correction

OUT15

Data

OUT14

Data

OUT1

OUT0

Data

XDCLAT

(7 bits)

Shift Register for Dot Correction

16th byte

15th byte

2nd byte

1st byte

DCCLK

DCDIN6 MSB

DCDIN0 LSB

DCDIN6 MSB

DCDIN0 LSB

DCDIN6 MSB

DCDIN0 LSB

DCDIN6 MSB

DCDIN0 LSB

DCDOUT0 to 6

DCDIN0 to 6

Using Port B (RSEL0=L or H, RSEL1=L)

Latch for Dot Correction

OUT15

Data

OUT14

Data

OUT1

Data

OUT0

Data

XLATCH

(7 bits)

Shift Register for Dot Correction

16th byte

DIN6 MSB

DIN0 LSB

15th byte

DIN6 MSB

DIN0 LSB

2nd byte

DIN6 MSB

DIN0 LSB

1st byte

DIN6 MSB

DIN0 LSB

DCLK

DOUT0 to 6

DIN0 to 6

Using Port A (RSEL0=L, RSEL1=H)

Figure 5. Relationship Between the Shift Register and the Latch for Dot Correction

write data to shift register latch

The shift register latch written is selected using the RSEL0 and RSEL1 terminal. At port A, the data is applied

to the DIN data input terminal, clocked into the shift register and synchronized to the rising edge of DCLK after

XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal, clocked into the shift

with 16 × 10 bits and the shift register for dot correction is configured with 16 × 7 bits resulting in sixteen times

DCLK. The shift register for the brightness control is configured with 1 × 10 bits resulting in one times DCLK.

At the number of DCLK input for each case, data can be written into the shift register. In this condition, when

the XLATCH at port A or the XDCLAT at port B is pulled high, data in the shift register is clocked into the latch

(data through). When the XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).

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SLLS402 − DECEMBER 1999

PRINCIPLES OF OPERATION

brightness control function

By writing data into the brightness control latch, current on all the constant current outputs can be adjusted to

control the variation of brightness between ICs. The division ratio for the gray scale clock can be set to control

the variation of brightness for the total panel system. Furthermore, by writing data into the dot correction latch,

current on each constant current output can be adjusted.

output current adjustment on all constant current outputs − brightness adjustment between ICs

By using the lower 6 bits of the brightness control latch, output current can be adjusted in 64 steps as 1 step

of 0.8% of the current ratio between 100% and 50.8% when the output current is set to 100% of an external

resistor (note that the current value is lower if the constant current output is corrected using the dot correction

function). By using this function, the brightness control between modules (ICs) can be adjusted sending the

desired data externally even if ICs are mounted on a print-circuit board. When BCENA is pulled low, the output

current is set to 100%.

Table 2. Relative Current Ratio For Total Constant Current Output

CURRENT RATIO

IREF

(TYP)

20 (mA)

80 (mA)

CODE

50.8

10.2

40.6

MSB 000000 LSB

0.60

99.2

100

19.8

20.0

79.7

80.0

111110

1.19

1.20

†

111111

†

BCENA is low.

frequency division ratio setting for gray scale clock − panel brightness adjustment

By using the upper 4 bits of the brightness control latch, the gray scale clock can be divided into 1/1 to 1/16.

If the gray scale clock is set to 16 times the speed of frequency (1024×16=16384) during horizontal scanning

time, the brightness can be adjusted in 16 steps by selecting the frequency division ratio. By using this function,

the total panel brightness can be adjusted at once, and applied to the brightness of day or night. When BCENA

is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted

as shown in Table 3.

Table 3. Relative Brightness Ratio For Total Constant Current Output

RELATIVE

BRIGHTNESS RATIO

(%)

FREQUENCY DIVISION

CODE

RATIO

†

MSB 0000 LSB

1/1

6.3

1110

1111

1/15

1/16

93.8

100

†

BCENA is low.

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SLLS402 − DECEMBER 1999

PRINCIPLES OF OPERATION

output current adjustment on each constant current output − LED brightness adjustment

By using the dot correction latch, the output current on each constant current output can be adjusted in 128 steps

as 1 step of 0.8% of the current ratio between 100% and 0% when the output current is set to 100% of an external

resistor at 7Fh of the latched value and the lower 6 bits of the brightness control register. By using this function,

the brightness deviation from the LED brightness variation can be minimized. When DCENA is pulled low, the

output current is set to 100% without the dot correction.

Table 4. Relative Current Ratio By Constant Current Output

CODE

CURRENT RATIO %

=40 (mA)

OL(C)

MSB 0000000 LSB

0.0

1111110

99.2

100

39.7

†

1111111

DCENA is low.

†

clock edge selection

The high speed clock signal is diminished due to the duty ratio change through the multiple stages of the IC or

module as shown in Figure 6.

OUT

A’

OUT

OUT’

IN’

A’

OUT

a) Propagate through multiple stages buffer

with slow falling edge

b) Insert inverter between buffers

Figure 6. Clock Edge Selection

In Figure 6a, if the falling edge at the internal buffer is behind the rising edge, the clock will disappear if a multiple

cascade connection is made. To resolve this problem, the duty ratio can be held unchanged using the

connection as shown in Figure 6b if the valid clock edge can be selected (arrow in Figure 6). Note that the clock

delay is not avoided even in this case.

The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,

the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL,

thus the degradation for the duty ratio can be reduced. The relationship between each signal is shown in Table 5.

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PRINCIPLES OF OPERATION

Table 5. Valid Edge For DCLK and GSCLK

DPOL

DCLK valid edge

DCLK↑

Operation at XENABLE = H

Pull DCLK to low level

Pull DCLK to high level

DCLK↓

GSPOL

GSCLK valid edge

GSCLK↑

PLL operation

Synchronize to the high level of DCLK

Synchronize to the low level of DCLK

GSCLK↓

The device supplies the XPOUT and XGSOUT output terminals for the cascade operation which inverts GSPOL

and GSCLK respectively. It also supplies the BOUT output terminal as a buffered BLANK to make timing easy

with GSCLK and XGSOUT.

gray scale clock generation

When MAG<0:2> are all low, the clock input from the GSCLK terminal is used as the gray scale clock with no

change, and except for this case the internal PLL generates the clock for the gray scale control clock. When

using the PLL, the gray scale clock is generated by adjusting the clock to have the same number of pulses as

the multiple ratio of the GSCLK reference period (when GSCLK and GSPOL are kept at the same level). The

ratio in this case is determined depending on MAG0 through MAG2 as shown in Table 6.

When using the PLL, the internal PLLCLK is clocked out at the XGSOUT terminal. Therefore, the clock can be

utilized for other devices on the same print-circuit board. Note that the number of ICs connected is limited

depending on the frequency.

Table 6. PLL Multiple Ratio

MAG2

MAG1

MAG0

MULTIPLE RATIO

XGSOUT

1 (Signal to control GSCLK by GSPOL)

Inverted GSCLK

2 +6(=262)

2 +10(=522)

+18(=1042)

+34(=2082)

+66(=4162)

+130(=8322)

+258(=16642)

PLLCLK

(Gray scale clock is internally generated)

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PRINCIPLES OF OPERATION

gray scale clock generation (continued)

MAG<2:0>

GSPOL

Except all low level

GSCLK

XGSOUT

PLLCLK

Same number of pulse as ratio

a) GSPOL is low

Same number of pulse as ratio

a) GSPOL is high

Figure 7. Gray Scale Clock Generation

The oscillation frequency bandwidth as referenced for the PLL can be set by an external resistor connected

between RBIAS and GND. The relation between the external resistor and the oscillation frequency is shown

in Table 7.

Table 7. PLL Oscillation Frequency

RBIAS

22 kΩ

30 kΩ

62 kΩ

12 0kΩ

FREQUENCY

13 to 16 MHz

8 to 14 MHz

4 to 9 MHz

3 to 5 MHz

Note that it takes 30 ms for the PLL to be stabilized. Furthermore, to make the PLL operation stabilized, a resistor

and a capacitor connection is required between VCOIN, PDOUT and GND. The recommended values are

shown in the Figure 8.

PDOUT

VCOIN

pd)

VCO)

Recommeded Value

0.1 to 1 µF 22 to 62 kΩ

(pd)

VCO)

Figure 8. Resistor and Capacitor Connection

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PRINCIPLES OF OPERATION

protection

This device incorporates WDT and TSD functions. If the WDT or TSD functions, the constant current output is

stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be

detected immediately. Since the XDOWN1 output is configured as open collector, outputs of multiple ICs are

brought together.

WDT (watchdog timer)

The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the

signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (a signal to the control

line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned

off preventing the LED from burning and damage caused by continuous LED turn on at the dynamic scanning

operation. The detection time can be set using an external capacitor, C1. The typical value is approximately 10

ms without capacitor, 160 ms with a1000 pF capacitor, and 1500 ms with a 0.01 µF capacitor. During static

operation, the WDT function is disabled connecting the WDCAP to GND (high or low level should be applied

to WDTRG). Note that normal operations will be resumed changing the WDTRG level when WDT functions.

WDT operational time T (ms) ≅ 10 + 0.15 x C1 (pF)

Time (ms)

1500

TLC5911

Scan Signal

WDTRG

WDCAP

160

0.001

0.01

C1 − External Capacitor − µF

Figure 9. WDT Operational Time and Usage Example

TSD (thermal shutdown)

When the junction temperature exceeds the limit, TSD functions and turns the constant current output off, and

XDOWN1 goes low. When TSD is used, TSENA is pulled high. When TSD is not used, TSENA is pulled low.

To recover from the constant current output off-state to normal operations, the power supply should be turned

off or TSENA should be pulled low once.

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SLLS402 − DECEMBER 1999

PRINCIPLES OF OPERATION

LOD function (LED open detection)

When LEDCHK is low, the LED disconnection detection function is disabled and XDOWN2 goes to a

high-impedance state. When LEDCHK is high, the LED disconnection detection function is enabled, and

XDOWN2 goes low if any LED is disconnected while monitoring the OUTn terminals to be turned on. This

function is operational for sixteen OUTn terminals individually. To determine which constant current output is

disconnected, the level of XDOWN2 is checked 16 times from OUT0 to OUT15 turning one constant current

output on. The power supply voltage should be set so the constant current output applied is above 0.4 V when

the LED is turned on normally. Also, since approximately 1000 ns is required from turning the constant current

output on to XDOWN2 output, the gray scale data to be turned on during that period should be applied.

Table 8 is an example of XDOWN2 output status using four LEDs .

Table 8. XDOWN2 Output Example

LED NUMBER

LED STATUS

OUTn

GOOD

DETECTION RESULT

XDOWN2

GOOD

LOW (by case 2, 4)

LED NUMBER

LED STATUS

OUTn

GOOD

OFF

GOOD

DETECTION RESULT

XDOWN2

GOOD

LOW (by case 2)

LED NUMBER

LED STATUS

OUTn

GOOD

OFF

GOOD

OFF

GOOD

OFF

GOOD

DETECTION RESULT

XDOWN2

GOOD

HIGH-IMPEDANCE

noise reduction

concurrent switching noise reduction

Concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time. To

prevent this noise, the device has delay output terminals such as XGSOUT, BOUT for GSCLK (gray scale clock),

and BLANK (blanking signal) respectively. By connecting these outputs to the GSCLK and BLANK terminals

of next stage IC, it allows differences in the switching time between ICs. When GSCLK is output to GSOUT

through the device, duty will be changed between input and output. The number of stages to be connected will

be limited depending on the frequency.

delay between constant current output

The constant current output has a delay time of approximately 20 ns between outputs. It means approximately

300 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for the reduction

of concurrent switching noise.

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PRINCIPLES OF OPERATION

others

power supply

The following should be taken into consideration:

VCCLOG, VCCANA and VCCLED should be supplied by a single power supply to minimize voltage

differences between these terminals.

The bypass capacitor should be located between the power supply and GND to eliminate the variation of

power supply voltage.

GND

Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally

connected to reduce noise influence.

thermal pad

The thermal pad should be connected to GND to eliminate the noise influence, since it is connected to the bottom

side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with

better thermal conductivity.

power rating free-air temperature

3.2

4.7

2.3

1.48

−20

− Free-Air Temperature − °C

NOTES: A. The IC is mounted on PCB.

PCB size : 102 × 76 × 1.6 [mm ], four layers with the internal two layers being plane. The thermal pad is soldered to the PCB

pattern of 10 × 10 [mm ]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.

=5 V, I

= 80 mA, I is a typical value.

CC(LOG) CC(ANA) CC(LED)

OL(C)

B. The thermal impedance will be varied depending on the mounting conditions. Since the PZP package established a low

thermal impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with a low thermal

impedance.

C. The material for the PCB should be selected considering the thermal characteristics since the temperature will rise around

the thermal pad.

Figure 10. Power Rating

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PRINCIPLES OF OPERATION

0.1

1.0

10.0

(kΩ)

(IREF)

Conditions : V = 1 V, V

= 1.2 V

(IREF)

(V)

(kW)

(IREF)

(mA) ^

OL(C)

(IREF)

(kW) ^

(IREF)

(mA)

OL(C)

NOTE: The brightness control and dot corrected value are set at 100%.

The resistor, R , should be located as close as possible to the IREF terminal to avoid noise influence.

(IREF)

Figure 11. Current on Constant Current Output vs External Resistor

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Template Release Date: 7−11−94

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ꢁ ꢆ ꢇ ꢧꢇ ꢈ ꢉ ꢊꢆ ꢈ

SLLS402 − DECEMBER 1999

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅꢅ

ꢁ ꢆ ꢇꢧ ꢇꢈ ꢉ ꢊꢆ ꢈ

SLLS402 − DECEMBER 1999

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Template Release Date: 7−11−94

ꢀ ꢁ ꢂꢃ ꢄ ꢅꢅ

ꢁ ꢆ ꢇ ꢧꢇ ꢈ ꢉ ꢊꢆ ꢈ

SLLS402 − DECEMBER 1999

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅꢅ

ꢁ ꢆ ꢇꢧ ꢇꢈ ꢉ ꢊꢆ ꢈ

SLLS402 − DECEMBER 1999

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Template Release Date: 7−11−94

ꢀ ꢁ ꢂꢃ ꢄ ꢅꢅ

ꢁ ꢆ ꢇ ꢧꢇ ꢈ ꢉ ꢊꢆ ꢈ

SLLS402 − DECEMBER 1999

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

TLC5911PZP

ACTIVE

HTQFP

PZP

100

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-3-260C-168 HR

-20 to 85

TLC5911

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Applications

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www.ti.com/audio

amplifier.ti.com

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www.dlp.com

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DLP® Products

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www.ti.com/energy

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Interface

www.ti.com/clocks

interface.ti.com

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www.ti.com/industrial

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power.ti.com

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TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TLC5911PZPG4 [TI]

相关型号：

TLC5916

TLC5916-Q1

TLC5916I

TLC5916ID

TLC5916IDG4

TLC5916IDR

TLC5916IDRG4

TLC5916IN

TLC5916INE4

TLC5916IPW

TLC5916IPWG4

TLC5916IPWR