TLC5916IPWRG4 [TI]
8-BIT CONSTANT-CURRENT LED SINK DRIVERS; 8位恒流LED灌电流驱动器
| 型号： | TLC5916IPWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT CONSTANT-CURRENT LED SINK DRIVERS |
| 文件： | 总30页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
1
FEATURES
•
Eight Constant-Current Output Channels
•
•
•
•
30-MHz Clock Frequency
Schmitt-Trigger Input
•
•
•
•
Output Current Adjusted Through External
Resistor
3.3-V or 5-V Supply Voltage
Constant Output Current Range:
5 mA to 120 mA
Thermal Shutdown for Overtemperature
Protection
Constant Output Current Invariant to Load
Voltage Change
APPLICATIONS
•
•
•
•
•
•
General LED Lighting Applications
LED Display Systems
LED Signage
Automotive LED Lighting
White Goods
Open Load, Short Load and Overtemperature
Detection
•
•
256-Step Programmable Global Current Gain
Excellent Output Current Accuracy:
–
–
Between Channels: < ±3% (Max)
Between ICs: < ±6% (Max)
Gaming Machines/Entertainment
•
Fast Response of Output Current
DESCRIPTION/ORDERING INFORMATION
The TLC5916/TLC5917 is designed for LED displays and LED lighting applications with constant-current control
and open-load, shorted-load, and overtemperature detection. The TLC5916/TLC5917 contains an 8-bit shift
register and data latches, which convert serial input data into parallel output format. At the output stage, eight
regulated current ports are designed to provide uniform and constant current for driving LEDs within a wide range
of VF variations. Used in system design for LED display applications, e.g., LED panels, it provides great flexibility
and device performance. Users can adjust the output current from 5 mA to 120 mA through an external resistor,
Rext, which gives flexibility in controlling the light intensity of LEDs. The devices are designed for up to 17 V at
the output port. The high clock frequency, 30 MHz, also satisfies the system requirements of high-volume data
transmission.
The TLC5916/TLC5917 provides a Special Mode in which two functions are included, Error Detection and
Current Gain Control. There are two operation modes and three phases: Normal Mode phase, Mode Switching
transition phase, and Special Mode phase. The signal on the multiple function pin OE(ED2) is monitored to
determine the mode. When an one-clock-wide pulse appears on OE(ED2), the device enters the Mode Switching
phase. At this time, the voltage level on LE(ED1) determines the mode to which the TLC5916/TLC5917 switches.
In the Normal Mode phase, the serial data can be transferred into TLC5916/TLC5917 via the pin SDI, shifted in
the shift register, and transferred out via the pin SDO. LE(ED1) can latch the serial data in the shift register to the
output latch. OE(ED2) enables the output drivers to sink current.
In the Special Mode phase, the low-voltage-level signal OE(ED2) can enable output channels and detect the
status of the output current, to determine if the driving current level is sufficient. The detected Error Status is
loaded into the 8-bit shift register and shifted out via the pin SDO, synchronous to the CLK signal. The system
controller can read the error status and determine whether or not the LEDs are properly lit.
In the Special Mode phase, the TLC5916/TLC5917 allows users to adjust the output current level by setting a
runtime-programmable Configuration Code. The code is sent into the TLC5916/TLC5917 via SDI. The positive
pulse of LE(ED1) latches the code in the shift register into a built-in 8-bit configuration latch, instead of the output
latch. The code affects the voltage at the terminal R-EXT and controls the output-current regulator. The output
current can be finely adjusted by a gain ranging from 1/12 to 127/128 in 256 steps. Therefore, the current skew
between ICs can be compensated within less than 1%. This feature is suitable for white balancing in LED color
display panels.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SHORT TO VLED
DETECTION
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP – N
SOIC – D
Tube of 25
TLC5916IN
TLC5916IN
Tube of 40
Reel of 2500
Tube of 90
Reel of 2000
Tube of 25
Tube of 40
Reel of 2500
Tube of 90
Reel of 2000
TLC5916ID
TLC5916I
No
TLC5916IDR
TLC5916IPW
TLC5916IPWR
TLC5917IN
TSSOP – PW
PDIP – N
Y5916
–40°C to 125°C
TLC5917IN
TLC5917I
TLC5917ID
SOIC – D
Yes
TLC5917IDR
TLC5917IPW
TLC5917IPWR
TSSOP – PW
Y5917
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
BLOCK DIAGRAM
OUT0
OUT1
OUT6 OUT7
I/O Regulator
R-EXT
8
Output Driver and
Error Detection
OE(ED2)
LE(ED1)
Control
Logic
8
8
VDD
8-Bit Output
Latch
Configuration
Latches
8
CLK
SDI
8
8-Bit Shift
Register
SDO
8
2
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
D, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
GND
SDI
16 VDD
15
14
13
12
11
10
9
R-EXT
SDO
CLK
LE(ED1)
OUT0
OUT1
OUT2
OUT3
OE(ED2)
OUT7
OUT6
OUT5
OUT4
Terminal Descriptions
TERMINAL
NAME
DESCRIPTION
CLK
Clock input for data shift on rising edge
GND
Ground for control logic and current sink
Data strobe input
Serial data is transferred to the respective latch when LE(ED1) is high. The data is latched when LE(ED1) goes low.
Also, a control signal input for an Error Detection Mode and Current Adjust Mode (see Timing Diagram). LE(ED1) has
an internal pulldown.
LE(ED1)
Output enable. When OE(ED2) is active (low), the output drivers are enabled; when OE(ED2) is high, all output drivers
are turned OFF (blanked). Also, a control signal input for an Error Detection Mode and Current Adjust Mode (see
Figure 1). OE(ED2) has an internal pullup.
OE(ED2)
OUT0–OUT7
R-EXT
SDI
Constant-current outputs
Input used to connect an external resistor for setting up all output currents
Serial-data input to the Shift register
SDO
Serial-data output to the following SDI of next driver IC or to the microcontroller
Supply voltage
VDD
Diagnostic Features
OVERTEMPERATURE
DETECTION
OPEN-LOAD
DETECTION
SHORT TO GND
DETECTION
SHORT TO VLED
DETECTION
DEVICE(1)
TLC5916
TLC5917
X
X
X
X
X
X
X
(1) The device has one single error register for all these conditions (one error bit per channel).
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
Timing Diagram
0
1
2
3
4
5
6
7
CLK
1
0
OE(ED2)
LE(ED1)
SDI
off
on
off
on
off
on
off
on
OUT0
OUT1
OUT2
OUT3
off
on
OUT7
SDO
Don't care
Figure 1. Normal Mode
Truth Table in Normal Mode
CLK
LE(ED1)
OE(ED2)
SDI
OUT0...OUT7
SDO
↑
↑
↑
↓
↓
H
L
L
L
L
L
H
Dn
Dn...Dn – 7
No change
Dn + 2...Dn – 5
Dn + 2...Dn – 5
Off
Dn – 7
Dn – 6
Dn – 5
Dn – 5
Dn – 5
Dn + 1
Dn + 2
Dn + 3
Dn + 3
H
X
X
The signal sequence shown in Figure 2 makes the TLC5916/TLC5917 enter Current Adjust and Error Detection
Mode.
1
2
3
4
5
CLK
OE(ED2)
LE(ED1)
1
0
0
0
1
0
1
1
1
0
Figure 2. Switching to Special Mode
4
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
In the Current Adjust Mode, sending the positive pulse of LE(ED1), the content of the shift register (a current
adjust code) is written to the 8-bit configuration latch (see Figure 3).
6
0
1
2
3
7
CLK
1
0
OE(ED2)
LE(ED1)
SDI
8-bit Configuration Code
Figure 3. Writing Configuration Code
When the TLC5916/TLC5917 is in the Error Detection Mode, the signal sequence shown in Figure 4 enables a
system controller to read error status codes through SDO.
1
2
3
CLK
>2 µs
1
0
OE(ED2)
LE(ED1)
SDO
Error Status Code
Figure 4. Reading Error Status Code
The signal sequence shown in Figure 5 makes TLC5916/TLC5917 resume the Normal Mode. Switching to
Normal Mode resets all internal Error Status registers. OE(ED2) always enables the output port, whether the
TLC5916/TLC5917 enters Current Adjust Mode or not.
1
2
3
4
5
CLK
OE(ED2)
LE(ED1)
1
0
0
0
1
0
1
0
1
0
Figure 5. Switching to Normal Mode
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
0
MAX
UNIT
VDD
VI
Supply voltage range
7
V
Input voltage range
–0.4
–0.5
VDD + 0.4
20
V
V
VO
Output voltage range
fclk
Clock frequency
25
MHz
mA
mA
°C
IOUT
IGND
TA
Output current
120
960
125
150
150
1.5
GND terminal current
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
Electrostatic discharge capability, V(HBMESD)
–40
–40
–55
TJ
°C
Tstg
ESD
°C
100 pF, 1.5 kΩ
kV
Power Dissipation and Thermal Impedance
MIN
MAX
1.5
1
UNIT
D package
N package
PW package
D package
N package
PW package
D package
N package
PW package
Mounted on JEDEC 4-layer board (JESD 51-7),
No airflow, TA = 25°C, TJ = 125°C
PD
Power dissipation
W
0.9
103
148
176
66
Mounted on JEDEC 1-layer board (JESD 51-3),
No airflow
Thermal impedance,
junction to free air
θJA
°C/W
Mounted on JEDEC 4-layer board (JESD 51-7),
No airflow
97
112
6
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Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
Recommended Operating Conditions
CONDITIONS
MIN
MAX
5.5
UNIT
V
VDD
VO
Supply voltage
3
Supply voltage to output pins
OUT0–OUT7
DC test circuit
17
V
V
O ≥ 0.6 V
O ≥ 1 V
5
IO
Output current
mA
V
120
IOH
IOL
VIH
VIL
High-level output current source
Low-level output current sink
High-level input voltage
SDO shorted to GND
SDO shorted to VCC
–1
mA
mA
V
1
0.7 × VDD
0
CLK, OE(ED2), LE(ED1), and SDI
CLK, OE(ED2), LE(ED1), and SDI
VDD
Low-level input voltage
0.3 × VDD
V
Recommended Timing
VDD = 3 V to 5.5 V (unless otherwise noted)
CONDITIONS
MIN
MAX
UNIT
ns
tw(L)
LE(ED1) pulse duration
CLK pulse duration
Normal Mode
20
20
500
700
3
tw(CLK)
Normal Mode
ns
Normal Mode, IOUT < 60 mA
Normal Mode, IOUT > 60 mA
Normal Mode
tw(OE)
OE(ED2) pulse duration
ns
tsu(D)
Setup time for SDI
ns
ns
th(D)
Hold time for SDI
Normal Mode
2
tsu(L)
Setup time for LE(ED1)
Hold time for LE(ED1)
CLK pulse duration
Normal Mode
15
15
20
2000
4
ns
th(L)
Normal Mode
ns
tw(CLK)
tw(ED2)
tsu(ED1)
th(ED1)
tsu(ED2)
th(ED2)
fCLK
Error Detection Mode
Error Detection Mode
Error Detection Mode
Error Detection Mode
Error Detection Mode
Error Detection Mode
Cascade operation
ns
OE(ED2) pulse duration
Setup time for LE(ED1)
Hold time for LE(ED1)
Setup time for OE(ED2)
Hold time for OE(ED2)
Clock frequency
ns
ns
10
6
ns
ns
10
ns
30
MHz
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
Electrical Characteristics
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
VDD
VO
3
5.5
17
V
V
Supply voltage to the output pins
V
O ≥ 0.6 V
O ≥ 1 V
5
IO
Output current
mA
V
120
IOH
IOL
VIH
VIL
High-level output current, source
Low-level output current, sink
High-level input voltage
–1
1
mA
mA
V
0.7 × VDD
GND
VDD
0.3 × VDD
0.5
Low-level input voltage
V
TJ = 25°C
Ileak
Output leakage current
VOH = 17 V
µA
TJ = 125°C
2
VOH
VOL
High-level output voltage
Low-level output voltage
SDO, IOL = –1 mA
SDO, IOH = 1 mA
VDD – 0.4
V
V
0.4
VOUT = 0.6 V, Rext = 720 Ω,
CG = 0.992
Output current 1
26
±3
mA
%
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
IO(1)
Output current error, die-die
±6
±3
Output current skew,
channel-to-channel
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
±1.5
52
%
mA
%
Output current 2
VO = 0.8 V, Rext = 360 Ω, CG = 0.992
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
Output current error, die-die
±2
±6
±3
IO(2)
Output current skew,
channel-to-channel
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
±1.5
±0.1
±1
%
VO = 1 V to 3 V, IO = 26 mA
IOUT vs
VOUT
Output current vs
output voltage regulation
%/V
VDD = 3.0 V to 5.5 V,
IO = 26 mA/120 mA
Pullup resistance
OE(ED2)
LE(ED1)
500
500
175
15
kΩ
kΩ
°C
°C
Pulldown resistance
Overtemperature shutdown(2)
Tsd
150
200
Thys
Restart temperature hysteresis
Threshold current for open error
detection
IOUT,Th1
IOUT,Th2
IOUT,Th3
IOUT,Th
IOUT,target = 26 mA
0.5 × Itarget
0.5 × Itarget
0.5 × Itarget
0.5 × Itarget
%
%
%
%
Threshold current for open error
detection
IOUT,target = 52 mA
Threshold current for open error
detection
IOUT,target = 104 mA
IOUT,target = 5 mA to 120 mA
Threshold current for open error
detection
Trigger threshold voltage for
short-error detection
(TLC5917 only)
VOUT,TTh
IOUT,target = 5 mA to 120 mA
IOUT,target = 5 mA to 120 mA
2.5
2.2
2.7
3.1
V
V
Return threshold voltage for
short-error detection
(TLC5917 only)
VOUT,RTh
Rext = Open
Rext = 720 Ω
Rext = 360 Ω
Rext = 180 Ω
5
8
10
14
18
22
IDD
Supply current
mA
11
16
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) Specified by design.
8
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Product Folder Link(s): TLC5916 TLC5917
TLC5916, TLC5917
8-BIT CONSTANT-CURRENT LED SINK DRIVERS
www.ti.com
SLVS695A–JUNE 2007–REVISED MARCH 2008
Electrical Characteristics
VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
VDD
VO
3
5.5
17
V
V
Supply voltage to the output pins
V
O ≥ 0.6 V
O ≥ 1 V
5
IO
Output current
mA
V
120
IOH
IOL
VIH
VIL
High-level output current, source
Low-level output current, sink
High-level input voltage
–1
1
mA
mA
V
0.7 × VDD
GND
VDD
0.3 × VDD
0.5
Low-level input voltage
V
TJ = 25°C
Ileak
Output leakage current
VOH = 17 V
µA
TJ = 125°C
2
VOH
VOL
High-level output voltage
Low-level output voltage
SDO, IOL = –1 mA
SDO, IOH = 1 mA
VDD – 0.4
V
V
0.4
VOUT = 0.6 V, Rext = 720 Ω,
CG = 0.992
Output current 1
26
±3
mA
%
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
IO(1)
Output current error, die-die
±6
±3
Output current skew,
channel-to-channel
IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω,
TJ = 25°C
±1.5
52
%
mA
%
Output current 2
VO = 0.8 V, Rext = 360 Ω, CG = 0.992
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
Output current error, die-die
±2
±6
±3
IO(2)
Output current skew,
channel-to-channel
IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω,
TJ = 25°C
±1.5
±0.1
±1
%
VO = 1 V to 3 V , IO = 26 mA
IOUT vs
VOUT
Output current vs
output voltage regulation
%/V
VDD = 3.0 V to 5.5 V,
IO = 26 mA/120 mA
Pullup resistance
OE(ED2),
LE(ED1),
500
500
175
15
kΩ
kΩ
°C
°C
Pulldown resistance
Overtemperature shutdown(2)
Tsd
150
200
Thys
Restart temperature hysteresis
Threshold current for open error
detection
IOUT,Th1
IOUT,Th2
IOUT,Th3
IOUT,Th
IOUT,target = 26 mA
0.5 × Itarget
0.5 × Itarget
0.5 × Itarget
0.5 × Itarget
%
%
%
%
Threshold current for open error
detection
IOUT,target = 52 mA
Threshold current for open error
detection
IOUT,target = 104 mA
IOUT,target = 5 mA to 120 mA
Threshold current for open error
detection
Trigger threshold voltage for
short-error detection
(TLC5917 only)
VOUT,TTh
IOUT,target = 5 mA to 120 mA
IOUT,target = 5 mA to 120 mA
2.5
2.2
2.7
3.1
V
V
Return threshold voltage for
short-error detection
(TLC5917 only)
VOUT,RTh
Rext = Open
Rext = 720 Ω
Rext = 360 Ω
Rext = 180 Ω
6
11
13
19
10
14
18
24
IDD
Supply current
mA
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) Specified by design.
Copyright © 2007–2008, Texas Instruments Incorporated
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8-BIT CONSTANT-CURRENT LED SINK DRIVERS
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SLVS695A–JUNE 2007–REVISED MARCH 2008
Switching Characteristics
VDD = 3 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
95
UNIT
ns
tPLH1
tPLH2
tPLH3
tPLH4
tPHL1
tPHL2
tPHL3
tPHL4
tw(CLK)
tw(L)
Low-to-high propagation delay time, CLK to OUTn
Low-to-high propagation delay time, LE(ED1) to OUTn
Low-to-high propagation delay time, OE(ED2) to OUTn
Low-to-high propagation delay time, CLK to SDO
High-to-low propagation delay time, CLK to OUTn
High-to-low propagation delay time, LE(ED1) to OUTn
High-to-low propagation delay time, OE(ED2) to OUTn
High-to-low propagation delay time, CLK to SDO
Pulse duration, CLK
40
40
40
12
65
65
95
95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
65
20
30
300
300
300
20
365
365
365
30
12
20
20
500
2
Pulse duration, LE(ED1)
tw(OE)
tw(ED2)
th(ED1,ED2)
th(D)
Pulse duration, OE(ED2)
VIH = VDD, VIL = GND,
Rext = 360 Ω, VL = 4 V,
RL = 44 Ω, CL = 10 pF,
CG = 0.992
Pulse duration, OE(ED2) in Error Detection Mode
Hold time, LE(ED1) and OE(ED2)
Hold time, SDI
10
2
tsu(D,ED1)
tsu(ED2)
th(L)
Setup time, SDI, LE(ED1)
3
Setup time, OE(ED2)
8.5
15
15
Hold time, LE(ED1), Normal Mode
Setup time, LE(ED1), Normal Mode
Rise time, CLK(2)
tsu(L)
tr
500
500
105
100
370
225
30
tf
Fall time, CLK(2)
tor
Rise time, outputs (off)
40
85
83
tor
Rise time, outputs (off), TJ = 25°C
Rise time, outputs (on)
tof
100
280
170
tof
Rise time, outputs (on), TJ = 25°C
Clock frequency
fCLK
Cascade operation
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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Switching Characteristics
VDD = 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
95
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tPLH1
tPLH2
tPLH3
tPLH4
tPHL1
tPHL2
tPHL3
tPHL4
tw(CLK)
tw(L)
Low-to-high propagation delay time, CLK to OUTn
Low-to-high propagation delay time, LE(ED1) to OUTn
Low-to-high propagation delay time, OE(ED2) to OUTn
Low-to-high propagation delay time, CLK to SDO
High-to-low propagation delay time, CLK to OUTn
High-to-low propagation delay time, LE(ED1) to OUTn
High-to-low propagation delay time, OE(ED2) to OUTn
High-to-low propagation delay time, CLK to SDO
Pulse duration, CLK
40
40
40
8
65
65
95
65
95
20
30
300
300
300
20
365
365
365
30
8
20
20
500
2
Pulse duration, LE(ED1)
tw(OE)
tw(ED2)
Pulse duration, OE(ED2)
VIH = VDD, VIL = GND,
Rext = 360 Ω, VL = 4 V,
RL = 44 Ω, CL = 10 pF,
CG = 0.992
Pulse duration, OE(ED2) in Error Detection Mode
th(D,ED1,ED2) Hold time, SDI, LE(ED1), and OE(ED2)
10
2
th(D)
tsu(D,ED1)
tsu(ED2)
th(L)
tsu(L)
tr
Hold time, SDI
Setup time, SDI, LE(ED1)
Setup time, OE(ED2)
3
8.5
15
15
Hold time, LE(ED1), Normal Mode
Setup time, LE(ED1), Normal Mode
Rise time, CLK(2)
500
500
105
100
370
225
30
tf
Fall time, CLK(2)
tor
Rise time, outputs (off)
Rise time, outputs (off), TJ = 25°C
Rise time, outputs (on)
Rise time, outputs (on), TJ = 25°C
Clock frequency
40
85
83
tor
tof
100
280
170
tof
fCLK
Cascade operation
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.
(2) If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two
cascaded devices.
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PARAMETER MEASUREMENT INFORMATION
IDD
VDD
IOUT
OE(ED2)
OUT0
IIH, IIL
CLK
LE(ED1)
OUT7
SDO
SDI
VIH, VIL
R-EXT
GND
Iref
Figure 6. Test Circuit for Electrical Characteristics
IDD
IOUT
VDD
VIH, VIL
OUT0
OUT7
SDO
OE(ED2)
CLK
Function
Generator
LE(ED1)
RL
CL
SDI
R-EXT
GND
Logic Input
Waveform
Iref
VL
CL
VIH = 5 V
VIL = 0V
Figure 7. Test Circuit for Switching Characteristics
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PARAMETER MEASUREMENT INFORMATION (continued)
tw(CLK)
50%
50%
CLK
SDI
50%
50%
tsu(D)
th(D)
50%
50%
tPLH4, tPHL4
50%
SDO
tw(L)
50%
LE(ED1)
tsu(L)
th(L)
OE(ED2)
OUTn
LOW
tPLH2, tPHL2
Output off
Output on
50%
tPLH1, tPHL1
tw(OE)
HIGH
OE(ED2)
50%
50%
tPLH3
tPHL3
Output off
80%
80%
OUTn
50%
50%
20%
20%
tor
tof
Figure 8. Normal Mode Timing Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
tw(CLK)
50%
CLK
tsu(ED2)
th(ED2)
OE(ED2)
50%
tsu(ED1)
th(ED1)
LE(ED1)
50%
2 CLK
Figure 9. Switching to Special Mode Timing Waveforms
50%
CLK
50%
OE(ED2)
tw(ED2)
Figure 10. Reading Error Status Code Timing Waveforms
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TYPICAL CHARACTERISTICS
LE = 5 V (active)
OE = GND (active)
CLK
OUTn
Figure 11. Response Time, CLK to OUTn
Turn on only one channel
Channel 1
OE
OUT1
Figure 12. Response Time, OE to OUT1
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TYPICAL CHARACTERISTICS (continued)
Turn on only one channel
Channel 8
OE
OUT7
Figure 13. Response Time, OE to OUT7
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APPLICATION INFORMATION
Operating Principles
Constant Current
In LED display applications, TLC5916/TLC5917 provides nearly no current variations from channel to channel
and from IC to IC. While IOUT ≤ 100 mA, the maximum current skew between channels is less than ±3% and
between ICs is less than ±6%.
Adjusting Output Current
TLC5916/TLC5917 scales up the reference current, Iref, set by the external resistor Rext to sink a current, Iout, at
each output port. Users can follow the below formulas to calculate the target output current IOUT,target in the
saturation region:
VR-EXT = 1.26 V × VG
Iref = VR-EXT/Rext, if another end of the external resistor Rext is connected to ground
IOUT,target = Iref × 15 × 3CM – 1
Where Rext is the resistance of the external resistor connected to the R-EXT terminal, and VR-EXT is the voltage of
R-EXT, which is controlled by the programmable voltage gain (VG), which is defined by the Configuration Code.
The Current Multiplier (CM) determines that the ratio IOUT,target/Iref is 15 or 5. After power on, the default value of
VG is 127/128 = 0.992, and the default value of CM is 1, so that the ratio IOUT,target/Iref = 15. Based on the default
VG and CM:
VR-EXT = 1.26 V × 127/128 = 1.25 V
IOUT,target = (1.25 V/Rext) × 15
Therefore, the default current is approximately 52 mA at 360 Ω and 26 mA at 720 Ω. The default relationship
after power on between IOUT,target and Rext is shown in Figure 14.
140
120
100
80
40
0
0
500 1000
1500 2000 2500 3000 3500 4000
Rext – Ω
Figure 14. Default Relationship Curve Between IOUT,target and Rext After Power Up
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Operation Phases
Operation Mode Switching
To switch between its two modes, TLC5916/TLC5917 monitors the signal OE(ED2). When an one-clock-wide
pulse of OE(ED2) appears, TLC5916/TLC5917 enters the two-clock-period transition phase, the Mode Switching
phase. After power on, the default operation mode is the Normal Mode (see Figure 15).
Switching to Special Mode
Switching to Normal Mode
1
2
3
4
5
1
2
3
4
5
CLK
OE(ED2)
LE(ED1)
CLK
OE(ED2)
LE(ED1)
1
0
0
1
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0
0
Actual Mode
(Normal or Special)
Mode
Switching
Actual Mode
(Normal or Special)
Mode
Switching
Special
Mode
Normal
Mode
Phase
Phase
Figure 15. Mode Switching
As shown in Figure 15, once a one-clock-wide short pulse (101) of OE(ED2) appears, TLC5916/TLC5917 enters
the Mode Switching phase. At the fourth rising edge of CLK, if LE(ED1) is sampled as voltage high,
TLC5916/TLC5917 switches to Special Mode; otherwise, it switches to Normal Mode. The signal LE(ED1)
between the third and the fifth rising edges of CLK cannot latch any data. Its level is used only to determine into
which mode to switch. However, the short pulse of OE(ED2) can still enable the output ports. During mode
switching, the serial data can still be transferred through SDI and shifted out from SDO.
NOTES:
1. The signal sequence for the mode switching may be used frequently to ensure that TLC5916/TLC5917 is in
the proper mode.
2. The 1 and 0 on the LE(ED1) signal are sampled at the rising edge of CLK. The X means its level does not
affect the result of mode switching mechanism.
3. After power on, the default operation mode is Normal Mode.
Normal Mode Phase
Serial data is transferred into TLC5916/TLC5917 via SDI, shifted in the Shift Register, and output via SDO.
LE(ED1) can latch the serial data in the Shift Register to the Output Latch. OE(ED2) enables the output drivers to
sink current. These functions differ only as described in Operation Mode Switching, in which case, a short pulse
triggers TLC5916/TLC5917 to switch the operation mode. However, as long as LE(ED1) is high in the Mode
Switching phase, TLC5916/TLC5917 remains in the Normal Mode, as if no mode switching occurred.
Special Mode Phase
In the Special Mode, as long as OE(ED2) is not low, the serial data is shifted to the Shift Register via SDI and
shifted out via SDO, as in the Normal Mode. However, there are two differences between the Special Mode and
the Normal Mode, as shown in the following sections.
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Reading Error Status Code in Special Mode
When OE(ED2) is pulled low while in Special Mode, error detection and load error status codes are loaded into
the Shift Register, in addition to enabling output ports to sink current. Figure 16 shows the timing sequence for
error detection. The 0 and 1 signal levels are sampled at the rising edge of each CLK. At least three zeros must
be sampled at the voltage low signal OE(ED2). Immediately after the second zero is sampled, the data input
source of the Shift Register changes to the 8-bit parallel Error Status Code register, instead of from the serial
data on SDI. Normally, the error status codes are generated at least 2 µs after the falling edge of OE(ED2). The
occurrence of the third or later zero saves the detected error status codes into the Shift Register. Therefore,
when OE(ED2) is low, the serial data cannot be shifted into TLC5916/TLC5917 via SDI. When OE(ED2) is pulled
high, the data input source of the Shift Register is changed back to SDI. At the same time, the output ports are
disabled and the error detection is completed. Then, the error status codes saved in the Shift Register can be
shifted out via SDO bit by bit along with CLK, as well as the new serial data can be shifted into
TLC5916/TLC5917 via SDI.
While in Special Mode, the TLC5916/TLC5917 cannot simultaneously transfer serial data and detect LED load
error status.
1
2
3
CLK
>2 µs
0
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
OE(ED2)
LE(ED1)
SDO
0
0
Error Status Code
Bit 7
Bit 6 Bit 5 Bit 4
Data source of
shift register
SDI
Error Detection
SDI
Figure 16. Reading Error Status Code
Writing Configuration Code in Special Mode
When in Special Mode, the active high signal LE(ED1) latches the serial data in the Shift Register to the
Configuration Latch, instead of the Output Latch. The latched serial data is used as the Configuration Code.
The code is stored until power off or the Configuration Latch is rewritten. As shown in Figure 17, the timing for
writing the Configuration Code is the same as the timing in the Normal Mode to latching output channel data.
Both the Configuration Code and Error Status Code are transferred in the common 8-bit Shift Register. Users
must pay attention to the sequence of error detection and current adjustment to avoid the Configuration Code
being overwritten by Error Status Code.
0
1
2
3
4
6
7
5
CLK
OE(ED2)
LE(ED1)
1
0
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
8-Bit Configuration Code
SDI
Figure 17. Writing Configuration Code
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Open-Circuit Detection Principle
The LED Open-Circuit Detection compares the effective current level Iout with the open load detection threshold
current IOUT,Th. If IOUT is below the IOUT,Th threshold, the TLC5916/TLC5917 detects an open-load condition. This
error status can be read as an error status code in the Special Mode. For open-circuit error detection, a channel
must be on.
Table 1. Open-Circuit Detection
CONDITION OF OUTPUT
STATE OF OUTPUT PORT
ERROR STATUS CODE
MEANING
CURRENT
Off
IOUT = 0 mA
0
Detection not possible
Open circuit
(1)
IOUT < IOUT,Th
0
On
(1)
I
OUT ≥ IOUT,Th
Channel n error status bit 1
Normal
(1) IOUT,Th = 0.5 × IOUT,target (typical)
Short-Circuit Detection Principle (TLC5917 Only)
The LED short-circuit detection compares the effective voltage level (VOUT) with the shorted-load detection
threshold voltages VOUT,TTh and VOUT,RTh. If VOUT is above the VOUT,TTh threshold, the TLC5917 detects an
shorted-load condition. If VOUT is below the VOUT,RTh threshold, no error is detected/error bit is reset. This error
status can be read as an error status code in the Special Mode. For short-circuit error detection, a channel must
be on.
Table 2. Shorted-Load Detection
CONDITION OF OUTPUT
STATE OF OUTPUT PORT
ERROR STATUS CODE
MEANING
VOLTAGE
IOUT = 0 mA
OUT ≥ VOUT,TTh
Off
0
0
1
Detection not possible
Short circuit
V
On
VOUT < VOUT,RTh
Normal
Minimum
Return
Threshold
Minimum
Trigger
Threshold
Maximum
Trigger
Threshold
No Fault
Short Fault
2.2 V
2.5 V
3.1 V
VOUT
VOUT,RTh
VOUT,TTh
Figure 18. Short-Circuit Detection Principle
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Overtemperature Detection and Shutdown
TLC5916/TLC5917 is equipped with a global overtemperature sensor and eight individual, channel-specific,
overtemperature sensors.
•
When the global sensor reaches the trip temperature, all output channels are shut down, and the error status
is stored in the internal Error Status register of every channel. After shutdown, the channels automatically
restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset
after cooling down and can be read out as the error status code in the Special Mode.
•
When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut
down, and the error status is stored only in the internal Error Status register of the affected channel. After
shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains
on. The stored error status is not reset after cooling down and can be read out as error status code in the
Special Mode.
For channel-specific overtemperature error detection, a channel must be on.
The error status code is reset when TLC5916/TLC5917 returns to Normal Mode.
Table 3. Overtemperature Detection(1)
STATE OF OUTPUT PORT
CONDITION
IOUT = 0 mA
ERROR STATUS CODE
MEANING
Off
0
1
On
On → all channels
Off
Tj < Tj,trip global
Normal
Tj > Tj,trip global
All error status bits = 0
Global overtemperature
Tj < Tj,trip channel n
Tj > Tj,trip channel n
1
Normal
On
On → Off
Channel n error status bit = 0
Channel n overtemperature
(1) The global shutdown threshold temperature is approximately 170°C.
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8-Bit Configuration Code and Current Gain
Bit definition of the Configuration Code in the Configuration Latch is shown in Table 4.
Table 4. Bit Definition of 8-Bit Configuration Code
Bit 0
CM
1
Bit 1
HC
1
Bit 2
CC0
1
Bit 3
CC1
1
Bit 4
CC2
1
Bit 5
CC3
1
Bit 6
CC4
1
Bit 7
CC5
1
Meaning
Default
Bit 7 is first sent into TLC5916/TLC5917 via SDI. Bits 1 to 7 {HC, CC[0:5]} determine the voltage gain (VG) that
affects the voltage at R-EXT and indirectly affects the reference current, Iref, flowing through the external resistor
at R-EXT. Bit 0 is the Current Multiplier (CM) that determines the ratio IOUT,target/Iref. Each combination of VG and
CM gives a specific Current Gain (CG).
•
VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown below:
VG = (1 + HC) × (1 + D/64) / 4
D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20
Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point
number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage
gain VG into 128 steps and two sub-bands:
Low voltage sub-band (HC = 0): VG = 1/4 ~ 127/256, linearly divided into 64 steps
High voltage sub-band (HC = 1): VG = 1/2 ~ 127/128, linearly divided into 64 steps
CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range.
High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.
Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA
CG: The total Current Gain is defined as the following.
•
•
VR-EXT = 1.26 V × VG
Iref = VR-EXT/Rext, if the external resistor, Rext, is connected to ground.
IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG
CG = VG × 3CM – 1
Therefore, CG = (1/12) to (127/128), and it is divided into 256 steps. If CG = 127/128 = 0.992, the
IOUT,target-Rext
.
Examples
•
•
•
Configuration Code {CM, HC, CC[0:5]} = {1,1,111111}
VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992
Configuration Code = {1,1,000000}
VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5
Configuration Code = {0,0,000000}
VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12
After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore,
VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 19.
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1.00
0.75
CM = 0 (Low Current Multiplier)
HC = 0 (Low
Voltage SubBand)
HC = 1 (High
Voltage SubBand)
HC = 0 (Low
Voltage SubBand)
0.50
0.25
0.00
HC = 1 (High
Voltage SubBand)
CM = 1 (High Current Multiplier)
Configuration Code (CM, HC, CC[0:5]) in Binary Format
Figure 19. Current Gain vs Configuration Code
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PACKAGE OPTION ADDENDUM
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18-Sep-2008
PACKAGING INFORMATION
Orderable Device
TLC5916ID
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC5916IDG4
TLC5916IDR
SOIC
SOIC
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC5916IDRG4
TLC5916IN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLC5916INE4
TLC5916IPW
TLC5916IPWG4
TLC5916IPWR
TLC5916IPWRG4
TLC5917ID
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC5917IDG4
TLC5917IDR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLC5917IDRG4
TLC5917IN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLC5917INE4
TLC5917IPW
TLC5917IPWG4
TLC5917IPWR
TLC5917IPWRG4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC5916, TLC5917 :
Automotive: TLC5916-Q1, TLC5917-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLC5916IDR
TLC5916IPWR
TLC5917IDR
TLC5917IPWR
SOIC
TSSOP
SOIC
D
PW
D
16
16
16
16
2500
2000
2500
2000
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
6.5
7.0
6.5
7.0
10.3
5.6
2.1
1.6
2.1
1.6
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
Q1
Q1
Q1
Q1
10.3
5.6
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC5916IDR
TLC5916IPWR
TLC5917IDR
TLC5917IPWR
SOIC
TSSOP
SOIC
D
PW
D
16
16
16
16
2500
2000
2500
2000
333.2
346.0
333.2
346.0
345.9
346.0
345.9
346.0
28.6
29.0
28.6
29.0
TSSOP
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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