TLC5923RHBT [TI]
16-channel LED driver with 20Mhz data transfer rate with dot correctionn and full diagnose 32-VQFN -40 to 85;
| 型号： | TLC5923RHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-channel LED driver with 20Mhz data transfer rate with dot correctionn and full diagnose 32-VQFN -40 to 85 驱动器 |
| 文件： | 总15页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
LED DRIVER
FEATURES
APPLICATIONS
•
•
•
•
Monocolor, Multicolor, Fullcolor LED Display
Monocolor, Multicolor LED Signboard
Display Backlighting
•
16 Channels
•
Drive Capability
– 0 to 80 mA (Constant-Current Sink)
Constant Current Accuracy
– ±1% (typical)
Multicolor LED lighting applications
•
DESCRIPTION
•
•
•
•
•
•
•
•
•
Serial Data Interface
The TLC5923 is a 16 channel constant-current sink
driver. Each channel has a On/Off state and a
128-step adjustable constant current sink (dot correc-
tion). The dot correction adjusts the brightness vari-
ations between LED, LED channels and other LED
drivers. Both dot correction and On/Off state are
accessible via a serial data interface. A single exter-
nal resistor sets the maximum current of all 16
channels.
Fast Switching Output: Tr / Tf = 10ns (typical)
CMOS Level Input/Output
30 MHz Data Transfer Rate
VCC = 3.0 V to 5.5 V
Operating Temperature = -20°C to 85 °C
LED Supply Voltage up to 17 V
32-pin HTSSOP (PowerPAD™) Package
Dot Correction
The TLC5923 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature con-
dition.
– 7 bit (128 Steps)
– individual adjustable for each channel
Controlled In-Rush Current
Error Information
•
•
– LOD: LED Open Detection
– TEF: Thermal Error Flag
VCC GND PGND SCLK
SIN
MODE
XLAT
BLANK
MODE
Constant Current
Driver
0
0
LOD
0
1
1
0
OUT0
Delay
x0
On/Off Register
0
Max. OUTn
Current
IREF
0
7−bit DC Register
6
On/Off
Input
BLANK
Shift
Register
1
16
Constant Current
Driver
LOD
OUT1
16
Delay
x1
1
15
On/Off Register
112
0
7
7−bit DC Register
13
LED Open
Detection
(LOD)
DC Input
Shift
Register
BLANK
Temperature
Error Flag
(TEF)
BLANK
Constant Current
Driver
15
1
0
LOD
OUT15
Delay
x15
15
111
On/Off Register
XERR
105
7−bit DC Register
111
0
1
MODE
SOUT
Figure 1. Function Block Diagram
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
Package
Part Number(1)
-20 °C to 85 °C
4 mm x 4 mm, 32-pin HTSSOP
TLC5923DAP
(1) The DAP package is available in tape and reel. Add R suffix (TLC5923DAPR) to order quantities of
2000 parts per reel.
(1)(2)
ABSOLUTE MAXIMUM RATINGS
TLC5923
- 0.3 to 6
UNIT
V
VCC
IO
Supply voltage(2)
Output current (dc)
Input voltage range(2)
IL(LC)
90
mA
V
VI
V(BLANK), V(XLAT), V(SCLK), V(SIN), V(MODE)
V(SOUT), V(XDOWN)
- 0.3 to VCC + 0.3
- 0.3 to VCC + 0.3
-0.3 to 18
V
VO
Output voltage range(2)
V(OUT0) - V(OUT15)
V
HBM (JEDEC JESD22-A114, Human Body
Model)
2
kV
V
ESD rating
CDM (JEDEC JESD22-C101, Charged Device
Model)
500
Tstg
Storage temperature range
-40 to 150
3.9
°C
W
Continuous total power dissipation at (or below) TA = 25°C
Power dissipation rating at (or above) TA = 25°C
31.4
mW/°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
DC Characteristics
MIN
NOM
MAX
5.5
UNIT
V
VCC
VO
Supply voltage
3
Voltage applied to output, (Out0 - Out15)
High-level input voltage
Low-level input voltage
17
V
VIH
VIL
0.8 VCC
GND
VCC
0.2 VCC
-1
V
V
IOH
High-level output current
VCC = 5 V at SOUT
mA
VCC = 5 V at SOUT,
XDOWN
IOL
Low-level output current
1
mA
IOLC
TA
Constant output current
Operating free-air temperature range(1)
OUT0 to OUT15
80
85
mA
-20
°C
(1) Please contact TI sales for slightly extended temperature range.
2
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
AC Characteristics
VCC = 3 V to 5.5 V, TA = -20°C to 85°C (unless otherwise noted)
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
twh0/twl0
twh1
tsu0
tsu1
tsu2
tsu3
th0
Clock frequency
SCLK
30
CLK pulse duration
XLAT pulse duration
SCLK=H/L
16
20
10
10
10
10
10
10
10
10
XLAT=H
ns
SIN - SCLK↑
SCLK↑-XLAT↓
MODE↑↓-SCLK↑
MODE↑↓-XLAT↓
SCLK↑-SIN
ns
ns
Setup time
Hold time
ns
ns
ns
th1
XLAT↓-SCLK↑
SCLK↑-MODE↑↓
XLAT↓-MODE↑↓
ns
th2
ns
th3
ns
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = - 20°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = - 1 mA, SOUT
IOL = 1 mA, SOUT
MIN
VCC -0.5
TYP
MAX
UNIT
V
VOH
VOL
High-level output voltage
Low-level output voltage
0.5
1
V
VI = VCC or GND, BLANK, XLAT, SCLK, SIN,
MODE
II
Input current
-1
µA
No data transfer, All output OFF, VO = 1 V,
R(IREF) = 10 kΩ
6
12
25
No data transfer, All output OFF, VO = 1 V,
R(IREF) = 1.3 kΩ
ICC
Supply current
mA
Data transfer 30 MHz, All output ON, VO = 1 V,
R(IREF) = 1.3 kΩ
Data transfer 30 MHz, All output ON, VO = 1 V,
R(IREF) = 600 kΩ
36
80
65(1)
90
IOLC
Constant output current
Leakage output current
All output ON, VO = 1 V, R(IREF) = 600 Ω
70
mA
µA
µA
%
All output OFF, VO = 15 V, R(IREF) = 600 Ω ,
OUT0 to OUT15
ILO0
0.1
10
ILO1
VXERR = 5.5 V, No TEF and LOD
All output ON, VO = 1 V, R(IREF) = 600 Ω,
OUT0 to OUT15
∆IOLC0
Constant current error
Constant current error
Power supply rejection ratio
± 1
± 4
± 1
± 4
device to device, averaged current from OUT0
to OUT15, R(IREF) = 600 Ω
∆IOLC1
∆IOLC2
± 8.5
± 4
%
All output ON, VO = 1 V, R(IREF) = 600 Ω,
OUT0 to OUT15
%/V
All output ON, VO = 1 V to 3 V, R(IREF) = 600
∆IOLC3
Load regulation
Ω,
± 2
± 6
%/V
OUT0 to OUT15
T(TEF)
V(LOD)
V(IREF)
Thermal error flag threshold Junction temperature, rising temperature(2)
150
160
0.3
180
0.4
°C
V
LED open detection
threshold
Reference voltage output
R(IREF) = 600 Ω
1.20
1.24
1.28
V
(1) Measured at device start-up temperature. Once the IC is operating (self heating), lower ICC values will be seen. See Figure 15.
(2) Not tested. Specified by design.
3
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
SWITCHING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
tr0
SOUT(see
)
16
Rise time
ns
OUTx, VCC = 5 V, TA = 60°C,
tr1
10
30
16
30
(2)
DCx = 7F (see
)
(1)
tf0
SOUT (see
)
Fall time
ns
OUTx, VCC = 5 V, TA = 60°C,
tf1
10
(2)
DCx = 7F (see
)
(3)
tpd0
tpd1
tpd2
SCLK↑ - SOUT↑↓ (see
)
300
300
60
(3)
MODE↑↓ - SOUT↑↓ (see
BLANK↓ - OUT0↑↓ (see
)
(4)
)
Propagation delay
time
(4)
ns
ns
tpd3
tpd4
XLAT↑ - OUT0↑↓ (see
)
60
(5)
OUTx↑↓-XERR↑↓ (see
)
1000
XLAT↑-IOUT(dot-correction) (see
)
tpd5
td
1000
30
(6)
OUTn↑↓-OUT(n+1)↑↓
Output delay time
14
22
(4)
(see
)
(1) See Figure 5. Defined as from 10% to 90%
(2) See Figure 6. Defined as from 10% to 90%
(3) See Figure 5, Figure 13
(4) See Figure 6 and Figure 13
(5) See Figure 6, Figure 7, and Figure 13
(6) See Figure 6
DAP PACKAGE
(TOP VIEW)
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
VCC
IREF
2
BLANK
XLAT
SCLK
SIN
3
MODE
XERR
SOUT
PGND
OUT15
OUT14
PGND
OUT13
OUT12
OUT11
OUT10
PGND
OUT9
OUT8
4
5
6
PGND
OUT0
OUT1
PGND
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
7
8
9
10
11
12
13
14
15
16
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
Blank (Light OFF). When BLANK=H, All OUTx outputs are forced OFF. When BLANK=L,
ON/OFF of OUTx outputs are controlled by input data.
BLANK
2
2
GND
IREF
1
Ground
31
I/O
I
Reference current terminal
Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control
logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic.
MODE
OUT0
30
7
O
Constant current output
4
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
Terminal Functions (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
8
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
10
11
12
13
15
16
17
18
20
21
22
23
25
26
6, 14, 19, 24,
27
PGND
SCLK
Power ground
Data shift clock. Note that the internal connections are switched by MODE (pin #30). At
SCLK↑, the shift-registers selected by MODE shift the data.
4
I
SIN
5
I
Data input of serial I/F
SOUT
VCC
28
32
29
O
Data output of serial I/F
Power supply voltage
XERR
O
I
Error output. XERR is open drain terminal. XERR gets L when LOD or TEF detected.
Data latch. Note that the internal connections are switched by MODE (pin #30). At XLAT↑, the
latches selected by MODE get new data.
XLAT
3
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
(Note: Resistor values are equivalent resistance and not tested).
VCC
400 W
INPUT
GND
Figure 2. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE)
10 W
SOUT
GND
Figure 3. Output Equivalent Circuit
5
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS (continued)
20 W
XERR
GND
Figure 4. Output Equivalent Circuit (XERR)
PARAMETER MEASUREMENT INFORMATION
SOUT
15 pF
Figure 5. Test Circuit for tr0, tf0, td0, td1
51 Ω
OUTn
15 pF
Figure 6. Test Circuit for tr1, tf1, tpd2, tpd3, tpd5, tpd6
470 kΩ
XDOWN
Figure 7. Test Circuit for tpd4
6
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
PRINCIPLES OF OPERATION
Setting Maximum Channel Current
The maximum output current per channel is set by a single external resistor, R(IREF), which is placed between
IREF and GND. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24V. The
maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 40. The
maximum output current can be calculated by Equation 1:
V
IREF
I
+
40
MAX
R
IREF
(1)
where:
VIREF = 1.24V typ.
RIREF = User selected external resistor (RIREF should not be smaller than 600 Ω)
Figure 8 shows the maximum output current, IO(LC), versus R(IREF) . In Figure 8, R(IREF) is the value of the resistor
between IREF terminal to ground, and IO(LC) is the constant output current of OUT0,.....OUT15.
100 k
48.8 k
V
Outn
= 1 V
DC = 127
10 k
9.76 k
4.88 k
2.44 k
1.63 k
1.22 k
976
1 k
813
697
100
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
− Output Current − mA
I
OLC
Figure 8. Reference Resistor vs Output Current
Setting Dot-Correction
The TLC5923 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This
is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the
output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel
output can be adjusted in 128 steps from 0% to 100% of the maximum output current IMAX. Equation 2
determines the output current for each OUTn:
I
DC
n
MAX
I
+
Outn
where:
127
(2)
IMax = the maximum programmable current of each output
DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)
n = 0, 1, 2 ... 15
7
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
Dot correction data are entered for all channels at the same time. The complete dot correction data format
consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 9 shows the DC data format.
LSB
0
MSB
111
6
7
104
105
DC 0.0
DC 0.6
DC 1.0
DC 14.6
DC 15.0
DC 15.6
DC OUT0
DC OUT15
DC OUT2 − DC OUT14
Figure 9. DC Data Format
To input data into dot correction register, MODE must be set to high. The internal input shift register is then set to
112 bit width. After all serial data is clocked in, a rising edge of XLAT latch the data to the dot correction register
(Figure 13).
Output Enable
All OUTn channels of TLC5923 can switched off with one signal. When BLANK signal is set to high, all OUTn are
disabled, regardless of On/Off status of each OUTn. When BLANK is the to low, all OUTn work under normal
conditions.
Table 1. BLANK Signal Truth Table
BLANK
LOW
OUT0 - OUT15
Normal condition
Disabled
HIGH
Setting Channel On/Off Status
All OUTn channels of TLC5923 can be switched on or off independently. Each of the channels can be
programmed with a 1-bit word. On/Off data are entered for all channels at the same time. The complete On/Off
data format consists of 16 x 1-bit words, which form a 16-bit wide data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 10 shows the On/Off data format.
LSB
0
MSB
15
On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10 OUT11 OUT12 OUT13 OUT14 OUT15
On/Off Data
Figure 10. On/Off Data
To input On/Off data into On/Off register MODE must be set to low. The internal input shift register is then set to
16 bit width. After all serial data is clocked in, a rising edge of XLAT during BLANK = high is used to latch data
into the On/Off register. Figure 13 shows the On/Off data input timing chart.
With the falling edge of XLAT signal all data in input shift register is replaced with LOD channel data. These data
is clocked out to SOUT when new On/Off data is clocked in.
Delay Between Outputs
The TLC5923 has graduated delay circuits between outputs. These delay circuits can be found in the constant
current block of the device (see Figure 1). The fixed delay time is 20 ns (typical), OUT0 has no delay, OUT1 has
20 ns delay, OUT2 has 40 ns delay, etc. This delay prevents large inrush currents, which reduce power supply
bypass capacitor requirements when the outputs turn on.
8
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
Serial Interface Data Transfer Rate
The TLC5923 includes a flexible serial interface, which can be connected to microcontroller or digital signal
processor. Only 3 pins are in required to input data into the device. The rising edge of SCLK signal shifts the
data from SIN pin to internal shift register. After all data is clocked in, a rising edge of XLAT latches the serial
data to the internal registers. All data is clocked in with MSB first. Multiple TLC5923 devices can be cascaded by
connecting SOUT pin of one device with SIN pin of following device. The SOUT pin can also be connected to
controller to receive LOD information from TLC5923.
V
V
V
V
V
(LED)
CC
(LED)
(LED)
(LED)
100 k
OUT0
OUT15
SOUT
OUT0
OUT15
SOUT
SIN
SIN
SIN
XERR
SCLK
XLAT
XERR
SCLK
XLAT
MODE
BLANK
XERR
SCLK
XLAT
V
V
CC
CC
100 nF
100 nF
TLC5923
IC 0
TLC5923
IC n
Controller
MODE
BLANK
MODE
BLANK
IREF
IREF
SOUT
5
Figure 11. Cascading Devices
Figure 11 shows a example application with n cascaded TLC5923 devices connected to a controller. The
maximum number of cascaded TLC5923 devices depends on application system and data transfer rate.
Equation 3 calculates the minimum data input frequency needed.
f_(SCLK)
where:
112
f_(update)
n
(3)
f_(SCLK): The minimum data input frequency for SCLK and SIN.
f_(update): The update rate of the whole cascaded system.
n: The number of cascaded TLC5923 devices.
Operating Modes
The TLC5923 has different operating modes depending on MODE signal. Table 2 shows the available operating
modes.
Table 2. TLC5923 Operating Modes Truth Table
MODE SIGNAL
LOW
INPUT SHIFT REGISTER
MODE
16 bit
On/Off Mode
HIGH
112 bit
Dot Correction Data Input Mode
9
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
Error Information Output
The open-drain output XERR is used to report both of the TLC5923 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through a external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on,
and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled
up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error.
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 3. XERR Truth Table
ERROR CONDITION
TEMPERATURE
ERROR INFORMATION
SIGNALS
OUNTn VOLTAGE
Don't Care
TEF
L
LOD
X
BLANK
XERR
TJ < T(TEF)
TJ > T(TEF)
TJ < T(TEF)
H
H
L
H
L
L
L
Don't Care
H
X
OUTn > V(LOD)
OUTn < V(LOD)
OUTn > V(LOD)
OUTn < V(LOD)
L
L
L
L
H
TJ > T(TEF)
H
L
H
H
TEF: Thermal Error Flag
The TLC5923 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature T(TEF) (160°C typical), the TEF circuit trips and pulls
XERR to ground.
LOD: LED Open Detection
The TLC5923 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16
LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are met
simultaneously:
1. BLANK is set to LOW
2. When the voltage at OUTn is less than V(LOD) (0.3 V typ.) (Note: the voltage at each OUTn is sampled 1 µs
after being turned on).
The LOD circuit also pulls XERR to GND when tripped.
The LOD status of each channel can also be read out from the TLC5923 SOUT pin. When MODE is low and
On/Off data is latched with rising edge of XLAT, LOD data is written to the input shift register with the falling edge
of XLAT. These LOD data is clocked out to SOUT when new On/Off data is clocked in. These allow to control the
LOD status of each OUTn channel. Figure 12 shows the LOD data format.
LSB
0
MSB
15
LOD
OUT0
LOD
OUT1
LOD
OUT2
LOD
OUT3
LOD
OUT4
LOD
OUT5
LOD
OUT6
LOD
OUT7
LOD
OUT8
LOD
OUT9
LOD
LOD
LOD
LOD
LOD
LOD
OUT10 OUT11 OUT12 OUT13 OUT14 OUT15
LOD Data
Figure 12. LOD Data
10
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
Figure 13. Timing Chart Example for ON/OFF Setting to Dot-Correction
11
TLC5923
www.ti.com
SLVS550–DECEMBER 2004
Power Rating - Free-Air Temperature
Figure 14 shows total power dissipation. Figure 15 shows supply current versus free-air temperature.
Power Dissipation
vs
Temperature
3.9
3.2
1.48
2
−20
0
25
85
T
A
− Free-Air Temperature − °C
Figure 14.
Supply Current(A)
vs
Free-Air Temperature
70
60
50
40
30
20
10
0
−50 −30 −10 10 30 50 70 90 110 130 150
T
A
− Free-Air Temperature − °C
A. Data Transfer = 30 MHz / All Outputs, ON/VO = 1 V / RIREF = 600 Ω / AVDD = 5 V
Figure 15.
12
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLC5923DAP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
DAP
32
32
46
TBD
TBD
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
TLC5923DAPR
DAP
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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Addendum-Page 1
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