TLC59401PWP_技术文档

TLC59401

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SBVS137 –DECEMBER 2009

16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

Check for Samples: TLC59401

1

FEATURES

APPLICATIONS

•

Monocolor, Multicolor, Full-Color LED Displays

LED Signboards

Display Back-Lighting

23

•

16 Channels

•

12-Bit (4096 Steps) Grayscale PWM Control

Dot Correction

–

6-Bit (64 Steps)

DESCRIPTION

•

Drive Capability (Constant-Current Sink)

The TLC59401 is a 16-channel, constant-current sink,

LED driver. Each channel has an individually

adjustable 4096-step grayscale PWM brightness

control and a 64-step constant-current sink (dot

correction). The dot correction adjusts the brightness

variations between LED channels and other LED

drivers. Both grayscale control and dot correction are

accessible via a serial interface. A single external

resistor sets the maximum current value of all 16

channels.

–

0 mA to 80 mA (V_CC≤ 3.6 V)

0 mA to 120 mA (V_CC> 3.6 V)

•

LED Power-Supply Voltage up to 17 V

V_CC= 3.0 V to 5.5 V

Serial Data Interface

Controlled Inrush Current

30-MHz Data Transfer Rate

CMOS Level I/O

The TLC59401 features two error information circuits.

The LED open detection (LOD) indicates a broken or

disconnected LED at an output terminal. The thermal

error flag (TEF) indicates an over-temperature

condition.

Error Information

–

LOD: LED Open Detection

TEF: Thermal Error Flag

VCC

GND

SCLK

SIN

XLAT

CNT

MODE

Constant-Current

Driver

1

0

12−Bit Grayscale

PWM Control

GS Register

OUT0

V

IREF

REF

=1.24

MODE

Max. OUTn

Current

11

5

0

1

0

Delay

x0

V

0

DC Register

6−Bit Dot Correction

LED Open Detection

0

GSCLK

BLANK

GS Counter

CNT

Input

Shift

Register

CNT

0

96

Status

Information:

Constant-Current

Driver

12−Bit Grayscale

PWM Control

192

GS Register

12

OUT1

23

11

LOD,

TED,

DC DATA

Delay

x1

95

96

DC Register

6−Bit Dot Correction

LED Open Detection

191

1

0

6

MODE

96

Temperature

LED Open

Detection

(LOD)

CNT

Error Flag

(TEF)

Input

Shift

Register

Constant-Current

Driver

12−Bit Grayscale

PWM Control

GS Register

180

OUT15

191

95

Delay

x15

XERR

DC Register

90

6−Bit Dot Correction

LED Open Detection

191

SOUT

Figure 1. Functional Block Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PowerPAD is a trademark of Texas Instruments Incorporated.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLC59401

SBVS137 –DECEMBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE

PART NUMBER

TLC59401PWP

TLC59401RHB

–40°C to +85°C

28-pin HTSSOP PowerPAD™

32-pin 5 mm x 5 mm QFN

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

TLC59401

–0.3 to 6

130

UNIT

V

V_I

I_O

Input voltage range⁽²⁾

Output current (dc)

V_CC

mA

V_(BLANK), V_(SCLK), V_(XLAT), V_(MODE), V_(SIN), V_(GSCLK), V_(IREF)

V_(TEST)

,

V_I

Input voltage range

Output voltage range

–0.3 to V_CC+0.3

V

V_(SOUT), V_(XERR)

–0.3 to V_CC+0.3

–0.3 to 18

2

V

V_O

V_(OUT0)to V_(OUT15)

HBM (JEDEC JESD22-A114, human body model)

CDM (JEDEC JESD22-C101, charged device model)

kV

ESD rating

500

V

T_J(max)Operating junction temperature

+150

°C

T_STG

T_A

Storage temperature range

Operating ambient temperature range

HTSSOP (PWP)⁽⁴⁾

QFN (RHB)⁽⁴⁾

–55 to +150

–40 to +85

31.58

°C

°C/W

Package thermal impedance⁽³⁾

35.9

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

(4) With PowerPAD soldered on PCB with 2-oz. trace of copper. See TI application report SLMA002 for further information.

2

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RECOMMENDED OPERATING CONDITIONS

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DC CHARACTERISTICS

V_CC

V _O

V_IH

V_IL

Supply Voltage

3

5.5

17

V

Voltage applied to output (OUT0 – OUT15)

High-level input voltage

0.8 V_CC

GND

V_CC

0.2 V_CC

–1

V

Low-level input voltage

V

I_OH

I_OL

High-level output current

Low-level output current

V_CC= 5 V at SOUT

mA

°C

V_CC= 5 V at SOUT, XERR

OUT0 to OUT15, V_CC≤ 3.6 V

OUT0 to OUT15, V_CC> 3.6 V

1

80

I_OLC

Constant output current

120

+125

+85

T_J

Operating junction temperature

–40

T_A

Operating free-air temperature range

AC CHARACTERISTICS

At V_CC= 3 V to 5.5 V and T_A= –40°C to +85°C, unless otherwise noted.

Data shift clock

frequency

f_(SCLK)

SCLK

30

MHz

Grayscale clock

frequency

f_(GSCLK)

GSCLK

t_wh0/t_wl0

t_wh1/t_wl1

t_wh2

t_wh3

t_su0

t_su1

t_su2

t_su3

t_su4

t_su5

t_h0

SCLK pulse duration

GSCLK pulse duration

XLAT pulse duration

BLANK pulse duration

SCLK = high/low (see Figure 12)

GSCLK = high/low (see Figure 12)

XLAT = high (see Figure 12)

16

20

5

ns

BLANK = high (see Figure 12)

SIN - SCLK↑ (see Figure 12)

SCLK↓ - XLAT↑ (see Figure 12)

MODE↑↓ - SCLK↑ (see Figure 12)

MODE↑↓ - XLAT↑ (see Figure 12)

BLANK↓ - GSCLK↑ (see Figure 12)

XLAT↑ - GSCLK↑ (see Figure 12)

SCLK↑ - SIN (see Figure 12)

10

30

3

Setup time

Hold Time

ns

t_h1

XLAT↓ - SCLK↑ (see Figure 12)

SCLK↑ - MODE↑↓ (see Figure 12)

XLAT↓ - MODE↑↓ (see Figure 12)

GSCLK↑ - BLANK↑ (see Figure 12)

10

t_h2

t_h3

t_h4

DISSIPATION RATINGS

POWER RATING

DERATING FACTOR

ABOVE T_A= +25°C

POWER RATING

T_A= +70°C

POWER RATING

T_A= +85°C

PACKAGE

T_A< +25°C

28-pin HTSSOP with

PowerPAD soldered⁽¹⁾

3958 mW

31.67 mW/°C

2533 mW

2058 mW

28-pin HTSSOP

without PowerPAD

soldered

32-pin QFN⁽¹⁾

2026 mW

3482 mW

16.21 mW/°C

27.86 mW/°C

1296 mW

2228 mW

1053 mW

1811 mW

(1) The PowerPAD is soldered to the PCB with a 2-oz. copper trace. See application report SLMA002 for further information.

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ELECTRICAL CHARACTERISTICS

At V_CC= 3 V to 5.5 V and T_A= –40°C to +85°C, unless otherwise noted.

TLC59401

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

V_OH

V_OL

High-level output voltage

Low-level output voltage

I_OH= –1 mA, SOUT

I_OL= 1 mA, SOUT

V_CC– 0.5

V

0.5

1

V

V_I= V_CCor GND; BLANK, TEST, GSCLK, SCLK, SIN, XLAT pin

V_I= GND; MODE pin

–1

μA

mA

μA

I_I

Input current

1

V_I= V_CC; MODE pin

50

6

No data transfer, all output OFF, V_O= 1 V, R_(IREF)= 10 kΩ

No data transfer, all output OFF, V_O= 1 V, R_(IREF)= 1.3 kΩ

Data transfer 30 MHz, all output ON, V_O= 1 V, R_(IREF)= 1.3 kΩ

Data transfer 30 MHz, all output ON, V_O= 1 V, R_(IREF)= 640 Ω

All output ON, V_O= 1 V, R_(IREF)= 640 Ω

0.9

5.2

16

30

61

12

25

60

69

0.1

I_CC

Supply current

I_O(LC)

I_lkg

Constant output current

Leakage output current

54

All output OFF, V_O= 15 V, R_(IREF)= 640 Ω , OUT0 to OUT15

All output ON, V_O= 1 V, R_(IREF)= 640 Ω, OUT0 to OUT15,

±1

±4

±8

%

–20°C to +85°C⁽¹⁾

All output ON, V_O= 1 V, R_(IREF)= 640 Ω, OUT0 to OUT15⁽¹⁾

All output ON, V_O= 1 V, R_(IREF)= 320 Ω, V_CC> 3.6 V, OUT0 to

ΔI_O(LC0)

Constant sink current error

OUT15,

±1

±6

%

–20°C to +85°C⁽¹⁾

All output ON, V_O= 1 V, R_(IREF)= 320 Ω, V_CC> 3.6 V, OUT0 to

±1

–2, +0.4

–2.7, +2

±1

±8

±4

OUT15⁽¹⁾

Device to device, averaged current from OUT0 to OUT15,

ΔI_O(LC1)

ΔI_O(LC2)

Constant sink current error

%

R_(IREF)= 1920 Ω (20 mA)⁽²⁾

Device to device, averaged current from OUT0 to OUT15,

R_(IREF)= 480 Ω (80 mA)⁽²⁾

All output ON, V_O= 1 V, R_(IREF)= 640 Ω OUT0 to OUT15,

%/V

V_CC= 3 V to 5.5 V⁽³⁾

ΔI_O(LC3)

Line regulation

All output ON, V_O= 1 V, R_(IREF)= 320 Ω OUT0 to OUT15,

±1

±2

±6

%/V

°C

V_CC> 3.6 V⁽³⁾

All output ON, V_O= 1 V to 3 V, R_(IREF)= 640 Ω, OUT0 to OUT15⁽⁴⁾

ΔI_O(LC4)

Load regulation

All output ON, V_O= 1 V to 3 V, R_(IREF)= 320 Ω, V_CC> 3.6 V, OUT0 to

±8

OUT15⁽⁴⁾

T_(TEF)

V_(LED)

V_(IREF)

Thermal error flag threshold

Junction temperature⁽⁵⁾

+150

1.20

+170

0.4

LED open detection

threshold

0.3

V

Reference voltage output

R_(IREF)= 640 Ω

1.24

1.28

V

(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1.

(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1.

The ideal current is calculated by Equation 3 in Table 1.

(3) The line regulation is calculated by Equation 4 in Table 1.

(4) The load regulation is calculated by Equation 5 in Table 1.

(5) Not tested. Specified by design.

4

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Table 1. Test Parameter Equations

I_OUTn- I_{OUTavg _ 0-15}

´100

D(%) =

I_{OUTavg _ 0-15}

(1)

(2)

I_OUTavg- I_OUT(IDEAL)

D(%) =

´100

I_OUT(IDEAL)

æ

ç

ö

÷

1.24V

R_IREF

I_OUT(IDEAL)= 31.5 ´

è

ø

(3)

(4)

(5)

(I_OUTnat V_CC= 5.5V) - (I_OUTnat V_CC= 3.0V)

(I_OUTnat V_CC= 3.0V)

100

2.5

D(% / V) =

D(%/ V) =

´

(I_OUTnat V_OUTn= 3.0V) - (I_OUTnat V_OUTn= 1.0V)

(I_OUTnat V_OUTn= 1.0V)

100

´

2.0

SWITCHING CHARACTERISTICS

At V_CC= 3 V to 5.5 V, C_L= 15 pF, and T_A= –40°C to 85°C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

10

MAX UNIT

t_r0

SOUT

16

ns

30

Rise time

t_r1

OUTn, V_CC= 5 V, T_A= +60°C, DCn = 3Fh

SOUT

t_f0

16

ns

30

Fall time

t_f1

OUTn, V_CC= 5 V, T_A= +60°C, DCn = 3Fh

SCLK - SOUT (see Figure 12)

BLANK - OUT0 (see Figure 12)

OUTn - XERR (see Figure 12)

GSCLK - OUT0 (see Figure 12)

XLAT - I_OUT(dot correction) (see Figure 12)

OUTn - OUT(n+1) (see Figure 12)

10

t_pd0

t_pd1

t_pd2

t_pd3

t_pd4

t_d

30

60

ns

Propagation delay time

1000

60

Output delay time

20

30

t_outon– T_gsclk(see Figure 12), GSn = 01h,

GSCLK = 11 MHz

t_{on_err}

Output on-time error

–90

–50

10

ns

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PIN CONFIGURATIONS

PWP PACKAGE

28-PIN HTSSOP PowerPAD

(TOP VIEW)

RHB PACKAGE

32-PIN 5 mm × 5 mm QFN

(TOP VIEW)

GND

BLANK

XLAT

1

2

3

4

5

6

7

8

9

28 VCC

27 IREF

32 31 30 29 28 27 26 25

26 TEST

25 GSCLK

24 SOUT

23 XERR

22 OUT15

21 OUT14

20 OUT13

19 OUT12

18 OUT11

17 OUT10

16 OUT9

15 OUT8

SCLK

SIN

1

2

3

4

5

6

7

8

24 GSCLK

SCLK

SIN

SOUT

23

MODE

OUT0

22 XERR

21 OUT15

MODE

OUT0

OUT1

OUT2

Thermal

Pad

Thermal

Pad

OUT14

OUT13

OUT12

OUT11

OUT1

OUT2

OUT3

OUT4

20

19

18

17

OUT3 10

OUT4 11

OUT5 12

OUT6 13

OUT7 14

9

10 11 12 13 14 15 16

(1) NC = no connection.

6

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SBVS137 –DECEMBER 2009

TERMINAL FUNCTION

TERMINAL

PWP

RHB

NO.

I/O

DESCRIPTION

NAME

NO.

Blank all outputs. When BLANK is high, all OUTn outputs are forced OFF.

GS counter is also reset. When BLANK is low, OUTn are controlled by the

grayscale PWM control.

BLANK

2

31

I

GND

1

30

24

G

I

Ground

GSCLK

25

Reference clock for grayscale PWM control

Reference current terminal. The maximum current for the outputs

OUT0-OUT15 is set with a resistor from IREF to GND. Any capacitance does

not need to be connected between IREF and GND.

IREF

NC

27

-

26

I/O

12, 13, 28, 29

4

No connection

Constant-current output. Multiple outputs can be configured in parallel to

increase the constant-current capability. Different voltages can be applied to

each output.

OUT0

7

O

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

SCLK

SIN

8

5

O

I

Constant-current output

Serial data shift clock

9

6

10

11

12

13

14

15

16

17

18

19

20

21

22

4

7

8

9

10

11

14

15

16

17

18

19

20

21

1

5

2

I

Serial data input

SOUT

TEST

VCC

24

26

28

23

25

27

O

I

Serial data output

Test pin: TEST must be connected to VCC

Power-supply voltage

I

Input mode-change pin. When MODE = GND, the device is in GS mode.

When MODE = V_CC, the device is in DC mode.

MODE

XERR

6

3

I

Error output. XERR is an open-drain terminal. XERR goes low when LOD or

TEF is detected.

23

22

O

Level triggered latch signal. When XLAT is high, the TLC59401 writes data

from the input shift register to either GS register (MODE is low) or DC

register (MODE is high). When XLAT is low, the data in the GS or DC

registers are held constant and do not change.

XLAT

3

32

I

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PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

Resistor values are equivalent resistance and not tested.

INPUT EQUIVALENT CIRCUIT

OUTPUT EQUIVALENT CIRCUIT (SOUT)

(BLANK, XLAT, SCLK, SIN, GSCLK, TEST)

VCC

23 W

400 W

INPUT

SOUT

GND

INPUT EQUIVALENT CIRCUIT (IREF)

VCC

OUTPUT EQUIVALENT CIRCUIT (XERR)

23 W

Amp

XERR

_

400 W

+

INPUT

100 W

GND

INPUT EQUIVALENT CIRCUIT (VCC)

OUTPUT EQUIVALENT CIRCUIT (OUT)

OUT

INPUT

GND

INPUT EQUIVALENT CIRCUIT (MODE)

INPUT

GND

Figure 2. Input and Output Equivalent Circuits

8

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PARAMETER MEASUREMENT INFORMATION (continued)

t_wh0, t_wIO, t_wh1, t_wl1, t_su0

t_su4,t_h4

V

(LED)

= 4 V

SOUT

Test Point

= 15 pF

R

= 51

L

C

L

OUTn

Test Point

= 15 pF

C

L

IOLC, IOLC3, IOLC4

=

V

(LED)

1 V

OUT0

OUTn

V

= 0 V ~ 7 V

_

CC

+

OUT15

IREF

Test Point

= 640

R

IREF

Figure 3. Parameter Measurement Circuits

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TYPICAL CHARACTERISTICS

REFERENCE RESISTOR

POWER DISSIPATION RATE

vs

OUTPUT CURRENT

FREE-AIR TEMPERATURE

4 k

10 k

TLC59401PWP

PowerPAD Soldered

7.68 kW

TLC59401RHB

3 k

1.92 kW

1 k

0.96 kW

2 k

1 k

0

0.64 kW

TLC59401PWP

PowerPAD Unsoldered

0.48 kW

0.38 kW

0.32 kW

100

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

I_O- Output Current - mA

T_A- Free-Air Temperature - °C

Figure 4.

Figure 5.

OUTPUT CURRENT

vs

OUTPUT CURRENT

vs

OUTPUT VOLTAGE

140

120

100

80

65

64

63

62

61

60

59

58

57

56

55

I_O= 60 mA,

V_CC= 5 V

T_A= +25°C,

I_O= 120 mA

I_O= 100 mA

V_CC= 5 V

T_A= +85°C

I_O= 80 mA

I_O= 60 mA

T_A= +25°C

T_A= -40°C

60

I_O= 40 mA

40

I_O= 20 mA

I_O= 5 mA

20

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

V_O- Output Voltage - V

Figure 6.

Figure 7.

10

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TYPICAL CHARACTERISTICS (continued)

CONSTANT OUTPUT CURRENT, ΔI_OLC

vs

AMBIENT TEMPERATURE

OUTPUT CURRENT

8

6

8

6

T_A= +25°C,

I_O= 60 mA

V_CC= 5 V

4

2

4

V_CC= 3.3 V

2

0

-2

-4

-6

-8

0

-2

-4

-6

-8

V_CC= 5 V

0

20

40

60

80

-40

-20

0

20

40

60

80

100

I_O- Output Current - mA

T_A- Ambient Temperature - °C

Figure 8.

Figure 9.

OUTPUT CURRENT

vs

OUTPUT CURRENT

vs

DOT CORRECTION LINEARITY (ABS Value)

140

120

100

80

70

I_O= 60 mA,

T_A= +25°C,

I_O= 120 mA

T_A= +25°C

V_CC= 5 V

60

50

40

30

20

10

0

T_A= +85°C

T_A= -40°C

I_O= 80 mA

I_O= 60 mA

60

40

I_O= 30 mA

I_O= 5 mA

20

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

Dot Correction Data - dec

Figure 10.

Figure 11.

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PRINCIPLES OF OPERATION

SERIAL INTERFACE

The TLC59401 has a flexible serial interface, which can be connected to microcontrollers or digital signal

processors in various ways. Only three pins are needed to input data into the device. The rising edge of SCLK

signal shifts the data from the SIN pin to the internal register. After all data are clocked in, a high-level pulse of

XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of

XLAT signal. All data are clocked in MSB first. The length of serial data is 96 bit or 192 bit, depending on the

programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although

new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale

data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing

grayscale data. Figure 12 shows the serial data input timing chart. More than two TLC59401s can be connected

in series by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading

two TLC59401s is shown in Figure 13 and the timing chart is shown in Figure 14. The SOUT pin can also be

connected to the controller to receive status information from TLC59401, as shown in Figure 22.

MODE

DC Data Input Mode

GS Data Input Mode

t

h3

su3

t

wh2

XLAT

1st GS Data Input Cycle

2nd GS Data Input Cycle

DC

MSB

DC

LSB

GS1

MSB

GS1

GS2

MSB

GS2

LSB

GS3

MSB

SIN

LSB

su1

192

t

su2

su0

h1

t

h2

t

wh0

h0

193

1

192

96

1

193

1

t

SCLK

SOUT

BLANK

GSCLK

t

pd0

wl0

SID2

MSB-1

GS1

MSB

SID1

MSB MSB-1

SID2

MSB

DC

-

MSB

GS2

MSB

SID1

LSB

-

t

wh3

First GS Data Output Cycle

Second GS Data Output Cycle

t

wh1

su4

h4

t

su5

1

4096

1

t

pd3

wl1

T

t

gsclk

pd4

pd1

t

pd3

OUT0

(current)

t + t

pd3 d

t

outon

d

t

pd1

+ t

d

OUT1

(current)

15 x t

t

+ 15 x t

d

pd1

d

OUT15

(current)

t

pd2

XERR

Figure 12. Serial Data Input Timing Chart

SIN(a)

SIN

SOUT(b)

SOUT

TLC59401 (a)

TLC59401 (b)

SCLK, XLAT,

BLANK,

GSCLK,

MODE

,

Figure 13. Cascading Two TLC59401 Devices

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MODE

XLAT

SIN(a)

SCLK

DCb

MSB

DCa

LSB

GSb1

MSB

GSa1

LSB

GSb2

MSB

GSa2

LSB

GSb3

MSB

385

1

384

192

1

385

1

96X2

192X2

SIDb2

MSB-1

GSb1

MSB

SIDb1

MSB-1

SIDb2

MSB

DCb

MSB

GSb2

MSB

SIDa1

LSB

SIDb1

MSB

-

SOUT(b)

BLANK

1

4096

1

GSCLK

OUT0

(current)

OUT1

(current)

OUT15

(current)

XERR

Figure 14. Timing Chart for Two Cascaded TLC59401 Devices

ERROR INFORMATION OUTPUT

The open-drain output XERR is used to report both of the TLC59401 error flags, TEF and LOD. During normal

operation, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to

V_CCthrough an external pull-up resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR

is pulled to GND. Because XERR is an open-drain output, multiple ICs can be ORed together and pulled up to

V_CCwith a single pull-up resistor. This capability reduces the number of signals needed to report a system error

(see Figure 22).

To differentiate the LOD and TEF signal from the XERR pin, LOD can be masked out with BLANK pulled high.

Table 2. XERR Truth Table

ERROR CONDITION

TEMPERATURE

ERROR INFORMATION

SIGNALS

OUTn VOLTAGE

Don't care

TEF

Low

High

Low

High

LOD

X

BLANK

XERR

High

Low

T_J< T_(TEF)

T_J> T_(TEF)

High

Don't care

X

OUTn > V_(LED)

OUTn < V_(LED)

OUTn > V_(LED)

OUTn < V_(LED)

Low

High

Low

High

Low

T_J< T_(TEF)

Low

T_J> T_(TEF)

Low

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TEF: THERMAL ERROR FLAG

The TLC59401 provides a temperature error flag (TEF) circuit to indicate an over-temperature condition of the IC.

If the junction temperature exceeds the threshold temperature (+160°C typical), TEF goes high and the XERR

pin goes to a low level. When the junction temperature becomes lower than the threshold temperature, TEF goes

low and the XERR pin becomes high impedance. The TEF status can also be read out from the TLC59401

status register.

LOD: LED OPEN DETECTION

The TLC59401 has an LED-open detection circuit that detects broken or disconnected LEDs. The LED open

detector pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the

Status Information Data is only active under the following open LED conditions:

1. OUTn is on and the time t_pd2(1 μs typical) has passed.

2. The voltage of OUTn is < 0.3V (typical)

The LOD status of each output can be also read out from the SOUT pin. See the Status Information Output

section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low

state after a high state. Therefore, the XLAT pin must be pulsed high, then low while XERR is active in order to

latch the LOD error into the Status Information Data for subsequent reading via the serial shift register.

DELAY BETWEEN OUTPUTS

The TLC59401 has graduated delay circuits between outputs. These circuits can be found in the constant-current

driver block of the device (see Figure 1). The fixed-delay time is 20 ns (typical), OUT0 has no delay, OUT1 has

20 ns delay, and OUT2 has 40 ns delay, etc. The maximum delay is 300 ns from OUT0 to OUT15. The delay

works during switch on and switch off of each output channel. These delays prevent large inrush currents which

reduces the bypass capacitors when the outputs turn on.

OUTPUT ENABLE

All OUTn channels of the TLC59401 can be switched off with one signal. When BLANK is set high, all OUTn

channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When

BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high

again in less than 300 ns, all outputs programmed to turn on do so for either the programmed number of

grayscale clocks or the length of time that the BLANK signal was low, whichever is lower. For example, if all

outputs are programmed to turn on for 1 ms, but the BLANK signal is only low for 200 ns, all outputs turn on for

200 ns even though some outputs are turning on after the BLANK signal has already gone high.

Table 3. BLANK Signal Truth Table

BLANK

Low

OUT0 - OUT15

Normal condition

Disabled

High

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SETTING MAXIMUM CHANNEL CURRENT

The maximum output current per channel is programmed by a single resistor, R_(IREF), which is placed between

IREF pin and GND pin. The voltage on IREF is set by an internal band gap V_(IREF)with a typical value of

1.24 V. The maximum channel current is equivalent to the current flowing through R_(IREF)multiplied by a factor of

31.5. The maximum output current can be calculated by Equation 6:

V

(IREF)

I

+

31.5

max

R

(IREF)

(6)

where:

V_(IREF)= 1.24 V

R_(IREF)= User-selected external resistor.

I_maxmust be set between 5 mA and 120 mA. The output current may be unstable if I_maxis set lower

than 5 mA. Output currents lower than 5 mA can be achieved by setting I_maxto 5 mA or higher and then

using dot correction.

See Figure 4 for the maximum output current I_Oversus R_(IREF). R_(IREF)is the value of the resistor between IREF

terminal to GND, and I_Ois the constant output current of OUT0 to OUT15. A variable power supply may be

connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum

output current per channel is 31.5 times the current flowing out of the IREF pin.

POWER DISSIPATION CALCULATION

The device power dissipation must be below the power dissipation rate of the device package to ensure correct

^{operation. Equation 7 calculat}ǒ^es_V^{the power dissipation of device:}

Ǔ

DC

n

₊ǒ_{VCC CC}Ǔ₎

P

I

N

d

D

OUT

MAX

PWM

63

(7)

where:

V_CC: device supply voltage

I_CC: device supply current

V_OUT: TLC59401 OUTn voltage when driving LED current

I_MAX: LED current adjusted by R_(IREF)Resistor

DC_n: maximum dot correction value for OUTn

N: number of OUTn driving LED at the same time

d_PWM: duty cycle defined by BLANK pin or GS PWM value

OPERATING MODES

The TLC59401 has two operating modes defined by MODE as shown in Table 4. The GS and DC registers are

set to random values that are not known immediately after power on. The GS and DC values must be

programmed before turning on the outputs. Please note that when initially setting GS and DC data after power

on, the GS data must be set before the DC data is set. Failure to set GS data before DC data may result in

losing the first bit of GS data. XLAT must be low when the MODE pin goes high-to-low or low-to-high to change

back and forth between GS mode and DC mode.

Table 4. TLC59401 Operating Modes Truth Table

MODE

GND

V_CC

INPUT SHIFT REGISTER

OPERATING MODE

Grayscale PWM Mode

192 bit

96 bit

Dot Correction Data Input Mode

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SETTING DOT CORRECTION

The TLC59401 has the capability to fine-adjust the output current of each channel (OUT0 to OUT15)

independently. This feature is also called dot correction. This feature is used to adjust the brightness deviations

of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a

6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I_max

.

The TEST pin must be connected to V_CCto ensure proper operation of the dot correction circuitry. Equation 8

determines the output current for each output n:

DCn

63

I

+ I

max

OUTn

(8)

where:

I_max= the maximum programmable output current for each output.

DCn = the programmed dot correction value for output n (DCn = 0 to 63).

n = 0 to 15

Figure 15 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The

format is Big-Endian format. In this format, the MSB is transmitted first, followed by the MSB-1, etc. The DC 15.5

in Figure 15 stands for the fifth-most significant bit for output 15.

MSB

0

LSB

95

5

6

89

90

DC 15.5

DC 15.0 DC 14.5

DC 1.0

DC 0.5

DC 0.0

DC OUT15

DC OUT0

DC OUT14 − DC OUT1

Figure 15. Dot Correction Data Packet Format

When MODE is set to V_CC, the TLC59401 enters the dot correction data input mode. The length of the input shift

register becomes 96 bits. After all serial data are shifted in, the TLC59401 writes the data in the input shift

register to the DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC

register is a level-triggered latch of the XLAT signal. Because XLAT is a level-triggered signal, SCLK and SIN

must not be changed while XLAT is high. After XLAT goes low, data in the DC register are latched and do not

change. The BLANK signal does not need to be high to latch in new data. When XLAT goes high, the new

dot-correction data immediately become valid and change the output currents if BLANK is low. XLAT has a setup

time (t_su1) and a hold time (t_h1) to SCLK, as shown in Figure 12.

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To input data into the dot correction register, MODE must be set to V_CC. The internal input shift register is then

set to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dot

correction register. Figure 16 shows the dc data input timing chart.

DC Mode Data

Input Cycle n

Input Cycle n+1

V

CC

MODE

SIN

DC n

MSB

DC n

MSB−1

DC n

MSB−2

DC n

LSB+1

DC n

LSB

DC n+1

MSB

DC n+1

MSB−1

DC n−1

LSB

t

wh0

SCLK

1

2

3

95

96

1

2

t

wl0

DC n−1

MSB

DC n−1

MSB−1

DC n−1

MSB−2

DC n−1

LSB+1

DC n−1

LSB

DC n

MSB

DC n

MSB−1

DC n

MSB−2

SOUT

XLAT

t

wh2

t

su1

t

h1

Figure 16. Dot Correction Data Input Timing Chart

When the IC is powered on, the data in the input shift register and DC register are not set to any default values.

Therefore, DC data must be written to the DC register before turning on the constant-current output.

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SETTING GRAYSCALE

The TLC59401 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12

bits per channel results in 4096 different brightness steps, from 0% to 100% brightness. Equation 9 determines

the brightness level for each output n:

GSn

4095

Brightness in % +

100

(9)

where:

GSn = the programmed grayscale value for output n (GSn = 0 to 4095)

n = 0 to 15

Grayscale data for all OUTn

The input shift register enters grayscale data into the grayscale register for all channels simultaneously. The

complete grayscale data format consists of 16 × 12 bit words, which forms a 192-bit wide data packet (see

Figure 17). The data packet must be clocked in MSB first.

MSB

0

LSB

191

11

GS 15.0 GS 14.11

GS OUT15

12

179

180

GS 15.11

GS 1.0 GS 0.11

GS 0.0

GS OUT14 − GS OUT1

GS OUT0

Figure 17. Grayscale Data Packet Format

When MODE is set to GND, the TLC59401 enters grayscale data input mode. The device switches the input shift

register to 192-bit width. After all data are clocked in, a rising edge of the XLAT signal latches the data into the

grayscale register (see Figure 18). New grayscale data immediately become valid at the rising edge of the XLAT

signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is high. The

first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete

the grayscale update cycle. All GS data in the input shift register are replaced with status information data (SID)

after updating the grayscale register.

DC Mode Data

Input Cycle

First GS Mode Data

Input Cycle After DC Data Input Cycle

Following GS Mode Data

Input Cycle

MODE

t

h3

t

h3

t

su3

XLAT

SIN

t

wh2

GS + 1

MSB

GS n + 1

LSB

GS

MSB

DC

LSB

GS

LSB

t

h1

t

h2

t

su1

t

su2

96

1

192

193

1

192

SCLK

SOUT

t

pd0

SID n + 1

MSB

SID

MSB−1

SID

MSB

SID

LSB

DC

MSB

DC n

LSB

GS

MSB

X

Figure 18. Grayscale Data Input Timing Chart

When the IC is powered on, the data in the input shift register and GS register are not set to any default values.

Therefore, GS data must be written to the GS register before turning on the constant-current output.

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STATUS INFORMATION OUTPUT

The TLC59401 has a status information register, which can be accessed in grayscale mode (MODE = GND).

After the XLAT signal latches the data into the GS register, the input shift register data are replaced with the

status information data (SID) of the device (see Figure 18). LOD, TEF, and dot-correction register data can be

read out at the SOUT pin. The status information data packet is 192 bits wide. Bits 0 to 15 contain the LOD

status of each channel. Bit 16 contains the TEF status. Bits 24 to 119 contain the data of the dot-correction

register. The remaining bits are reserved. The complete status information data packet is shown in Figure 19.

SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown in

Figure 20. The next SCLK pulse, which is the clock for receiving the MSB of the next grayscale data, transmits

MSB-1 of the SID. If the output voltage is less than 0.3 V (typical) when the output sink current turns on, the LOD

status flag becomes active. The LOD status flag is an internal signal that pulls the XERR pin low when the LOD

status flag becomes active. The delay time, t_pd2(1 μs maximum), is the period from the time of turning on the

output sink current to the time the LOD status flag becomes valid. The timing for each channel LOD status to

become valid is shifted by the 30-ns (maximum), channel-to-channel turn-on time. After the first GSCLK goes

high, OUT0 LOD status is valid; t_pd3+ t_pd2= 60 ns + 1 μs = 1.06 μs. OUT1 LOD status is valid; t_pd3+ t_d+ t_pd2

=

60 ns + 30 ns + 1 μs = 1.09 μs. OUT2 LOD status is valid; t_pd3+ (2 × t_d) + t_pd2= 1.12 μs, and so on. It takes 1.51

μs maximum (t_pd3+ (15 × t_d) + t_pd2) from the first GSCLK rising edge until all LOD become valid; t_suLOD must be

greater than 1.51 μs (see Figure 20) to ensure that all LOD data are valid.

MSB

0

LSB

191

15

16

23

X

24

119

120

X

LOD 15

LOD 0

TEF

X

DC 15.5

DC 0.0

X

LOD Data

TEF

DC Values

Reserved

Figure 19. Status Information Data Packet Format

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MODE

GS Data Input Mode

t_suLOD> t_pd3+ t_d´ 15 + t_pd2

t

suLOD

XLAT

SIN

First GS Data Input Cycle

Second GS Data Input Cycle

GS1

MSB

GS2

MSB

GS1

LSB

GS2

LSB

1

192

193

1

SCLK

SOUT

BLANK

GSCLK

GS1

MSB

SID1

MSB MSB-1

GS2

MSB

SID1

LSB

-

(1st GS Data Output Cycle)

4096

1

t

pd3

OUT0

(current)

t

d

OUT1

(current)

15 x t

d

OUT15

(current)

t

pd2

XERR

t

pd3

+ 15 x t + t

d pd2

Figure 20. Readout Status Information Data (SID) Timing Chart

The LOD status of each output can be read out from the SOUT pin. The LOD error bits are latched into the

Status Information Data when XLAT returns to a low after a high. Therefore, the XLAT pin must be pulsed high

then low while XERR is active in order to latch the LOD error into the Status Information Data for subsequent

reading via the serial shift register.

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GRAYSCALE PWM OPERATION

The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low

increases the grayscale counter by one and switches on all OUTn with a grayscale value not equal to zero. Each

following rising edge of GSCLK increases the grayscale counter by one. The TLC59401 compares the grayscale

value of each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the

counter values are switched off. A high BLANK signal after 4096 GSCLK pulses resets the grayscale counter to

zero and completes the grayscale PWM cycle ,as Figure 21 shows. When the counter reaches a count of FFFh,

the counter stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh

immediately resets the counter to zero.

If there are any unconnected outputs (OUTn), including LEDs in a failed short or failed open condition, the GS

data corresponding to the unconnected output should be set to '0' before turning on the LEDs. Otherwise, the

VCC supply current (I_CC) increases while the constant-current output is on.

GS PWM

Cycle n

GS PWM

Cycle n+1

BLANK

GSCLK

t

wl1

t

su4

t

wh1

t

h4

wh3

4096

1

2

3

1

t

wl1

t

pd3

pd1

pd3

OUT0

(Current)

n x t

d

t

+ n x t

pd3 d

t

+ t

d

pd1

OUT1

(Current)

t

OUT15

(Current)

+ 15 x t

d

pd1

t

pd2

XERR

Figure 21. Grayscale PWM Cycle Timing Chart

Output On-Time

The amount of time that each output is turned on is a function of the grayscale clock frequency and the

programmed grayscale PWM value. The on-time of each output can be calculated using Equation 10.

GSn

T _ on_n

=

+ t_{on _ err}

f_(GSCLK)

(10)

where:

T_on_nis the time that OUTn turns on and sinks current

GSn is the OUTn programmed grayscale PWM value between 0 and 4095

t_{on_err}is the output on-time error defined in the Switching Characteristics Table

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When using Equation 10 with very high GSCLK frequencies and very low grayscale PWM values, the resulting

T_on-time may be negative. If T_on is negative, the output does not turn on. For example, using f_(GSCLK)= 30

MHz, GSn = 1, and the typical t_{on_err}= 50 ns, Equation 10 calculates that OUTn turns on for –16.6 ns. This

output may not turn on under these conditions. Increasing the PWM value or reducing the GSCLK clock

frequency ensures turn-on.

SERIAL DATA TRANSFER RATE

Figure 22 shows a cascading connection of n TLC59401 devices connected to a controller, building a basic

module of an LED display system. There is no TLC59401 limitation to the maximum number of ICs that can be

cascaded. The maximum number of cascading TLC59401 devices depends on the application system.

Equation 11 calculates the minimum frequency needed:

f

+ 4096 f

(GSCLK)

+ 193 f

(update)

n

f

(SCLK)

(update)

(11)

where:

f_(GSCLK): minimum frequency needed for GSCLK

f_(SCLK): minimum frequency needed for SCLK and SIN

f_(update): update rate of whole cascading system

n: number cascaded of TLC59401 device

APPLICATION EXAMPLE

V

(LED)

CC

(LED)

100 k

OUT0

OUT15

SOUT

OUT0

OUT15

SOUT

SIN

XERR

SCLK

XERR

SCLK

XLAT

XERR

SCLK

XLAT

V

CC

100 nF

XLAT

TLC59401

GSCLK

MODE

BLANK

SOUT

GSCLK

MODE

BLANK

TEST

GSCLK

MODE

BLANK

TEST

IREF

Controller

V

CC

V

CC

IC 0

IC n

6

Figure 22. Cascading Devices

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PACKAGE OPTION ADDENDUM

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23-Dec-2009

PACKAGING INFORMATION

Orderable Device

TLC59401PWP

TLC59401PWPR

TLC59401RHBR

TLC59401RHBT

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

28

32

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

HTSSOP

QFN

PWP

RHB

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLC59401PWP
厂家：	TEXAS INSTRUMENTS
描述：	16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL 16通道LED驱动器，具有点校正和灰度PWM控制显示驱动器驱动程序和接口接口集成电路光电二极管 PC
文件：	总29页 (文件大小：914K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC59401PWP [TI]

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