TLC5945 [TI]
16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL; 16通道LED驱动器，具有点校正和灰度PWM控制
| 型号： | TLC5945 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL |
| 文件： | 总29页 (文件大小：999K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC5945
PWP
RHB
www.ti.com
SLVS755–MARCH 2007
16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
FEATURES
APPLICATIONS
•
Monocolor, Multicolor, Full-Color LED
Displays
•
•
•
16 Channels
12-bit (4096 Steps) Grayscale PWM Control
Dot Correction
•
•
LED Signboards
Display Back-lighting
–
6 bit (64 Steps)
Drive Capability (Constant-Current Sink)
0 mA to 80 mA
•
DESCRIPTION
–
The TLC5945 is a 16-channel, constant-current sink,
LED driver. Each channel has an individually
adjustable 4096-step grayscale PWM brightness
control and a 64-step constant-current sink (dot
correction). The dot correction adjusts the brightness
variations between LED channels and other LED
drivers. Both grayscale control and dot correction are
accessible via a serial interface. A single external
resistor sets the maximum current value of all 16
channels.
•
•
•
•
•
•
LED Power Supply Voltage up to 17 V
VCC = 3.0 V to 5.5 V
Serial Data Interface
30-MHz Data Transfer Rate
CMOS Level I/O
Error Information
–
–
LOD: LED Open Detection
TEF: Thermal Error Flag
The TLC5945 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature
condition.
VCC
GND
SCLK
SIN
XLAT
CNT
MODE
Constant-Current
Driver
1
0
12−Bit Grayscale
PWM Control
GS Register
OUT0
V
IREF
REF
=1.24
MODE
Max. OUTn
Current
11
5
0
1
0
V
0
DC Register
6−Bit Dot Correction
LED Open Detection
0
GSCLK
BLANK
GS Counter
CNT
Input
Shift
Register
CNT
0
96
Status
Information:
Constant-Current
Driver
12−Bit Grayscale
PWM Control
192
192
GS Register
12
OUT1
23
11
LOD,
TED,
DC DATA
95
96
96
DC Register
6−Bit Dot Correction
LED Open Detection
191
1
0
6
MODE
96
Temperature
LED Open
Detection
(LOD)
CNT
Error Flag
(TEF)
Input
Shift
Register
Constant-Current
Driver
12−Bit Grayscale
PWM Control
GS Register
180
OUT15
191
95
XERR
DC Register
90
6−Bit Dot Correction
LED Open Detection
191
SOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TLC5945
www.ti.com
SLVS755–MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE(1)
PART NUMBER
TLC5945PWP
TLC5945RHB
–40°C to 85°C
–40°C to 85°C
28-pin HTSSOP PowerPAD™
32-pin 5 mm x 5 mm QFN
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS.
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
–0.3 V to 6 V
90 mA
VI
IO
VI
Input voltage range(2)
Output current (dc)
Input voltage range
VCC
V(BLANK), V(SCLK), V(XLAT), V(MODE), V(SIN), V(GSCLK), V(IREF), V(TEST)
V(SOUT), V(XERR)
–0.3 V to VCC +0.3 V
–0.3 V to VCC +0.3 V
–0.3 V to 18 V
2 kV
VO
Output voltage range
V(OUT0) to V(OUT15)
HBM (JEDEC JESD22-A114, Human Body Model)
CDM (JEDEC JESD22-C101, Charged Device Model)
ESD rating
500 V
Tstg
TA
Storage temperature range
–55°C to 150°C
–40°C to 85°C
31.58°C/W
Operating ambient temperature range
HTSSOP (PWP)(4)
QFN (RHB)(4)
Package thermal impedance(3)
35.9°C/W
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) With PowerPAD soldered on PCB with 2-oz. trace of copper. See TI application report SLMA002 for further information.
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SLVS755–MARCH 2007
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Characteristics
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VCC
VO
Supply Voltage
3
5.5
17
V
V
Voltage applied to output (OUT0 - OUT15)
High-level input voltage
VIH
VIL
IOH
IOL
0.8 VCC
GND
VCC
0.2 VCC
–1
V
Low-level input voltage
V
High-level output current
VCC = 5 V at SOUT
mA
mA
mA
°C
Low-level output current
VCC = 5 V at SOUT, XERR
OUT0 to OUT15
1
IOLC
TA
Constant output current
80
Operating free-air temperature range
–40
85
AC Characteristics
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
Data shift clock
frequency
f(SCLK)
SCLK
30
30
MHz
MHz
Grayscale clock
frequency
f(GSCLK)
GSCLK
twh0/twl0
twh1/twl1
twh2
twh3
tsu0
tsu1
tsu2
tsu3
tsu4
tsu5
th0
SCLK pulse duration
GSCLK pulse duration
XLAT pulse duration
BLANK pulse duration
SCLK = H/L (See Figure 6)
16
16
20
20
5
ns
ns
ns
ns
GSCLK = H/L (See Figure 6)
XLAT = H (See Figure 6)
BLANK = H (See Figure 6)
SIN - SCLK↑ (See Figure 6)
SCLK↓ - XLAT↑ (See Figure 6)
MODE↑↓ - SCLK↑ (See Figure 6)
MODE↑↓ - XLAT↑ (See Figure 6)
BLANK↓ - GSCLK↑ (See Figure 6)
XLAT↑ - GSCLK↑ (See Figure 6)
SCLK↑ - SIN (See Figure 6)
10
10
10
10
30
3
Setup time
Hold Time
ns
ns
th1
XLAT↓ - SCLK↑ (See Figure 6)
SCLK↑ - MODE↑↓ (See Figure 6)
XLAT↓ - MODE↑↓ (See Figure 6)
GSCLK↑ - BLANK↑ (See Figure 6)
10
10
10
10
th2
th3
th4
DISSIPATION RATINGS
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
POWER RATING
PACKAGE
TA < 25°C
TA = 70°C
TA = 85°C
28-pin HTSSOP with PowerPAD™
soldered(1)
3958 mW
31.67 mW/°C
2533 mW
2058 mW
28-pin HTSSOP
without PowerPAD™ soldered
2026 mW
3482 mW
16.21 mW/°C
27.86 mW/°C
1296 mW
2228 mW
1053 mW
1811 mW
32-pin QFN(1)
(1) The PowerPAD is soldered to the PCB with a 2-oz. copper trace. See application report SLMA002 for further information.
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SLVS755–MARCH 2007
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = -40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNI
T
VOH
VOL
High-level output
voltage
IOH = –1 mA, SOUT
IOL = 1 mA, SOUT
VCC –0.5
V
Low-level output
voltage
0.5
V
VI = VCC or GND; BLANK, TEST, GSCLK, SCLK, SIN, XLAT pin
VI = GND; MODE pin
–1
–1
1
1
II
Input current
µA
VI = VCC; MODE pin
50
6
No data transfer, all output OFF, VO = 1 V, R(IREF) = 10 kΩ
No data transfer, all output OFF, VO = 1 V, R(IREF) = 1.3 kΩ
Data transfer 30 MHz, all output ON, VO = 1 V, R(IREF) = 1.3 kΩ
Data transfer 30 MHz, all output ON, VO = 1 V, R(IREF) = 640 Ω
0.9
5.2
16
30
61
12
25
60
ICC
Supply current
mA
IO(LC)
Ilkg
Constant output current All output ON, VO = 1 V, R(IREF) = 640 Ω
54
69 mA
Leakage output current All output OFF, VO = 15 V, R(IREF) = 640 Ω , OUT0 to OUT15
0.1 µA
All output ON, VO = 1 V, R(IREF) = 640 Ω, OUT0 to OUT15,
–20°C to 85°C(1)
All output ON, VO = 1 V, R(IREF) = 640 Ω, OUT0 to OUT15(1)
±1
±1
±1
±1
±4
±8
Constant sink current
error
∆IO(LC0)
%
All output ON, VO = 1 V, R(IREF) = 480 Ω, OUT0 to OUT15,
–20°C to 85°C(1)
All output ON, VO = 1 V, R(IREF) = 480 Ω, OUT0 to OUT15(1)
±6
±8
Constant sink current
error
Device to device, averaged current from OUT0 to OUT15,
–2,
0.4
∆IO(LC1)
∆IO(LC2)
±4
±4
±4
±6
%
%
R(IREF) = 1920 Ω (20 mA)(2)
Constant sink current
error
Device to device, averaged current from OUT0 to OUT15,
–2.7,
2
R(IREF) = 480 Ω (80 mA)(2)
All output ON, VO = 1 V, R(IREF) = 640 Ω OUT0 to OUT15,
±1
±1
VCC = 3 V to 5.5 V(3)
%/
V
∆IO(LC3)
Line regulation
All output ON, VO = 1 V, R(IREF) = 480 Ω OUT0 to OUT15,
VCC = 3 V to 5.5 V(3)
All output ON, VO = 1 V to 3 V, R(IREF) = 640 Ω, OUT0 to OUT15(4)
All output ON, VO = 1 V to 3 V, R(IREF) = 480 Ω, OUT0 to OUT15(4)
±2
±2
±6
±8
%/
V
∆IO(LC4)
Load regulation
Thermal error flag
threshold
T(TEF)
V(LED)
V(IREF)
Junction temperature(5)
150
170 °C
LED open detection
threshold
0.3
0.4
V
V
Reference voltage
output
RI(REF) = 640 Ω
1.20
1.24
1.28
(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1.
(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1.
The ideal current is calculated by Equation 3 in Table 1.
(3) The line regulation is calculated by Equation 4 in Table 1.
(4) The load regulation is calculated by Equation 5 in Table 1.
(5) Not tested. Specified by design.
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SLVS755–MARCH 2007
Table 1. Test Parameter Equations
IOUTn - IOUTavg _ 0-15
´100
D(%) =
IOUTavg _ 0-15
(1)
(2)
IOUTavg - IOUT(IDEAL)
D(%) =
´100
IOUT(IDEAL)
æ
ç
ç
ö
÷
÷
1.24V
RIREF
IOUT(IDEAL) = 31.5 ´
è
ø
(3)
(4)
(5)
(IOUTn at VCC = 5.5V) - (IOUTn at VCC = 3.0V)
(IOUTn at VCC = 3.0V)
100
2.5
D(% / V) =
D(%/ V) =
´
(IOUTn at VOUTn = 3.0V) - (IOUTn at VOUTn = 1.0V)
(IOUTn at VOUTn = 1.0V)
100
´
2.0
SWITCHING CHARACTERISTICS
VCC = 3 V to 5.5 V, CL = 15 pF, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tr0
SOUT
16
ns
30
Rise time
tr1
OUTn, VCC = 5 V, TA = 60°C, DCn = 3Fh
SOUT
10
10
tf0
16
ns
30
Fall time
tf1
OUTn, VCC = 5 V, TA = 60°C, DCn = 3Fh
SCLK - SOUT (see Figure 6)
tpd0
tpd1
tpd2
tpd3
tpd4
ton_err
30
60
ns
ns
ns
ns
ns
ns
BLANK - OUTn (see Figure 6)
OUTn - XERR (see Figure 6)
Propagation delay time
Output on-time error
1000
60
GSCLK - OUTn (see Figure 6)
XLAT - IOUT (dot correction) (see Figure 6)
touton– Tgsclk (see Figure 6), GSn = 01h
1000
0
–12
–3
5
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SLVS755–MARCH 2007
DEVICE INFORMATION
RHB PACKAGE
(TOP VIEW)
PWP PACKAGE
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
BLANK
XLAT
VCC
2
3
4
5
6
7
8
9
IREF
TEST
SCLK
SIN
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
MODE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
TEST
25
16 OUT10
15 OUT9
14 OUT8
13 NC
Thermal
PAD
IREF 26
VCC 27
NC 28
THERMAL
PAD
10
11
12
13
14
NC 29
12 NC
GND 30
BLANK 31
11 OUT7
10 OUT6
OUT8
XLAT
32
9
OUT5
NC − No internal connection
TERMINAL FUNCTION
TERMINAL
PWP
I/O
DESCRIPTION
NAME
RHB
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
BLANK
2
31
I
GND
1
30
24
26
G
I
Ground
GSCLK
IREF
25
27
Reference clock for grayscale PWM control
I/O Reference current terminal
No connection
NC
-
12, 13, 28, 29
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
SCLK
SIN
7
4
5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Constant-current output
Serial data shift clock
Serial data input
8
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
4
7
8
9
10
11
14
15
16
17
18
19
20
21
1
5
2
I
6
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SLVS755–MARCH 2007
DEVICE INFORMATION (continued)
TERMINAL FUNCTION (continued)
TERMINAL
I/O
DESCRIPTION
NAME
SOUT
TEST
VCC
PWP
24
RHB
23
O
I
Serial data output
26
25
Test pin: TEST must be connected to VCC.
Power supply voltage.
28
27
I
Input mode-change pin. When MODE = GND, the device is in GS mode. When MODE =
VCC, the device is in DC mode.
MODE
XERR
6
3
I
23
22
O
Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
Level triggered latch signal. When XLAT = high, the TLC5945 writes data from the input shift
register to either GS register (MODE = low) or DC register (MODE = high). When XLAT=low,
the data in the GS or DC registers is held constant and does not change.
XLAT
3
32
I
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SLVS755–MARCH 2007
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Resistor values are equivalent resistance and not tested.
INPUT EQUIVALENT CIRCUIT
OUTPUT EQUIVALENT CIRCUIT (SOUT)
(BLANK, XLAT, SCLK, SIN, GSCLK, TEST)
VCC
23 W
23 W
400 W
INPUT
SOUT
GND
GND
INPUT EQUIVALENT CIRCUIT (IREF)
VCC
OUTPUT EQUIVALENT CIRCUIT (XERR)
23 W
Amp
XERR
_
400 W
+
INPUT
100 W
GND
GND
INPUT EQUIVALENT CIRCUIT (VCC)
OUTPUT EQUIVALENT CIRCUIT (OUT)
OUT
INPUT
GND
GND
INPUT EQUIVALENT CIRCUIT (MODE)
INPUT
GND
Figure 1. Input and Output Equivalent Circuits
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PARAMETER MEASUREMENT INFORMATION (continued)
t
, t , t , t , t
who wIO wh1 wl1 su0
t
t
su4, h4
V
(LED)
= 4 V
SOUT
Test Point
= 15 pF
R
= 51
L
C
L
OUTn
Test Point
= 15 pF
C
L
IOLC, IOLC3, IOLC4
=
V
(LED)
1 V
OUT0
OUTn
V
= 0 V ~ 7 V
_
CC
+
OUT15
IREF
Test Point
= 640
R
IREF
Figure 2. Parameter Measurement Circuits
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Typical Characteristics
REFERENCE RESISTOR
vs
OUTPUT CURRENT
POWER DISSIPATION RATE
vs
FREE-AIR TEMPERATURE
4000
10 k
TLC5945PWP
PowerPAD Soldered
TLC5945RHB
3.84 k
3000
2000
1.92 k
1.28 k
1 k
0.96 k
TLC5945PWP
PowerPAD Unsoldered
0.79 k
0.64 k
0.55 k
0.48 k
1000
0
−40
100
−20
0
20
40
60
80
0
10
20
30
40
50
60
70
80
I
− Output Current − mA
T
A
− Free-Air Temperature − C
O(LC)
Figure 3.
Figure 4.
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
I
= 60 mA
MAX
I
= 30 mA
MAX
I
= 5 mA
MAX
0
0.20.4 0.6 0.8 1 1.21.4 1.61.8 2 2.22.4 2.6 2.8 3
V
O
− Output Voltage − V
Figure 5.
10
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PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5945 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK
signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of
XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of
XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending
on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle.
Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the
grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the
existing grayscale data. Figure 6 shows the timing chart. More than two TLC5945s can be connected in series
by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5945s is shown in Figure 7. The SOUT pin can also be connected to the controller to receive status
information from TLC5945 as shown in Figure 16.
MODE
DC Data Input Mode
GS Data Input Mode
t
t
h3
su3
t
wh2
XLAT
1st GS Data Input Cycle
2nd GS Data Input Cycle
DC
MSB
DC
LSB
GS1
MSB
GS1
GS2
MSB
GS2
LSB
GS3
MSB
SIN
LSB
su1
192
t
t
t
t
t
su2
su0
h1
t
h2
t
wh0
h0
193
1
192
96
1
193
1
1
t
SCLK
SOUT
BLANK
GSCLK
t
pd0
wl0
SID2
MSB-1
GS1
MSB
SID1
SID1
MSB MSB-1
SID2
MSB
DC
-
MSB
GS2
MSB
SID1
LSB
-
-
t
wh3
1st GS Data Output Cycle
2nd GS Data Output Cycle
t
t
t
wh1
su4
h4
t
su5
1
4096
1
t
t
pd3
wl1
T
t
t
gsclk
pd4
pd1
t
pd3
OUT0
(current)
t
t
outon
pd3
OUT1
(current)
OUT15
(current)
t
pd2
XERR
Figure 6. Serial Data Input Timing Chart
SIN(a)
SIN
SIN
SOUT(b)
SOUT
SOUT
TLC5945 (a)
TLC5945 (b)
SCLK, XLAT,
BLANK,
GSCLK,
MODE
Figure 7. Cascading Two TLC5945 Devices
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PRINCIPLES OF OPERATION (continued)
MODE
XLAT
DCb
MSB
DCa
LSB
GSb1
MSB
GSa1
LSB
GSb2
MSB
GSa2
LSB
GSb3
MSB
SIN(a)
385
1
384
384
192
1
385
1
1
SCLK
96X2
192X2
SIDb2
MSB-1
GSb1
MSB
SIDb1
MSB-1
SIDb2
MSB
DCb
MSB
GSb2
MSB
SIDa1
LSB
SIDb1
MSB
-
-
-
SOUT(b)
BLANK
1
4096
1
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
Figure 8. Timing Chart for Two Cascaded TLC5945 Devices
ERROR INFORMATION OUTPUT
The open-drain output XERR is used to report both of the TLC5945 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned
on, and XERR is pulled to GND. Because XERR is an open-drain output, multiple ICs can be ORed together
and pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system
error (see Figure 16).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 2. XERR Truth Table
ERROR CONDITION
TEMPERATURE
ERROR INFORMATION
SIGNALS
OUTn VOLTAGE
Don't Care
TEF
L
LOD
X
BLANK
XERR
TJ < T(TEF)
TJ > T(TEF)
H
L
H
L
L
L
H
Don't Care
H
X
OUTn > V(LED)
OUTn < V(LED)
OUTn > V(LED)
OUTn < V(LED)
L
L
TJ < T(TEF)
L
H
L
H
L
TJ > T(TEF)
H
H
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TEF: THERMAL ERROR FLAG
The TLC5945 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC.
If the junction temperature exceeds the threshold temperature (160°C typical), TEF becomes H and XERR pin
goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes
L and XERR pin becomes high impedance. TEF status can also be read out from the TLC5945 status register.
LOD: LED OPEN DETECTION
The TLC5945 has an LED-open detection circuit that detects broken or disconnected LED's. The LED open
detector pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in
the Status Information Data is only active under the following open LED conditions.
1. OUTn is on and the time tpd2 (1 µs typical) has passed.
2. The voltage of OUTn is < 0.3V (typical)
The LOD status of each output can be also read out from the SOUT pin. See the STATUS INFORMATION
OUTPUT section for details. The LOD error bits are latched into the Status Information Data when XLAT returns
to a low after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to
latch the LOD error into the Status Information Data for subsequent reading via the serial shift register.
OUTPUT ENABLE
All OUTn channels of the TLC5945 can be switched off with one signal. When BLANK is set high, all OUTn
channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When
BLANK is set low, all OUTn channels operate normally. If BLANK goes low and then back high before the
grayscale counter reaches 4095, all outputs turn on for their programmed number of grayscale clocks, or the
length of time the that the BLANK signal was low, whichever is lower. For example, if all outputs are
programmed to turn on for 1 ms, but the BLANK signal is only low for 200 ns, all outputs turn on for 200 ns.
Table 3. BLANK Signal Truth Table
BLANK
LOW
OUT0 - OUT15
Normal condition
Disabled
HIGH
SETTING MAXIMUM CHANNEL CURRENT
The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between
IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of
1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of
31.5. The maximum output current can be calculated by Equation 6:
V
(IREF)
I
+
31.5
max
R
(IREF)
(6)
where:
V(IREF) = 1.24 V
R(IREF) = User-selected external resistor.
Imax must be set between 5 mA and 80 mA. The output current may be unstable if Imax is set lower than 5 mA.
Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot
correction.
Figure 3 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF
terminal to GND, and IO is the constant output current of OUT0 to OUT15. A variable power supply may be
connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum
output current per channel is 31.5 times the current flowing out of the IREF pin.
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POWER DISSIPATION CALCULATION
The device power dissipation needs to be below the power dissipation rate of the device package to ensure
correct operation. Equation 7ǒcaVlculates the power dissipation of device:
Ǔ
DC
n
+ ǒVCC CCǓ)
P
I
I
N
d
D
OUT
MAX
PWM
63
(7)
where:
VCC: device supply voltage
ICC: device supply current
VOUT: TLC5945 OUTn voltage when driving LED current
IMAX: LED current adjusted by R(IREF) Resistor
DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
dPWM: duty cycle defined by BLANK pin or GS PWM value
OPERATING MODES
The TLC5945 has two operating modes defined by MODE as shown in Table 4. The GS and DC registers are
set to random values that are not known just after power on. The GS and DC values must be programmed
before turning on the outputs. Please note that when initially setting GS and DC data after power on, the GS
data must be set before the DC data is set. Failure to set GS data before DC data may result in the first bit of
GS data being lost. XLAT must be low when the MODE pin goes high-to-low or low-to-high to change back and
forth between GS mode and DC mode.
Table 4. TLC5945 Operating Modes Truth Table
MODE
GND
VCC
INPUT SHIFT REGISTER
OPERATING MODE
Grayscale PWM Mode
192 bit
96 bit
Dot Correction Data Input Mode
SETTING DOT CORRECTION
The TLC5945 has the capability to fine-adjust the output current of each channel (OUT0 to OUT15)
independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs
connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit
word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. The
TEST pin must be connected to VCC to ensure proper operation of the dot correction circuitry. Equation 8
determines the output current for each output n:
DCn
63
I
+ I
max
OUTn
where:
(8)
Imax = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63).
n = 0 to 15
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Figure 9 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC
15.5 in Figure 9 stands for the 5th-most significant bit for output 15.
MSB
0
LSB
95
5
6
89
90
DC 15.5
DC 15.0 DC 14.5
DC 1.0
DC 0.5
DC 0.0
DC OUT15
DC OUT0
DC OUT14 − DC OUT1
Figure 9. Dot Correction Data Packet Format
When MODE is set to VCC, the TLC5945 enters the dot correction data input mode. The length of input shift
register becomes 96bits. After all serial data are shifted in, the TLC5945 writes the data in the input shift register
to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a
level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed
while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal
does not need to be high to latch in new data. When XLAT goes high, the new dot-correction data immediately
becomes valid and changes the output currents if BLANK is low. XLAT has setup time (tsu1) and hold time (th1)
to SCLK as shown in Figure 6.
To input data into the dot correction register, MODE must be set to VCC. The internal input shift register is then
set to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dot
correction register. Figure 10 shows the dc data input timing chart.
DC Mode Data
DC Mode Data
Input Cycle n
Input Cycle n+1
V
CC
MODE
SIN
DC n
MSB
DC n
MSB−1
DC n
MSB−2
DC n
LSB+1
DC n
LSB
DC n+1
MSB
DC n+1
MSB−1
DC n−1
LSB
t
wh0
SCLK
1
2
3
95
96
1
2
t
wl0
DC n−1
MSB
DC n−1
MSB−1
DC n−1
MSB−2
DC n−1
LSB+1
DC n−1
LSB
DC n
MSB
DC n
MSB−1
DC n
MSB−2
SOUT
XLAT
t
wh2
t
su1
t
h1
Figure 10. Dot Correction Data Input Timing Chart
SETTING GRAYSCALE
The TLC5945 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits
per channel results in 4096 different brightness steps, from 0% to 100% brightness. Equation 9 determines the
brightness level for each output n:
GSn
4095
Brightness in % +
100
(9)
where:
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
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SLVS755–MARCH 2007
n = 0 to 15
Grayscale data for all OUTn
The input shift register enters grayscale data into the grayscale register for all channels simultaneously. The
complete grayscale data format consists of 16 x 12 bit words, which forms a 192-bit wide data packet (see
Figure 11). The data packet must be clocked in with the MSB first.
MSB
0
LSB
191
11
GS 15.0 GS 14.11
GS OUT15
12
179
180
GS 15.11
GS 1.0 GS 0.11
GS 0.0
GS OUT14 − GS OUT1
GS OUT0
Figure 11. Grayscale Data Packet Format
When MODE is set to GND, the TLC5945 enters the grayscale data input mode. The device switches the input
shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into
the grayscale register (see Figure 12). New grayscale data immediately becomes valid at the rising edge of the
XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is
high. The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal
to complete the grayscale update cycle. All GS data in the input shift register is replaced with status information
data (SID) after updating the grayscale register.
DC Mode Data
Input Cycle
First GS Mode Data
Input Cycle After DC Data Input Cycle
Following GS Mode Data
Input Cycle
MODE
t
h3
t
h3
t
su3
XLAT
SIN
t
wh2
GS + 1
MSB
GS n + 1
LSB
GS
MSB
DC
LSB
GS
LSB
t
h1
t
h2
t
su1
t
su2
96
1
192
193
1
192
SCLK
SOUT
t
pd0
SID n + 1
MSB
SID
MSB−1
SID
MSB
SID
LSB
DC
MSB
DC n
LSB
GS
MSB
X
X
Figure 12. Grayscale Data Input Timing Chart
STATUS INFORMATION OUTPUT
The TLC5945 does have a status information register, which can be accessed in grayscale mode (MODE =
GND). After the XLAT signal latches the data into the GS register, the input shift register data is replaced with
status information data (SID) of the device (see Figure 12). LOD, TEF, and dot-correction register data can be
read out at the SOUT pin. The status information data packet is 192 bits wide. Bits 0 – 15 contain the LOD
status of each channel. Bit 16 contains the TEF status. Bits 24 – 119 contain the data of the dot-correction
register. The remaining bits are reserved. The complete status information data packet is shown in Figure 13.
SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown in
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TLC5945
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SLVS755–MARCH 2007
Figure 14. The next SCLK pulse, which will be the clock for receiving the MSB of the next grayscale data,
transmits MSB-1 of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status
flag becomes active. The LOD status flag is an internal signal which pulls XERR pin down to low when the LOD
status flag becomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink
current to the time LOD status flag becomes valid.
MSB
0
LSB
191
15
16
23
X
24
119
120
X
LOD 15
LOD 0
TEF
X
DC 15.5
DC 0.0
X
LOD Data
TEF
DC Values
Reserved
Figure 13. Status Information Data Packet Format
MODE
GS Data Input Mode
XLAT
SIN
1st GS Data Input Cycle
2nd GS Data Input Cycle
GS1
MSB
GS1
LSB
GS2
MSB
GS2
LSB
> t
+ t
pd3
pd2
t
suLOD
1
192
192
193
1
SCLK
SOUT
BLANK
GSCLK
GS1
MSB
SID1
MSB-1
GS2
MSB
SID1
LSB
SID1
MSB
-
-
(1st GS Data Output Cycle)
4096
1
t
pd3
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
t
t
pd2 + pd3
Figure 14. Readout Status Information Data (SID) Timing Chart
GRAYSCALE PWM OPERATION
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low
increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following
rising edge of GSCLK increases the grayscale counter by one. The TLC5945 compares the grayscale value of
17
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TLC5945
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SLVS755–MARCH 2007
each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values
are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and
completes the grayscale PWM cycle (see Figure 15). When the counter reaches a count of FFFh, the counter
stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets
the counter to zero.
GS PWM
Cycle n
GS PWM
Cycle n+1
BLANK
GSCLK
t
wl1
t
t
su4
t
wh1
1
t
h4
wh3
4096
2
3
1
t
wl1
t
t
t
pd3
pd1
pd3
OUT0
(Current)
t
pd3
OUT1
(Current)
OUT15
(Current)
t
pd2
XERR
Figure 15. Grayscale PWM Cycle Timing Chart
SERIAL DATA TRANSFER RATE
Figure 16 shows a cascading connection of n TLC5945 devices connected to a controller, building a basic
module of an LED display system. There is no TLC5945 limitation to the maximum number of ICs that can be
cascaded. The maximum number of cascading TLC5945 devices depends on the application system and is in
the range of 40 devices. Equation 10 calculates the minimum frequency needed:
f
+ 4096 f
(GSCLK)
+ 193 f
(update)
n
f
(SCLK)
(update)
(10)
where:
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5945 device
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Application Example
V
V
V
V
V
CC
(LED)
(LED)
(LED)
(LED)
100 k
OUT0
OUT15
SOUT
OUT0
OUT15
SOUT
SIN
SIN
SIN
XERR
SCLK
XERR
SCLK
XLAT
GSCLK
XERR
SCLK
XLAT
V
V
CC
CC
100 nF
100 nF
XLAT
TLC5945
TLC5945
GSCLK
MODE
BLANK
TEST
GSCLK
MODE
BLANK
TEST
MODE
IREF
IREF
Controller
V
BLANK
SOUT
CC
V
CC
IC 0
IC n
6
Figure 16. Cascading Devices
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PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
MLA
MLA
MLA
Reel
Diameter Width
(mm)
Reel
A0 (mm)
7.1
B0 (mm)
10.4
K0 (mm)
1.3
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
TLC5945PWPR
TLC5945RHBR
TLC5945RHBT
PWP
RHB
RHB
28
32
32
330
16
12
8
16 PKGORN
T1TR-MS
P
330
177
12
12
5.3
5.3
1.5
12 PKGORN
T2TR-MS
P
5.3
5.3
1.5
8
12 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLC5945PWPR
TLC5945RHBR
TLC5945RHBT
PWP
RHB
RHB
28
32
32
MLA
MLA
MLA
346.0
346.0
190.0
346.0
346.0
212.7
33.0
29.0
31.75
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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