TLC59581 [TI]
具有预充电 FET、LOD Caterpillar 且支持 32 路多路复用的 48 通道 16 位 ESPWM LED 驱动器;
| 型号： | TLC59581 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有预充电 FET、LOD Caterpillar 且支持 32 路多路复用的 48 通道 16 位 ESPWM LED 驱动器 驱动 驱动器 |
| 文件： | 总34页 (文件大小：1495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC59581
ZHCSEA1 –OCTOBER 2015
TLC59581 具有预充电 FET、LOD Caterpillar 消除功能和显示数据存储器
且支持 32 路多路复用的 48 通道 16 位 ES-PWM LED 驱动器
1 特性
3 说明
1
•
•
48 个恒定灌电流输出通道
TLC59581 是一款 48 通道恒定灌电流驱动器。每个通
道都具有单独可调的 65536 步长脉宽调制 (PWM) 灰
度 (GS) 亮度控制。
具有最大亮度控制 (BC)/最大颜色亮度控制 (CC) 数
据的灌电流：
–
–
5 VCC 时为 25mA
输出通道分为三组。各组都具有 512 步长颜色亮度控
制 (CC) 功能。CC 可调节颜色之间的亮度。全部 48
通道的最大电流值可通过 8 步长全局亮度控制 (BC) 功
能设置。BC 调节 LED 驱动器之间的亮度偏差。可通
过一个串行接口端口访问 GS、CC 和 BC 数据。
3.3 VCC 时为 20mA
•
•
全局亮度控制 (BC)：3 位（8 步长）
每个颜色组的颜色亮度控制 (CC)：
9 位（512 步长），分为三组
•
•
•
发光二极管 (LED) 电源电压高达 10V
VCC = 3.0V 至 5.5V
TLC59581 具有一个错误标志：LED 开路检测
(LOD)。该标志可通过串行接口端口读取。为解决开路
LED 引发的此类 caterpillar 问题，TLC59581 器件具
有一个增强型电路。该电路可提供 caterpillar 效应消
除、热关断 (TSD) 和 IREF 电阻短路保护 (ISP) 功能，
以确保较高的系统稳定性。TLC59581 器件还具有节电
模式，可在输出全部关闭后将总流耗降为 0.8mA（典
型值）。TLC59581 器件是一款提升多路复用面板低灰
度显示模式性能的良好解决方案。
恒流精度
–
通道到通道 = ±1%（典型值），±3%（最大
值）
–
器件到器件 = ±1%（典型值），±2%（最大
值）
•
•
•
•
•
•
•
•
数据传输速率：25MHz
灰度时钟频率：33MHz
预充电场效应晶体管 (FET) 可避免重影现象
增强电路可消除 Caterpillar 效应
低灰度增强
请参见应用笔记《使用 TLC59581 构建高密度、高刷
新率多路复用 LED 面板》，SLVA744。
LED 开路检测 (LOD)
器件信息(1)
热关断 (TSD)
运行温度：-40°C 至 85°C
器件型号
TLC59581
封装
封装尺寸（标称值）
VQFN (56)
8.00mm x 8.00mm
2 应用范围
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
•
•
•
采用多路复用系统的 LED视频显示屏
采用多路复用系统的 LED 信号板
高刷新率、高密度的 LED 面板
典型应用电路原理图（以菊花链方式连接的多个 TLC59581）
VLED
SW
COM
n
COM
n
VLED
SW
COM
1
COM
1
VLED
SW
COM
0
COM
0
X
48
X 48
OUTR0
OUTB15
SOUT
OUTR0
OUTB15
SOUT
DATA
SCLK
LAT
SIN
SIN
TLC59581
IC1
VCC
TLC59581
ICn
VCC
SCLK
LAT
SCLK
LAT
VCC
VCC
Controller
GCLK
GCLK
IREF
GCLK
IREF
Thermal
Pad
Thermal
Pad
FLAGS
READ
IREFGND
IREFGND
GND
GND
GND
GND
3
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCZ9
TLC59581
ZHCSEA1 –OCTOBER 2015
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Device Functional Modes........................................ 17
Application and Implementation ........................ 21
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information ................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 12
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 22
12 器件和文档支持 ..................................................... 22
12.1 社区资源................................................................ 22
12.2 相关链接................................................................ 22
12.3 商标....................................................................... 22
12.4 静电放电警告......................................................... 22
12.5 Glossary................................................................ 22
13 机械、封装和可订购信息....................................... 23
7
7.1 Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 12
7.2 Timing Diagrams..................................................... 14
4 修订历史记录
日期
修订版本
注释
2015 年 10 月
*
最初发布版本。
2
Copyright © 2015, Texas Instruments Incorporated
TLC59581
www.ti.com.cn
ZHCSEA1 –OCTOBER 2015
5 Pin Configuration and Functions
RTQ Package with Thermal Pad
56-Pin VQFN
(Top View)
56 55 54 53 52 51 50 49 48 47 46 45 44 43
SOUT
IREF
OUTR14
OUTG14
OUTB14
OUTR15
OUTG15
OUTB15
OUTR0
OUTG0
OUTB0
1
42
41
40
39
38
OUTB9
OUTG9
OUTR9
OUTB8
OUTG8
OUTR8
OUTB7
OUTG7
OUTR7
OUTB6
OUTG6
OUTR6
GCLK
2
3
4
5
6
7
37
36
Thermal
PAD
(Solder side)
(GND terminal)
35
34
33
32
31
30
29
8
9
10
11
12
13
14
OUTR1
OUTG1
OUTB1
OUTR2
15 16 17 18
27 28
19 20 21 22 23 24 25 26
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GCLK
GND
NO.
Grayscale(GS) pulse width modulation (PWM) reference clock control for OUTXn.
Each GCLK rising edge increase the GS counter by 1 for PWM control.
29
I
ThermalPad
–
Power ground. The thermal pad must be soldered to GND on PCB.
Maximum constant-current value setting. The OUTR0 to OUTB15 maximum constant output
current are set to the desired values by connecting an external resistor between IREF and
IREFGND. See (1) for more detail. The external resistor should be placed close to the
device.
IREF
1
–
Analog ground. Dedicated ground pin for the external IREF resistor. This pin should be
connected to analog ground trace which is connected to power ground near the common
GND point of board.
IREFGND
LAT
56
27
–
I
The LAT falling edge latches the data from the common shift register into the GS data
memory or function control (FC) register FC1 or FC2.
(1) The deviation of each output in same color group (OUTR0~15 or OUTG0~15 or OUTB0~15) from the average of same color group
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0~15)
é
ê
ê
ê
ù
ú
IOUTXn
D %
( )
=
-1 ´100
ú
(IOUTX0 + IOUTX1+ ¼+ IOUTX14 + IOUTX15)
16
ú
ê
ë
ú
û
spacer
Copyright © 2015, Texas Instruments Incorporated
3
TLC59581
ZHCSEA1 –OCTOBER 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
8
OUTR0
OUTR1
OUTR2
OUTR3
OUTR4
OUTR5
OUTR6
OUTR7
OUTR8
OUTR9
OUTR10
OUTR11
OUTR12
OUTR13
OUTR14
OUTR15
OUTG0
OUTG1
OUTG2
OUTG3
OUTG4
OUTG5
OUTG6
OUTG7
OUTG8
OUTG9
OUTG10
OUTG11
OUTG12
OUTG13
OUTG14
OUTG15
11
14
17
20
23
30
33
36
39
44
47
50
53
2
Constant current output for RED LED. Multiple outputs can be tied together to increase the
constant current capability. Different voltages can be applied to each output. These outputs
are turned on-off by GCLK signal and the data in GS data memory.
O
5
9
12
15
18
21
24
31
34
37
40
45
48
51
54
3
Constant current output for GREEN LED. Multiple outputs can be tied together to increase
the constant current capability. Different voltages can be applied to each output. These
outputs are turned on-off by GCLK signal and the data in GS data memory.
O
6
4
Copyright © 2015, Texas Instruments Incorporated
TLC59581
www.ti.com.cn
ZHCSEA1 –OCTOBER 2015
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
10
13
16
19
22
25
32
35
38
41
46
49
52
55
4
OUTB0
OUTB1
OUTB2
OUTB3
OUTB4
OUTB5
OUTB6
OUTB7
OUTB8
OUTB9
OUTB10
OUTB11
OUTB12
OUTB13
OUTB14
OUTB15
Constant current output for BLUE LED. Multiple outputs can be tied together to increase the
constant current capability. Different voltages can be applied to each output. These outputs
are turned on-off by GCLK signal and the data in GS data memory.
O
7
Serial data shift clock. Data present on SIN are shifted to the 48-bit common shift register
LSB with the SCLK rising edge. Data in the shift register are shifted towards the MSB at
each SCLK rising edge. The common shift register MSB appears on SOUT.
SCLK
28
26
I
I
Serial data input of the 48-bit common shift register. When SIN is high level, the LSB is set
to '1' for only one SCLK input rising edge. If two SCLK rising edges are input while SIN is
high, then the 48-bit shift register LSB and LSB+1 are set to '1'. When SIN is low, the LSB is
set to '0' at the SCLK input rising edge.
SIN
Serial data output of the 48-bit common shift register. SOUT is connected to the MSB of the
register.
SOUT
VCC
42
43
O
–
Power-supply voltage.
Copyright © 2015, Texas Instruments Incorporated
5
TLC59581
ZHCSEA1 –OCTOBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
MIN
MAX
6.0
UNIT
V
(2)
VCC
Supply voltage
Output current (dc)
Input voltage
VCC
0.3
IOUT
OUTx0 to OUTx15, x = R, G, B
SIN, SCLK, LAT, GCLK, IREF
SOUT
30
mA
(2)
VIN
–0.3
–0.3
–0.3
VCC+0.3
VCC+0.3
11
V
(2)
VOUT
Output voltage
V
OUTx0 to OUTx15, x = R, G, B
TJ(MAX)
TSTG
Operating junction temperature
Storage temperature range
150
°C
°C
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to device ground terminal.
6.2 ESD Ratings
MIN
MAX
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(2)
0
4000
Electrostatic
discharge
(1)
V(ESD)
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(3)
0
1000
(1) Electrostatic discharge (ESD) measures device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
At TA = –40°C to 85°C, unless otherwise noted
MIN
NOM
MAX UNIT
DC CHARACTERISTICS, VCC = 3 V to 5.5 V
VCC
VO
Supply voltage
3
5.5
10
V
V
V
Voltage applied to output
High level input voltage
OUTx0 to OUTx15, x = R, G, B
SIN, SCLK, LAT, GCLK
VIH
0.7 × VCC
GND
VCC
0.3 ×
VCC
VIL
Low level input voltage
SIN, SCLK, LAT, GCLK
V
IOH
IOL
High level output current
Low level output current
SOUT
SOUT
–2
2
mA
mA
OUTx0 to OUTx15, x = R, G, B,
3 V ≤ VCC ≤ 3.6 V
20
25
IOLC
Constant output sink current
mA
OUTx0 to OUTx15, x = R, G, B,
4 V < VCC ≤ 5.5 V
TA
TJ
Operating free air temperature
Operation junction temperature
–40
–40
85
°C
°C
125
6
Copyright © 2015, Texas Instruments Incorporated
TLC59581
www.ti.com.cn
ZHCSEA1 –OCTOBER 2015
Recommended Operating Conditions (continued)
At TA = –40°C to 85°C, unless otherwise noted
MIN
NOM
MAX UNIT
AC CHARACTERISTICS, VCC = 3 V to 5.5 V(1)
FCLK(SCLK)
FCLK(GCLK)
tWH0
Data shift clock frequency
SCLK
25
33
MHz
MHz
Grayscale control clock frequency GCLK
SCLK
10
10
15
10
2
tWL0
SCLK
Pulse duration
GCLK
ns
tWH1
tWL1
GCLK
tSU0
SIN - SCLK↑
tSU1
LAT↑ - SCLK↑
LAT↓ - SCLK↑
3
5
ns
tSU2
LAT↓ - SCLK↑, for READSID,
READFC1, and READFC2
50
Setup time
tSU3
tSU4
LAT↓ (Vsync command) - GCLK↑
2500
The last LAT↓ for no all ‘0’ data latching
to resume normal mode – GCLK↑,
PSAVE_ENA bit = ‘1b’
50
µS
ns
The last GCLK↑ - the 1st GCLK↑ of next
line
tSU5
20
tH0
tH1
tH2
SCLK↑ - SIN
SCLK↑ - LAT↑
SCLK↑ - LAT↓
2
2
Hold time
ns
13
(1) Specified by design
6.4 Thermal Information
TLC59581
THERMAL METRIC(1)
RTQ
56 PINS
27.4
13.6
5.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.5
RθJC(bot)
0.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
7
TLC59581
ZHCSEA1 –OCTOBER 2015
www.ti.com.cn
6.5 Electrical Characteristics
At VCC = 3.0 V to 5.5 V and TA = –40°C to 85°C, VLED = 5.0 V; Typical values are at VCC = 3.3 V, TA = 25°C (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCC
0.4
UNIT
V
VOH
High
Low
IOH = –2 mA at SOUT
IOL= 2 mA at SOUT
LODVTH = 00b
VCC–0.4
Output voltage
VOL
V
VLOD0
VLOD1
VLOD2
VLOD3
VIREF
IIN
0.12
0.32
0.52
0.72
1.19
–1
0.2
0.4
0.28
0.48
0.68
0.88
1.228
1
LODVTH = 01b
LED open detection threshold
V
LODVTH = 10b
0.6
LODVTH = 11b
0.8
Reference voltage output
Input current (SIN, SCLK)
RIREF = 6.2 kΩꢀ(1 mA target), BC = 0h, CCR/G/B = 81h
VIN = VCC or GND
1.209
V
µA
SIN/SCLK/LAT/GSCLK = GND, GSn = 0000h, BC = 0h,
9
11
25
11
ICC0
CCR/G/B = 100h, PCHG_EN = 0, VOUTn = VCC
,
RIREF = OPEN
SIN/SCLK/LAT/GSCK = GND, GSn = 0000h, BC = 4h,
CCR/G/B = 140h,VOUTn Floating, PCHG_EN = 0,
RIREF = 7.5 kΩ (Io = 10 mA target)
13
31
ICC1
SIN/SCLK/LAT = GND, GCLK = 33 MHz, TSU5 = 200 nS,
8+8 mode, GSn = FFFFh, BC = 4h, CCR/G/B = 140h,
VOUTn = 1 V when channel on, VOUTn = VCC
when channel off. PCHG_EN = 0
Supply current (VCC
)
mA
ICC2
SIN/SCLK/LAT = GND, GCLK = 33 MHz, TSU5 = 200 nS,
8+8 mode, GSn = FFFFh, BC = 7h, CCR/G/B = 1FFh,
VOUTn = 1 V when channel on, VOUTn = VCC
when channel off. PCHG_EN = 0
28
33
ICC3
ICC4
In power save mode and PCHG_EN = 1
1
1.4
All OUTn = on, BC = 0h, CCR/G/B = 81h,
±1%
±3%
Constant current error
(OUTx0-15, x = R/G/B)
Channel-to-
channel(1)
VOUTn = VOUTfix = 1 V, RIREF = 6.2 kΩ(1 mA target),
TA = 25°C, at same color grouped output of OUTR0-15,
OUTG0-15 and OUTB0-15
ΔIOLC0
All OUTn = on, BC = 0h, CCR/G/B = 81h,
VOUTn = VOUTfix = 1 V, RIREF = 6.2 kΩ(1 mA target),
TA = 25°C, at same color grouped output of OUTR0-15,
OUTG0-15 and OUTB0-15
±1%
±1
±2%
±1.5
Constant current error
(OUTx0-15, x = R/G/B)
Device-to-
device(2)
ΔIOLC1
VCC = 3.0 to 5.5 V, All OUTn = on, BC = 0h, CCR/G/B = 81h,
VOUTn = VOUTfix = 1 V, RIREF = 6.2 kΩꢀ(1 mA target)
ΔIOLC2
Line regulation(3)
%/V
(1) The deviation of each output in same color group (OUTR0~15 or OUTG0~15 or OUTB0~15) from the average of same color group
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0~15)
é
ê
ê
ê
ù
ú
IOUTXn
D %
( )
=
-1 ´100
ú
(IOUTX0 + IOUTX1+ ¼+ IOUTX14 + IOUTX15)
16
ú
ê
ë
ú
û
spacer
(2) The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) :
é (IOUTX0 + IOUTX1 + ¼ + IOUTX15)
ù
ú
ú
ú
- (Ideal Output Current)
ê
16
D %
( )
=
´100
ê
Ideal Output Current
ê
ê
ë
ú
û
Ideal current is calculated by the following equation:
é
ê
ù
ú
V
IREF
(W)
Ideal Output mA = Gain ´
´ CCR or CCG, CCB /511d, VIREF = 1.209V Typ ,
(
)
(
)
(
)
R
ê
ë
ú
û
IREF
Refer to Table 1 for the Gain at chosen BC.
spacer
(3) Line regulation is calculated by the following equation. (X = R or G or B, n = 0~15):
é
ù
(IOUTXn at VCC = 5.5V) – IOUTXn at VCC = 3.0V
(
)
100
D %V
=
´
ê
ú
(
)
IOUTXn at VCC = 3.0V
5.5V – 3V
(
)
ê
ú
ë
û
spacer
8
Copyright © 2015, Texas Instruments Incorporated
TLC59581
www.ti.com.cn
ZHCSEA1 –OCTOBER 2015
Electrical Characteristics (continued)
At VCC = 3.0 V to 5.5 V and TA = –40°C to 85°C, VLED = 5.0 V; Typical values are at VCC = 3.3 V, TA = 25°C (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All OUTn = on, BC = 0h, CCR/G/B = 81h, VOUTn = 1 to 3 V,
VOUTfix = 1 V, RIREF = 6.2 kΩꢀ(1 mA target)
ΔIOLC3
Load regulation(4)
±1
±1.5
%/V
All OUTn = on, BC = 7h, CCR/G/B = 1F7h, VOUTn =
VOUTfix = 1 V,
RIREF = 7.5 kΩ(25 mA target), TA = 25°C, at same color
Channel-to-
channel(1)
Constant current error
(OUTx0-15, x = R/G/B)
ΔIOLC4
±1%
±1%
±3%
grouped output of OUTR0-15, OUTG0-15 & OUTB0-15
All OUTn = on, BC = 7h, CCR/G/B = 1F7h, VOUTn =
VOUTfix = 1 V,
RIREF = 7.5 kΩ(25 mA target), TA = 25°C, at same color
Device-to-
device(2)
Constant current error
(OUTx0-15, x = R/G/B)
ΔIOLC5
±2%
±1.5
grouped output of OUTR0-15, OUTG0-15 and OUTB0-15
VCC = 3.0 to 5.5 V, All OUTn = on, BC = 7h, CCR/G/B =
1F7h,
VOUTn = VOUTfix = 1 V, RIREF = 7.5 kΩꢀ(25 mA target)
ΔIOLC6
Line regulation(3)
Load regulation(4)
±1
±1
%/V
%/V
All OUTn = on, BC = 7h, CCR/G/B = 1F7h, VOUTn = 1 to 3
V,
VOUTfix = 1 V, RIREF = 7.5 kΩꢀ(25 mA target)
ΔIOLC7
±1.5
180
TTSD
Thermal shutdown threshold(5)
Thermal shutdown hysterisis
160
170
10
°C
°C
V
THYS
VISP(in)
IREF resistor short protection threshold
0.15
0.195
IREF resistor short-protection release
threshold
V
VISP(out)
0.325
0.4
RPDWN
RPUP
Pull-down resistor
Pull-up resistor
LAT
250
250
500
500
750
750
kΩ
kΩ
V
GCLK
All OUTn = on, BC = 4h, CCR/G/B = 137h, RIREF = 7.5 kΩ.
(Io = 10 mA target)
0.32
0.35
(5)
Vknee
Knee voltage (OUTX 0~15), X = R/G/B
(4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0~15):
é
ê
ë
ù
ú
û
(IOUTXn at VOUTXn = 3V) – IOUTXn at VOUTXn = 1V
(
)
100
D %V
(
=
´
)
IOUTXn at VOUTXn = 1V
3V – 1V
(
)
ê
ú
spacer
(5) Specified by design.
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6.6 Typical Characteristics
VCC = 3.3 V and TA = 25°C, unless otherwise noted.
35
35
30
25
20
15
10
5
1 mA
1 mA
5 mA
10 mA
20 mA
25 mA
5 mA
30
25
20
15
10
5
10 mA
20 mA
0
0
0.0
0.5
1.0
Output Voltage (V)
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Output Voltage (V)
C001
C002
VCC = 5 V
CCR/G/B = 1FFh, BC = 0
VCC = 3.3 V
CCR/G/B = 1FFh, BC = 0
Figure 1. Output Current vs Output Voltage
Figure 2. Output Current vs Output Voltage
12
10
8
3
2
1
6
0
4
œ1
œ2
œ3
VCC = 3.3 V Min
T
T
T
= œ40°C
A
V=3.3 V Max
CC
2
= 25°C
A
V
= 5 V Min
CC
= 85°C
V
= 5 V Max
A
CC
0
0.0
0.2
0.4
0.6
0.8
1.0
0
5
10
15
20
25
30
Output Voltage (V)
Output Current (mA)
C003
C004
VCC = 5 V
Temperature
Changing
CCR/G/B = 1FFh,
BC = 0
VOUTXn = 0.8 V
CCR/G/B = 1FFh, BC = 0
Figure 4. Constant Current Error (CH-to-CH) vs Output
Current
Figure 3. Output Current vs Output Voltage
3
2
30
1 mA
5 mA
25
10 mA
1
20
20 mA
25 mA
15
0
œ1
œ2
œ3
10
5
1 mA Min
1 mA Max
25 mA Min
25 mA Max
0
0
20
40
60
80
œ40
œ20
0
128
256
384
512
Ambient Temperature (°C)
Color Control Data (Decimal)
C005
C006
VCC = 5 V
VOUTXn = 0.8 V
CCR/G/B = 1FFh,
BC = 0
VCC = 5 V
VOUTXn = 0.8 V
BC = 7
Figure 6. Color Control (CC) vs Output Current
Figure 5. Constant-Current Error (CH-to-CH) vs Temperature
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Typical Characteristics (continued)
VCC = 3.3 V and TA = 25°C, unless otherwise noted.
30
35
30
25
20
15
10
5
1 mA
5 mA
25
10 mA
20
20 mA
25 mA
15
10
5
VCC=3.3V
VCC=5V
0
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
Brightness Control Data (Decimal)
Output Current (mA)
C007
C008
VCC = 5 V
VOUTXn = 0.8 V
CCR/G/B = 1FFh
VOUTXn = 0.8 V
GCLK = 33 MHz,
GSXn = FFFFh
CCR/G/B = 1FFh,
BC = 0
Figure 7. Brightness Control (BC) vs Output Current
Figure 8. Supply Current (Icc) vs Output Current
30
25
20
15
10
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
V
V
= 3 V
V
= 3 V
CC
CC
5
0
= 4 V
V
= 4 V
CC
CC
= 5.5 V
V
= 5.5 V
CC
CC
0
20
40
60
80
100
120
0
20
40
60
80
100
120
œ40
œ20
œ40
œ20
Ambient Temperature (°C)
Ambient Temperature (°C)
C009
C010
VOUTXn = 0.8 V
CCR/G/B = 137h,
BC = 4, GCLK = 33
MHz
GSXn = FFFFh,
RIREF = 7.5 kΩ (10-
mA target)
VOUTXn = 0.8 V
CCR/G/B = 137h,
BC = 4
GCLK = GND,
GSXn = 0h
Figure 10. Supply Current in Power Save Mode (Icc)
vs Temperature
Figure 9. Supply Current (Icc) vs Temperature
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7 Parameter Measurement Information
7.1 Pin Equivalent Input and Output Schematic Diagrams
VCC
VCC
LAT
INPUT
GND
GND
Figure 11. SIN, SCLK
Figure 12. LAT
VCC
VCC
GCLK
OUTPUT
GND
GND
Figure 13. GCLK
Figure 14. SOUT
(1) X = R or G or B, n = 0~15
OUTXn(1)
GND
Figure 15. OUTR0/G0/B0 Through OUTR15/G15/B15
12
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Pin Equivalent Input and Output Schematic Diagrams (continued)
7.1.1 Test Circuits
(1) CL includes measurement probe and jig capacitance.
(2) X = R or G or B, n = 0~15
(1) CL includes measurement probe and jig capacitance.
RL
VCC
VCC
VLED
VCC
VCC
OUTXn(2)
GND
SOUT
CL(1)
CL(1)
GND
Figure 16. Rise and Fall Time Test Circuit for
OUTXn
Figure 17. Rise and Fall Time Test Circuit for SOUT
(1) X = R or G or B, n = 0~15
V
OUTR0
CC
V
CC
OUTXn(1)
OUTB15
VOUTXn(1)
GND
VOUTfix
Figure 18. Constant Current Test Circuit for OUTXn
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7.2 Timing Diagrams
tWH0, WL0, WH1,tWL1,tWH2
t
t
INPUT
50%
GND
tWH
tWL
tSU0, SU1, SU2, SU3, SU4,tH0,tH1,tH2
t
t
t
t
CLOCK
INPUT(1)
50%
GND
tH
tSU
VCC
DATA/CONTROL
INPUT(1)
50%
GND
tSU5
GCLK(2)
1
2
3
255 256 257
1
2
255 256 257
TSU
(1) Input pulse rise and fall time is 1~3ns
(2) 8 + 8 mode (SEL_PWM = 0)
Figure 19. Timing Diagrams
14
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8 Detailed Description
8.1 Overview
The TLC59581 device is a 48-channel constant-current sink driver for multiplexing system with 1 to 32 duty ratio.
Each channel has an individually-adjustable, 65536-step, pulse width modulation (PWM) grayscale (GS).
48-kbit display memory is implemented to increase the visual refresh rate and to decrease the GS data writing
frequency.
The TLC59581 device's support output current ranges from 1 mA to 25 mA; channel-to-channel accuracy is 3%
max, and device-to-device accuracy is 2% max in all current range. The device also implements Low Gray Scale
Enhancement (LGSE) technology to improve the display quality at low grayscale condition. These features make
the TLC59581 device more suitable for high-density multiplexing application.
The output channels are divided into three groups. Each group has a 512-step color brightness control (CC). CC
adjusts brightness control between colors. The maximum current value of all 48 channels can be set by 8-step
global brightness control (BC). BC adjusts brightness deviation between LED drivers. GS, CC and BC data are
accessible through a serial interface port.
The TLC59581 device has one error flag: the LED open detection (LOD), which can be read through a serial
interface port. The TLC59581 device has an enhanced circuit to resolve this caterpillar issue caused by an open
LED. Thermal shut down (TSD) and IREF resistor short protection (ISP) ensure a higher system reliability. The
TLC59581 device also has a power-save mode that sets the total current consumption to 0.8 mA (typical) when
all outputs are off.
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8.2 Functional Block Diagram
OUTG0
OUTB0
OUTR1
OUTB15
OUTG15
OUTR0
VCC
VCC
LED Open Detection (LOD)
48
30
IREF
Reference
current
control
48-CH Constant Current Sink
3-bit BC and 27-bit CC
Detection
Voltage
IREFGND
48
1
Programmable Group delay
2
48
GS Counter
Line read counter and
Sub-period counter
ES-PWM Decoder and
timing control for 48CH
Vsync
48
BANK_SEL
Vsync
Line address
for read
48kbit SRAM
BANK A
16-bit x48CH 16-bit x48CH
x 32Line
x 32Line
BANK B
48
Address
decoder and
writing control
WRTGS
Vsync
44-bit FC1 register
44-bit FC2 register
WRTFC
LAT
Command
Decoder
SCLK
43
LSB
MSB
READFC1/2
48-bit Common shift register
SOUT
SIN
READSID
0
47
48
Power
save
control
To all
analog
circuit
48-bitLOD data
Thermal
Pad
GND
16
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8.3 Device Functional Modes
After power on, all OUTXn of the TLC59581 device are turned off. All the internal counters and function control
registers (FC1/FC2) are initialized. The following list is a brief summary of the sequence to operate the
TLC59581 driver that gives users a general idea of how the device works. The function block related to each
step is detailed in subsequent sections.
1. According to required LED current, choose BC & CC code, select the current-programming resistor RIREF
2. Send WRTFC command to set FC1/2 register value if the default value need be changed.
3. Write GS data of all lines (max 32 lines) into one of the two memory BANKs.
.
4. Send Vsync command, the BANK with the GS data written just now will be displayed.
5. Input GCLK continuously, 257GCLK (or 129GCLK) as a segment. Between the interval of two segments,
supply voltage should be switched from one line to next line accordingly.
6. During the same period of step 5, GS data for next frame should be written into another BANK.
7. When the time of one frame ends, Vsync command should be input to swap the purpose of the two BANKs.
Repeat step 5 through 7.
8.3.1 Brightness Control (BC) Function
The TLC59581 device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit word,
thus all output currents can be adjusted in 8 steps from 12.9% to 100% for a given current-programming resistor,
RIREF (See Table 2).
BC data can be set through the serial interface. When the BC data changes, the output current also changes
immediately. When the device is powered on, the BC data in the function control (FC) register FC1 is set to 4h
as the initial value.
8.3.2 Color Brightness Control (CC) Function
The TLC59581 device is able to adjust the output current of each of the three color groups OUTR0-OUTR15,
OUTG0-OUTG15, and OUTB0-OUTB15 separately. This function is called color brightness control (CC). For
each color, it has 9-bit data latch CCR, CCG, or CCB in FC1 register. Thus, all color group output currents can
be adjusted in 512 steps from 0% to 100% of the maximum output current, IOLCMax. (See the next section for
more detail about IOLCMax). The CC data are entered through the serial interface. When the CC data change, the
output current also changes immediately.
When the IC is powered on, the CC data are set to ‘100h’. Equation 1 calculates the actual output current.
Iout(mA) = IOLCMax(mA) × ( CCR/511d or CCG/511d or CCB/511d)
where
•
•
IOLCMax = the maximum channel current for each channel, determined by BC data and RIREF (see Equation 2)
CCR/G/B = the color brightness control value for each color group in the FC1 register (000h to 1FFh)
(1)
Table 1 shows the CC data versus the constant-current against IOLCMax
:
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Device Functional Modes (continued)
Table 1. CC Data vs Current Ratio and Set Current Value
RATIO OF OUTPUT
CURRENT TO
CC DATA (CCR or CCG or CCB)
OUTPUT CURRENT (mA, RIREF = 7.41 kΩ)
IOLCMax(%, typical)
BC = 7 h
(IOLCMax = 25 mA)
BC = 0 h
(IOLCMax = 3.2 mA)
BINARY
DECIMAL
HEX
0 0000 0000
0 0000 0001
0 0000 0010
---
0
1
00
01
02
---
0
0
0
0.2
0.4
---
0.05
0.10
---
0.006
0.013
---
2
---
1 0000 0000
(Default)
256
(Default)
100
(Default)
50.1
12.52
1.621
---
---
---
---
---
---
1 1111 1101
1 1111 1110
1 1111 1111
509
510
511
1FD
1FE
1FF
99.6
99.8
100.0
24.90
24.95
25
3.222
3.229
3.235
8.3.3 Select RIREF For a Given BC
The maximum output current per channel, IOLCMax, is determined by resistor RIREF, placed between the IREF and
IREFGND pins, and the BC code in FC1 register. The voltage on IREF is typically 1.209 V. RIREF can be
calculated by Equation 2.
RIREF(kΩ) = VIREF(V) / IOLCMax(mA) × Gain
where
•
•
•
VIREF = the internal reference voltage on IREF (1.209 V, typical)
IOLCMax = the largest current for each output at CCR/G/B = 1FFh.
Gain = the current gain at a selected BC code (See Table 2 )
(2)
Table 2. Current Gain Versus BC Code
BC DATA
RATIO OF
GAIN
GAIN / GAIN_MAX (AT MAX
BC)
BINARY
HEX
000 (recommend)
0 (recommend)
20.4
40.3
12.9%
25.6%
52.4%
12.9%
64.7%
73.3%
91.7%
100%
001
010
1
2
59.7
011
3
82.4
100 (default)
101
4 (default)
101.8
115.4
144.3
157.4
5
6
7
110
111
NOTE: Recommend using a smaller BC code for better performance. For noise immunity purposes, suggest RIREF < 60 kΩ
8.3.4 Choosing BC/CC For a Different Application
BC is mainly used for global brightness adjustment between day and night. Suggested BC is 4h, which is in the
middle of the range, allowing flexible changes in brightness up and down.
CC can be used to fine tune the brightness in 512 steps, this is suitable for white balance adjustment between
RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio of R, G, B
LED is 3:6:1. Depending on the characteristics of the LED (Electro-Optical conversion efficiency), the current
ratio of R, G, B LED will be much different from this ratio. Usually, the Red LED needs the largest current.
Choose 511d (the max value) CC code for the color group that needs the largest initial current, then choose
proper CC code for the other two color groups according to the current ratio requirement of the LED used.
18
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8.3.4.1 Example 1: Red LED Current is 20 mA, Green LED Needs 12 mA, Blue LED needs 8 mA
1. Red LED needs the largest current; choose 511d for CCR
2. 511 x 12 mA / 20 mA = 306.6; choose 307d for CCG. With same method, choose 204d for CCB.
3. According to the required red LED current, choose 7h for BC.
4. According to Equation 2, RIREF = 1.209 V/20 mA x 157.4 = 9.5 kΩ
In this example, choose 7h for BC instead of using the default 4h. This is because the Red LED current is 20
mA, approaching the upper limit of current range. To prevent the constant output current from exceeding the
upper limit in case a larger BC code is input accidently, choose the maximum BC code here.
8.3.4.2 Example 2: Red LED Current is 5 mA, Green LED Needs 2 mA, Blue LED Needs 1 mA.
1. Red LED needs the largest current; choose 511d for CCR.
2. 511 x 2 mA / 5 mA = 204.4; choose 204d for CCG. With same method, choose 102d for CCB.
3. According to the required blue LED current, choose 0h for BC.
4. According to Equation 2, RIREF = 1.209 V / 5 mA x 20.4 = 4.93 kΩ
In this example, choose 0h for BC, instead of using the default 4h. This is because the Blue LED current is 1 mA,
is approaching the lower limit of current range. To prevent the constant output current from exceeding the lower
limit in case a lower BC code is input accidently, choose the minimum BC code here. In general, if LED current is
in the middle of the range (i.e, 10 mA), use the default 4h as BC code.
8.3.5 LED Open Detection (LOD)
The LOD function detects faults caused by an open circuit in any LED string; or, a short from OUTXn to ground
with low impedance. It does this by comparing the OUTXn voltage to the LOD detection threshold voltage level
set by LODVLT in the FC1 register. If the OUTXn voltage is lower than the programmed voltage, the
corresponding output LOD bit is set to '1' to indicate an open LED. Otherwise, the output of that LOD bit is '0'.
LOD data output by the detection circuit are valid only during the ‘on’ period of that OUTXn output channel. The
LOD data are always ‘0’ for outputs that are turned off.
8.3.6 Internal Circuit for Caterpillar Removal
Caterpillar effect is a common issue for the LED panel. It is usually caused by LED lamp open, LED lamp
leakage or LED lamp short. The TLC59581 device implements an internal circuit that can eliminate the caterpillar
issue caused by LED open. The caterpillar removal function is enabled by setting LOD_MMC_EN (bit4 of FC1
register) to ‘1’. When powered on, the default value of this bit is ‘0’. When this function is enabled, the IC
automatically detects the open LED lamp, and the lamp does not turn on until IC reset.
8.3.7 Power Save Mode (PSM)
The power-save mode (PSM) is enabled by setting PSAVE_ENA (bit5 of FC2 register) to ‘1’. At power on, this bit
default is ‘0’.
When this function is enabled, if the GS data received for the next frame is all ‘0’, the IC enters power-save
mode immediately.
When the IC is in power-save mode, it resumes normal mode when it detects non-zero GS data input. In power-
save mode all analog circuits such as constant current output and the LOD circuit are not operational; the device
total current consumption, ICC, is below 1 mA.
8.3.8 Internal Pre-Charge FET
The internal pre-charge FET can prevent ghosting of multiplexed LED modules. One cause of this phenomenon
is the charging current for parasitic capacitance of the OUTXn through the LED when the supply voltage switches
from one common line to the next common line.
To prevent this unwanted charging current, the TLC59581 device uses an internal FET to pull OUTXn up to VCC
–1.4 V during the common line switching period. As a result, no charging current flows through LED and ghosting
is eliminated.
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8.3.9 Thermal Shutdown (TSD)
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)
exceeds 170°C (typical). It resumes normal operation when TJ falls below 160°C (typical).
8.3.10 IREF Resistor Short Protection (ISP)
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing though the
constant-current output when the IREF resistor is shorted accidently. The TLC59581 device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the TLC59581 device resumes normal operation.
20
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
See application note: Build High Density, High Refresh Rate, Multiplexing LED Panel with TLC59581, SLVA744
available on ti.com
10 Power Supply Recommendations
Decouple the VCC power supply voltage by placing a 0.1-µF ceramic capacitor close to VCC pin and GND plane.
Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed to get a
well regulated LED supply voltage (VLED). VLED voltage ripple must be less than 5% of its nominal value.
Furthermore, set the VLED voltage as calculated by equation:
VLED > Vf + 0.4 V (10 mA constant current example)
where
•
Vf = maximum forward voltage of LED
(3)
11 Layout
11.1 Layout Guidelines
1. Place the decoupling capacitor near the VCC pin and GND plane.
2. Place the current programming resistor RIREF close to IREF pin and IREFGND pin.
3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is
approximately 1.2 A.
4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as
possible to reduce wire inductance.
5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally,
there will be large current flow through this pad when all channels turn on. Furthermore, this pad should be
connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via
pattern is shown as below. For more information about suggested thermal via pattern and via size, see
PowerPAD Thermally Enhanced Package, SLMA002G.
6. MOSFETS must be placed in the in the middle of the board, which should be laid out as symmetrically as
possible.
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11.2 Layout Example
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 相关链接
1. 应用报告《PowerPAD 耐热增强型封装》，SLMA002G
2. 应用报告《半导体和 IC 封装热指标》，SPRA953
3. 应用报告《使用 TLC59581 构建高密度、高刷新率多路复用 LED 面板》，SLVA744
12.3 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
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13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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重要声明
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC59581RTQR
TLC59581RTQT
ACTIVE
ACTIVE
QFN
QFN
RTQ
RTQ
56
56
2000 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
250 RoHS & Green NIPDAU | NIPDAUAG Level-3-260C-168 HR
-40 to 85
-40 to 85
TLC59581AB
TLC59581AB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RTQ 56
8 x 8, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224653/A
www.ti.com
PACKAGE OUTLINE
RTQ0056E
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
8.15
7.85
A
B
PIN 1 INDEX AREA
8.15
7.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 6.5
5.7 0.1
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
28
15
14
29
SYMM
57
2X 6.5
5.7 0.1
1
42
52X 0.5
PIN 1 ID
0.30
0.18
56
43
56X
0.5
0.3
0.1
C A B
56X
0.05
4224191/A 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTQ0056E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(5.7)
(2.6) TYP
SEE SOLDER MASK
DETAIL
43
(1.35) TYP
56X (0.6)
56X (0.24)
56
1
42
52X (0.5)
(2.6) TYP
(R0.05) TYP
(1.35) TYP
57
SYMM
(7.8)
(5.7)
(
0.2) TYP
VIA
14
29
28
15
SYMM
(7.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224191/A 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTQ0056E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.675) TYP
(1.35) TYP
43
56X (0.6)
56X (0.24)
56
1
42
52X (0.5)
(1.35) TYP
(R0.05) TYP
57
(0.675) TYP
(7.8)
SYMM
16X (1.15)
14
29
15
28
SYMM
16X (1.15)
(7.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 57
65% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224191/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
8.15
7.85
A
B
8.15
7.85
PIN 1 INDEX AREA
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
5.6±0.1
(0.2) TYP
15
28
52X 0.5
14
29
57
4X
6.5
SYMM
5.6±0.1
1
42
0.30
0.18
56X
PIN 1 ID
(OPTIONAL)
43
56
0.1
C A B
C
0.5
0.3
56X
SYMM
0.05
4225369 / A 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
(0.78)
(5.6)
8X (1.33)
6X (1.22)
43
56X (0.6)
56
1
42
56X (0.24)
6X (1.22)
8X (1.33)
52X (0.5)
SYMM
(7.8)
(5.6)
57
(R0.05)
TYP
14
29
(Ø0.2) TYP
VIA
15
28
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225369 / A 10/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. it is recommended thar vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
(7.8)
8X (0.665)
8X (1.33)
43
56X (0.6)
56
56X (0.24)
1
42
57
8X (1.33)
52X (0.5)
SYMM
(7.8)
8X (0.665)
(R0.05) TYP
16X
(
1.13)
14
29
METAL
TYP
15
28
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
66% PRINTED COVERAGE BY AREA
SCALE: 10X
4225369 / A 10/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
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所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
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TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
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