TLC6946 [TI]
支持 32 路多路复用的 16 通道 16 位 ES-PWM 恒流 LED 驱动器;
| 型号： | TLC6946 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持 32 路多路复用的 16 通道 16 位 ES-PWM 恒流 LED 驱动器 驱动 驱动器 |
| 文件： | 总35页 (文件大小：2788K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC6946, TLC6948
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
TLC694x 16 通道 32/48 路复用 16 位 ES-PWM 恒定电流 LED 驱动器
1 特性
•
智能省电模式
1
•
电源电压范围
2 应用
–
–
V
CC 电压范围：3V 至 5.5V
•
•
•
单色、多色、全色 LED 显示
VLED 电压范围：高达 VCC + 0.3V
高刷新率 LED 视频显示
•
16 个恒定电流阱通道
高密度、小间距 LED 矩阵显示
–
–
–
–
0.3mA 至 25mA (3V ≤ VCC ≤ 5.5V)
通道电流偏差：±1%（典型值）
器件电流偏差：±1%（典型值）
膝点电压低：10mA 时为 0.3V（典型值）
3 说明
在高密度、小间距 LED 面板 应用中，人们对多通道
LED 驱动器的性能要求在不断提高，以期实现高多路
复用、高 PWM 分辨率和高刷新率。为了满足严格的
显示质量要求，LED 驱动器必须能够解决不同 LED 矩
阵应用场景中的各种问题。
•
•
•
7 位（128 级）全局亮度控制功能 (BC)
16 位（65,536 级）增强频谱 PWM 灰度控制
内置存储器支持 TLC6946 32 路复用，支持
TLC6948 48 路复用
TLC694x 器件是一款 16 通道、恒定电流阱 LED 驱动
器。每个通道都有独立可调的 65,536 级 PWM 灰度控
制。所有 16 个通道的最大恒定电流值由一个具有 128
级全局亮度控制的外部电阻设置，电流范围为 0.3mA
至 25mA。
•
•
•
增强的 LED 显示性能
–
–
–
改善了低灰度均匀性
低灰度耦合问题消除
去除了重影和毛虫问题
高速串行数据接口
–
–
–
数据移位时钟：33MHz（最大值）
灰度控制时钟：33MHz（最大值）
支持双边灰度控制
器件信息(1)
器件型号
TLC6946
封装
SSOP (24)
封装尺寸（标称值）
8.65mm × 3.90mm
4.00mm x 4.00mm
8.65mm × 3.90mm
4.00mm × 4.00mm
诊断和保护
VQFN (24)
SSOP (24)
VQFN (24)
–
–
–
LED 开路检测 (LOD)
TLC6948
IREF 电阻器短路保护 (ISP)
热关断 (TSD)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
T48 路多路复用 LC6948典型应用原理图
VLED
Line 0
ꢀ
ꢀ
ꢀ
VLED
Line n
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
VLED
Line 47
ꢀ
OUT0
SIN
ꢀ
OUT15
SOUT
OUT0
SIN
ꢀ
OUT15
SOUT
OUT0
SIN
ꢀ
OUT15
SOUT
DATA
SCLK
VCC
VCC
VCC
SCLK TLC6948
SCLK TLC6948
SCLK TLC6948
LAT
VCC
GND
VCC
GND
VCC
GND
Controller
LAT
LAT
LAT
IC1
IC2
IC3
GSCLK
DATA BACK
GCLK
IREF
GCLK
IREF
GCLK
IREF
RIREF
RIREF
RIREF
3
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEB3
TLC6946, TLC6948
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
www.ti.com.cn
目录
9.2 Functional Block Diagram ....................................... 15
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 18
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ............................................... 19
11 Power Supply Recommendations ..................... 22
12 Layout................................................................... 22
12.1 Layout Guidelines ................................................. 22
12.2 Layout Examples................................................... 23
13 器件和文档支持 ..................................................... 25
13.1 文档支持................................................................ 25
13.2 相关链接................................................................ 25
13.3 接收文档更新通知 ................................................. 25
13.4 社区资源................................................................ 25
13.5 商标....................................................................... 25
13.6 静电放电警告......................................................... 25
13.7 术语表 ................................................................... 25
14 机械、封装和可订购信息....................................... 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 7
7.6 Switching Characteristics.......................................... 9
7.7 Typical Characteristics............................................ 11
Parameter Measurement Information ................ 13
8
9
8.1 Pin Equivalent Input and Output Schematic
Diagrams.................................................................. 13
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
4 修订历史记录
Changes from Original (June 2018) to Revision A
Page
•
首次发布生产数据数据表 ....................................................................................................................................................... 1
2
版权 © 2018–2019, Texas Instruments Incorporated
TLC6946, TLC6948
www.ti.com.cn
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
5 说明 （续）
TLC694x 器件集成了增强型电路来解决小间距 LED 显示应用中的 各种显示问题：低灰度均匀性问题、耦合问题、
重影问题和卡特彼勒问题。
TLC694x 器件 具有 LED 开路检测功能，错误检测结果可以通过串行数据接口读取。热关断和 IREF 电阻短路保护
可确保实现更高的系统可靠性。TLC694x 器件还具有智能省电模式，可以在所有输出关断的情况下将总电流消耗设
置为 1mA（典型值）。
Copyright © 2018–2019, Texas Instruments Incorporated
3
TLC6946, TLC6948
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
www.ti.com.cn
6 Pin Configuration and Functions
DBQ Package
24-Pin SSOP
Top View
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
GND
SIN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
2
IREF
SCLK
LAT
3
SOUT
GCLK
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
4
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
1
2
3
4
5
6
18
17
16
15
14
13
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
5
6
Thermal
Pad
7
8
9
10
11
12
Not to scale
Not to scale
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DBQ
21
RGE
20
Grayscale (GS) pulse-width modulation (PWM) reference-clock-signal input pin. In the
default operating mode, each GCLK rising edge increments the GS counter for PWM
control. GCLK supports dual-edge operation.
GCLK
GND
I
1
10
—
Power-ground reference
Pin for setting the maximum constant-current value. Connecting an external resistor
between IREF and GND sets the maximum current for each constant-current output
channel. When this pin is connected directly to GND, all outputs are forced off. The
external resistor should be placed close to the device.
IREF
LAT
23
4
21
1
I
I
Data latch pin. The falling edge of LAT latches the data from the common shift register
into the GS data memory or the function control register.
4
Copyright © 2018–2019, Texas Instruments Incorporated
TLC6946, TLC6948
www.ti.com.cn
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
Pin Functions (continued)
PIN
NO.
I/O
DESCRIPTION
NAME
DBQ
5
RGE
2
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
6
3
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
7
8
9
Constant-current output. Each output can be tied together with others to increase the
constant current. A different voltage can be applied to each output.
11
12
13
14
15
16
17
18
Clock-signal input pin. Serial data present on SIN are shifted to the LSB of the internal
16-bit common shift register on the SCLK rising edge. All data in the shift register are
shifted toward the MSB of the internal 16-bit common shift register on each SCLK rising
edge.
SCLK
SIN
3
2
24
23
I
I
Serial-data input pin of the internal 16-bit common shift register. When SIN is high, the
LSB of the internal 16-bit common shift register is set to 1 on the SCLK input rising
edge. When SIN is low, the LSB of the internal 16-bit common shift register is set to 0
on the SCLK input rising edge.
Serial data output pin of the internal 16-bit common shift register. The MSB of the
internal 16-bit common shift register appears on SOUT.
SOUT
VCC
22
24
—
19
22
—
O
I
Power supply pin
Thermal
pad
Internally connected to GND in the RGE package only. The thermal pad and the GND
pin must be connected together on the board.
—
Copyright © 2018–2019, Texas Instruments Incorporated
5
TLC6946, TLC6948
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2)
MIN
–0.3
–0.3
–0.3
0
MAX
6
UNIT
V
VCC
Voltage
GCLK, IREF, LAT, SCLK, SIN, SOUT
OUT0 to OUT15
VCC + 0.3
VCC + 0.3
27
V
V
Current
OUT0 to OUT15
mA
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–55
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
(2) All voltage values are with respect to GND.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±7000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
Supply voltage
Supply voltage
3
5.5
V
V
VOUTn Voltage applied to OUT0 to OUT15
Voltage applied to OUT0 to OUT15
0
VCC
0.7 ×
VCC
VIH
VIL
High-level input voltage
Low-level input voltage
GCLK, LAT, SCLK, SIN
GCLK, LAT, SCLK, SIN
VCC
V
V
0.3 ×
VCC
0
IOH
IOL
High-level output current
Low-level output current
SOUT
SOUT
–2
2
mA
mA
IOLC,
max
Maximum constant-output sink current
Data-shift clock frequency
OUT0 to OUT15
0.3
25
mA
fSCLK
SCLK
GCLK
33 MHz
33 MHz
fGCLK Grayscale control clock frequency
Grayscale control clock frequency for dual-edge
operation
fGCLK,B
GCLK
25 MHz
tw(H0)
tw(L0)
tw(H1)
tw(L1)
tw(H2)
tw(L2)
tsu(0)
tsu(1)
tsu(2)
tsu(3)
tsu(4)
Pulse width duration
Pulse width duration
Pulse width duration
Pulse width duration
Pulse width duration
Pulse width duration
Setup time
SCLK
10
10
10
10
18
18
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK
GCLK
GCLK
GCLK (for dual-edge operation)
GCLK (for dual-edge operation)
SIN to SCLK↑
Setup time
LAT ↑ to SCLK ↑
5
Setup time
LAT ↓ to SCLK ↑
5
Setup time
LAT ↓ to SCLK ↑ ,read data from SOUT
LAT ↓ (WRTGS) to LAT ↓ (WRTGS)
50
1.5
Setup time
6
Copyright © 2018–2019, Texas Instruments Incorporated
TLC6946, TLC6948
www.ti.com.cn
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
tsu(5)
tsu(6)
tsu(7)
Setup time
Setup time
Setup time
LAT ↓ (WRTGS) to LAT ↓ (VSYNC)
LAT ↓ (VSYNC) to GCLK ↑
1.5
2.5
2.5
µs
µs
µs
LAT ↓ (VSYNC) to LAT ↓ (WRTGS)
Last LAT (non-0 GS data latched) ↓ to the first
GCLK ↑ of next frame (wake up from power-
save mode)
tsu(8)
Setup time
50
µs
tLSW
th(0)
th(1)
th(2)
TA
Line switching time
Hold time
Last GCLK ↓ to the first GCLK ↑ of next line
SCLK ↑ to SIN
1
2
µs
ns
ns
ns
Hold time
SCLK ↑ to LAT ↑
2
Hold time
SCLK ↑ to LAT ↓
10
–40
–40
Operating ambient temperature
Operating junction temperature
Operating ambient temperature
Operating junction temperature
85
°C
°C
TJ
125
7.4 Thermal Information
TLC6946
THERMAL METRIC(1)
DBQ (SSOP)
24 PINS
87.2
RGE (VQFN)
24 PINS
35.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
42.3
34.7
41.4
15.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.2
0.7
ψJB
41
15.2
RθJC(bot)
N/A
5
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
VCC = 3 V to 5.5 V and TA = –40°C to 85°C; typical values are at VCC = VLED = 3.5 V, TA = 25°C, over recommended operating
conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –2 mA at SOUT
MIN
TYP
MAX
VCC
0.4
UNIT
V
VOH
VOL
High-level output voltage
Low-level output voltage
VCC – 0.4
IOL = 2 mA at SOUT
V
BC = 00h, RIREF = 10.7 kΩ (IOUTn
0.3-mA target)
=
VIREF
Reference voltage
0.8
V
All OUTn = on, LODVTH = 00b
All OUTn = on, LODVTH = 01b
All OUTn = on, LODVTH = 10b
All OUTn = on, LODVTH = 11b
0.12
0.42
0.82
1.12
0.2
0.5
0.9
1.2
0.28
0.58
0.98
1.28
V
V
V
V
V(LOD)
LED open-detection threshold
Knee voltage (OUT0 to OUT15)
All OUTn = on, BC = 36h, RIREF
1.27 kΩ (IOUTn = 10-mA target)
=
V(KNEE)
0.3
V
All OUTn = on, BC = 00h,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 0.3-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (channel-to-
channel)(1)
ΔIOLC0
±1%
±3.5%
(1) The deviation of each output from average of all channels constant current. The deviation is calculated by the formula.
»
…
…
…
ÿ
Ÿ
IOUTn
D % =
-1 ì100
(
)
Ÿ
IOUT0 +IOUT1+...+IOUT14 +IOUT15
Ÿ
16
⁄
Copyright © 2018–2019, Texas Instruments Incorporated
7
TLC6946, TLC6948
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
www.ti.com.cn
Electrical Characteristics (continued)
VCC = 3 V to 5.5 V and TA = –40°C to 85°C; typical values are at VCC = VLED = 3.5 V, TA = 25°C, over recommended operating
conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All OUTn = on, BC = 00h,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 0.3-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (device-to-
device)(2)
ΔIOLC1
ΔIOLC2
ΔIOLC3
ΔIOLC4
ΔIOLC5
ΔIOLC6
ΔIOLC7
±1%
±2%
All OUTn = on, BC = 2Ah,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 1-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (channel-to-
channel)(1)
±1%
±1%
±1%
±1%
±1%
±1%
±3%
±2.5%
±2.5%
±2.5%
±2%
All OUTn = on, BC = 2Ah,VOUTn = 1
V, RIREF = 10.7 kΩ (IOUTn = 1-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (device-to-
device)(2)
All OUTn = on, BC = 36h,VOUTn = 1
V, RIREF = 1.27 kΩ (IOUTn = 10-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (channel-to-
channel)(1)
All OUTn = on, BC = 36h,VOUTn = 1
V, RIREF = 1.27 kΩ (IOUTn = 10-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (device-to-
device)(2)
All OUTn = on, BC = 7Eh,VOUTn = 1
V, RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (channel-to-
channel)(1)
All OUTn = on, BC = 7Eh,VOUTn = 1
V, RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, includes the
VIREF tolerance
Constant-current error (device-to-
device)(2)
±2%
All OUTn = on, VCC = 3 V to 5.5 V,
VOUTn = 1 V
ΔIOLC8
ΔIOLC9
VIL(ISP)
Line regulation(3)
Load regulation(4)
±1
±1
±2
±2
%/V
%/V
V
All OUTn = on, VOUTn = 1 V to 3 V
IREF resistor short-protection enter
threshold
0.15
0.195
IREF resistor short-protection
release threshold
Thermal shutdown threshold(5)
Thermal shutdown hysteresis(5)
SCLK or SIN Input current
VIH(ISP)
0.325
0.4
1
V
T(TSD)
T(HYS)
II
170
15
°C
°C
µA
VI = VCC or GND at SCLK or SIN
–1
(2) The deviation of the average of constant current from the ideal constant current value.
IOUT0 +IOUT1+...+ IOUT14 + IOUT15
»
…
…
…
ÿ
Ÿ
Ÿ
Ÿ
⁄
-Ideal Output Current
16
D % =
ì100
(
)
Ideal Output Current
,Ideal current is calculated by the
≈
’
÷
V
1
8
BC
≈
’
IREF
∆
Ideal Output mA = Gainì
ì
+
(
)
∆
«
÷
◊
∆
÷
◊
RIREF W
144
(
)
«
following equation
(3) Line regulation is calculated by the following equation
»
ÿ
Ÿ
IOUTn at VCC = 5.5V - IOUTn at VCC = 3V
(
)
(
)
100
D %V =
ì
(
)
…
IOUTn at VCC = 3V
5.5V - 3V
…
Ÿ
⁄
(4) Load regulation is calculated by the following equation
»
ÿ
IOUTn at VOUTn = 3V - IOUTn at VOUTn = 1V
(
)
(
)
100
D %V =
ì
Ÿ
(
)
…
IOUTn at VOUTn = 1V
3V -1V
…
Ÿ
⁄
(5) Specified by design
8
Copyright © 2018–2019, Texas Instruments Incorporated
TLC6946, TLC6948
www.ti.com.cn
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
Electrical Characteristics (continued)
VCC = 3 V to 5.5 V and TA = –40°C to 85°C; typical values are at VCC = VLED = 3.5 V, TA = 25°C, over recommended operating
conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GCLK = LAT = SCLK = SIN = GND,
GSn = 0000h, BC = 00h, PCHG_EN
= 0, VOUTn = VCC, RIREF = open
ICC(0)
3
4.5
6
mA
GCLK = LAT = SCLK = SIN = GND,
GSn = 0000h, BC = 36h, PCHG_EN
= 0, VOUTn is floating, RIREF = 1.27
kΩ (IOUTn = 10-mA target)
ICC(1)
4
4
6.5
7.5
7
8
9
mA
mA
mA
mA
GCLK = LAT = SCLK = SIN = GND,
GSn = 0000h, BC = 7Eh, PCHG_EN
= 0, VOUTn is floating, RIREF = 1.27
kΩ (IOUTn = 20-mA target)
ICC(2)
ICC(3)
ICC(4)
Supply current(5)
LAT = SCLK = SIN = GND, GCLK =
33 MHz, GSn = FFFFh, BC = 36h,
4.7
4.7
10
PCHG_EN = 0, VOUTn = 1 V, RIREF
=
1.27 kΩ (IOUTn = 10-mA target)
LAT = SCLK = SIN = GND, GCLK =
33 MHz, GSn = FFFFh, BC = 7Eh,
7.7
1
10
PCHG_EN = 0, VOUTn = 1 V, RIREF
=
1.27 kΩ (IOUTn = 20-mA target)
In power-save mode, PCHG_EN =
0, RIREF = 1.60 kΩ
ICC(6)
RDW
1.5
mA
LAT
250
250
480
480
750
750
Pulldown resistor
kΩ
GCLK
7.6 Switching Characteristics
VCC = 3 V to 5.5 V and TA = –40°C to85°C; Typical values are at VCC = 3.3 V, TA = 25°C,VLED = 5 V, over recommended
operating conditions (unless otherwisenoted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tr(0)
tr(1)
tf(0)
tf(1)
SOUT
2
ns
Rise time(1)
OUTn, BC = 7Eh, VOUTn = 1 V,
RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, RL = 160 Ω
20
2
ns
ns
ns
SOUT
Fall time(1)
OUTn, BC = 7Eh, VOUTn = 1 V,
RIREF = 1.02 kΩ (IOUTn = 25-mA
target), TA = 25°C, RL = 160 Ω
15
SCLK↑ to SOUT↑↓, SEL_TD0 = 00b
SCLK↑ to SOUT↑↓, SEL_TD0 = 01b
SCLK↑ to SOUT↑↓, SEL_TD0 = 10b
SCLK↓ to SOUT↑↓, SEL_TD0 = 11b
5
10
20
5
ns
ns
ns
ns
tpd(0)
Propagation delay(1)
LAT↓ to SOUT, read LOD
information
tpd(1)
25
50
ns
(1) Specified by design
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tw(L)
SCLK(1)
50%
50%
50%
tw(H)
tsu
th
SIN(1)
tsu
tsu
tsu
th
LAT(1)
th
tpd
90%
SOUT
GCLK(1)
OUTn
50%
10%
tf
tr
tw(H)
50%
n-1
n(2)
1
n(2)
1
2
tw(L)
tLSW
tsu
90%
10%
tf
tr
(1) Pulse rise and fall times are 1 ns–3 ns
(2) The last GCLK of each display segment in the sub period
图 1. Timing Diagram
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7.7 Typical Characteristics
35
35
30
25
20
15
10
5
0.3 mA
1 mA
5 mA
10 mA
20 mA
25 mA
0.3 mA
1 mA
5 mA
10 mA
20 mA
25 mA
30
25
20
15
10
5
0
0
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Output Voltage (V)
Output Voltage (V)
D002
D001
VCC = 5 V
VCC = 3.3 V
图 2. Channel Sink Current vs OUTn Voltage
图 3. Channel Sink Current vs OUTn Voltage
12
10
8
12
10
8
6
6
4
4
TA = -40 o
C
TA = -40 o
C
2
2
TA = 25 o
TA = 85 o
C
C
TA = 25 o
TA = 85 o
C
C
0
0
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
Output Voltage (V)
Output Voltage (V)
D004
D003
VCC = 5 V
Temperature
changing
VCC = 3.3 V
Temperature
changing
图 4. Channel Sink Current vs OUTn Voltage
图 5. Channel Sink Current vs OUTn Current
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
Vcc = 3.3 V Min
Vcc = 3.3 V Max
Vcc = 5 V Min
Vcc = 5 V Max
1 mA Min
1 mA Max
25 mA Min
25 mA Max
0
5
10
15
20
25
30
-40
-20
0
20
40
60
80
100
Output Current (mA)
Ambient Temperature (oC)
D005
D006
VOUTn = 1 V
VOUTn = 1 V
图 6. Channel to Channel Accuracy vs OUTn Current
图 7. Channel to Channel Accuracy vs Temperature
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Typical Characteristics (接下页)
30
30
25
20
15
10
5
0.3 mA
1 mA
5 mA
10 mA
20 mA
25 mA
0.3 mA
1 mA
5 mA
10 mA
20 mA
25 mA
25
20
15
10
5
0
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
Brightness Control Data (Decimal)
Brightness Control Data (Decimal)
D008
D007
VCC = 5 V
VOUTn = 1 V
VCC = 3.3 V
VOUTn = 1 V
图 8. Channel Sink Current vs Brightness Control (BC)
图 9. Channel Sink Current vs Brightness Control (BC)
2
10
8
6
4
2
0
1.5
1
0.5
0
Vcc = 3.3 V
Vcc = 5 V
Vcc = 3.3 V
Vcc = 5 V
0
5
10
15
20
25
-40
-20
0
20
40
60
80
100
Output current (mA)
Ambient Temperature (oC)
D009
D011
VOUTn = 1 V
GCLK = 33 MHz
GSn = FFFFh
VOUTn = 1 V
BC = 36h
GCLK = 33 MHz
GSn = 0000h
RIREF = 1.27 kΩ (10-mA target)
图 10. Supply Current (ICC) vs Channel Sink Current
图 11. Supply Current (ICC) in Power-Save Mode vs
Temperature
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8 Parameter Measurement Information
8.1 Pin Equivalent Input and Output Schematic Diagrams
VCC
INPUT
GND
VCC
INPUT
GND
图 12. SIN, SCLK
图 13. LAT, GCLK
VCC
OUTn
INPUT
GND
GND
图 15. OUT0 Through OUT15
图 14. SOUT
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9 Detailed Description
9.1 Overview
The TLC694x device is a 16-channel constant-current-sink LED driver supporting 1- to 32-, 48-multiplexing. Each
channel has an individually adjustable 65,536-step pulse-width modulation (PWM) grayscale (GS) control. The
TLC6946 device implements 16-Kbit display memory and the TLC6948 device implements 24-Kbit display
memory to increase the visual refresh rate and to decrease the grayscale data-writing frequency.
The TLC694x device supports current from 0.3 mA to 25 mA for each channel, with typical 1% channel-to-
channel current deviation and typical 1% device-to-device current deviation. The maximum current value of all 16
channels is set by an external IREF resistor and can be adjusted by the 128-step global brightness control (BC).
The device also implements low-grayscale enhancement technology to solve the coupling issue and improve the
display quality in low-grayscale conditions. These features make the TLC694x device a candidate for high-
density-multiplexing LED-matrix-display and LED-panel applications.
The TLC694x device integrates enhanced circuits to solve the various display issues in fine-pitch LED display
applications: the low-grayscale uniformity issue, coupling issue, ghosting issue, and caterpillar issue. The
TLC694x device features an LED-open detection function, and the error detection results can be read via a serial
data-interface port. Thermal shutdown and IREF-resistor short protection ensure a higher system reliability. The
TLC694x device also has a smart power-save mode that sets the total current consumption to 1 mA (typical)
when all outputs are off.
14
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9.2 Functional Block Diagram
OUT1
OUT0 OUT2
OUT14
OUT13 OUT15
VCC
LED Open Detection (LOD)
Caterpillar Elimination and Ghosting Removal
VCC
16
Reference Current
16-CH Constant Current Sink Control
7-bit Global BC and Pre-Charge
LOD
Threshold
IREF
Control
16
GCLK
Internal
Counter
ES-PWM Decoder
Timing Control
VSYNC
VSYNC
16
Line Counter
BANK A
BANK B
BANK_SEL
16-bit × 16-CH
× 32-,48-line
16-bit × 16-CH
× 32-,48-line
Address Decoder
Writing Control
16
WRTGS
VSYNC
WRTFC
LAT
Command
Decoder
Function Control (FC) Registers
SCLK
READFCx
or
READLOD
16
16
LSB
MSB
16-bit Common Shift Register
SOUT
SIN
16
To Analog
GND
Power Save
Control
16-bit LOD Data
GND
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9.3 Feature Description
9.3.1 Built-In 16Kb Display Memory (SRAM)
The TLC6946 device integrates 16K bits of SRAM to support 1- to 32-multiplexing and the TLC6948 device
integrates 24K bits of SRAM to support 1- to 48-multiplexing. SRAM is divided into two BANKs: BANK A and
BANK B. While BANK A is displaying, BANK B is ready to receive the data of the next frame. While BANK B is
displaying, BANK A is ready to receive the data of next frame.
9.3.2 GCLK Dual-Edge Operation
The TLC694x device uses the rising edge or both edges of GCLK. The selection is made by setting the
GCLK_EDGE bit in the function control register. By default, the TLC6946 device uses the GCLK rising edge, and
the maximum input GCLK frequency is 33 MHz. By setting GCLK_EDGE = 1, the TLC694x device operates at
both GCLK edges (rising and falling), and the maximum internal GCLK frequency is 50 MHz with external 25MHz
input.
9.3.3 Programmable Constant-Sink Channel Current
9.3.3.1 Global Brightness Control (BC)
The TLC694x device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 7-bit word,
thus all output currents can be adjusted in 128 steps from 12.5% to 100.69% for a given current-programming
resistor, RIREF (See 表 1). BC data can be set through the serial interface. When the BC data changes, the output
current also changes immediately. When the device is powered on, the BC data in the function control register is
set to 36h as the default value.
表 1. Global BC Data vs Constant-Current Ratio and Set Current Value
BC DATA
DECIMAL
RATIO OF GAIN /
GAIN_MAX (AT
MAX BC)
IOUT (mA) (IOLCmax= 25
mA, TYP)
IOUT (mA) (IOLCmax
=
GAIN
2.4 mA, TYP)
BINARY
HEX
000 0000
000 0001
000 0010
...
0
1
00
01
02
...
4
12.5%
13.19%
13.88%
...
3.13
3.3
0.3
0.32
0.33
...
4.22
4.44
...
2
3.47
...
...
53
011 0101
35
15.78
49.31%
12.33
1.18
011 0110
(Default)
54 (Default)
36 (Default)
16
50%
12.5
1.2
011 0111
...
55
...
37
...
16.22
...
50.69%
...
12.67
...
1.22
...
111 1101
111 1110
111 1111
125
126
127
7D
7E
7F
31.78
32
99.31%
100%
24.83
25
2.38
2.4
32.22
100.69%
25.17
2.42
9.3.3.2 Select RIREF for a Given BC
The maximum current per channel, IOLCmax, is determined by resistor RIREF, placed between the IREF and GND
pins. The voltage on IREF is typically 0.8 V. RIREF can be calculated by 公式 1.
VIREF (V)
VIREF (V)
1
8
BC
≈
’
RIREF (kW) =
ìGain =
ì32ì
+
∆
«
÷
◊
IOLCmax (mA)
IOLCmax (mA)
144
where
•
•
•
VIREF is the internal reference voltage on IREF (0.8 V)
IOLCmax is the maximum current for each channel
Gain is the current gain at BC = 7E (See 表 1)
(1)
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RIREF must be between 1.02 kΩ and 10.7 kΩ in order to hold the channel sink current IOLC between 25 mA
(typical) and 0.3 mA (typical). Otherwise, the output may be unstable.
表 2. Maximum Constant Current vs External Resistor RIREF
IOLCmax (mA)
RIREF (kΩ, typical)
25
20
15
10
5
1.02
1.28
1.71
2.56
5.12
10.7
2.4
9.3.4 Grayscale (GS) Function (PWM Control)
The TLC694x device can adjust the brightness of each output channel using a pulse-width-modulation (PWM)
control scheme. The architecture of 16 bits per channel results in 65536 brightness steps, from 0% up to 100%
brightness. The on-time (tOUT_ON) of each output (OUTn) can be calculated by 公式 2.
tOUT _ ON = tGCLK ìGSn
where GSn is the grayscale of channel OUTn
(2)
The TLC694x device implements an enhanced spectrum (ES) PWM control. The ES-PWM control can be
selected with two different modes: 8-bit MSB + 8-bit LSB (8+8) mode, and 9-bit MSB + 7-bit LSB (9+7) mode.
See TLC6946 Technical Reference Manual for more details.
9.3.5 Serial Data Interface
The TLC6948 has a flexible serial interface that can be connected to microcontrollers or digital signal processors
in various ways. Only three pins are needed to input data into the device. More than two TLC6948s can be
connected in series by connecting an SOUT pin from one device to the SIN pin of the next device. The SOUT pin
can also be connected to the controller to read back data from the TLC6948 device.
9.3.6 LED-Open Detection (LOD)
The LED-open detection (LOD) function detects faults caused by an open circuit in any LED string or a short
from OUTn to ground with low impedance. It does this by comparing the OUTn voltage to the LOD-detection
threshold-voltage level set by LODVTH in the function control register. If the OUTn voltage is lower than the
programmed voltage, the corresponding output LOD bit is set to 1 to indicate an open LED. Otherwise, the
output of that LOD bit is 0. LOD data output by the detection circuit are valid only during the on period of that
OUTn output channel.
9.3.7 Caterpillar Removal
The TLC694x device implements an internal circuit that can eliminate the caterpillar issue caused by an open
LED. The caterpillar effect is a common issue for LED panels. The caterpillar removal function is enabled by
setting LODRM_EN to 1 (default value after device powered on) in the function control register. When this
function is enabled, the device automatically detects the open LED, and the corresponding channel does not turn
on until device reset.
9.3.8 Precharge FET
The TLC694x internal precharge FET can prevent ghosting of multiplexed LED modules. One cause of this
phenomenon is the charging current from parasitic capacitance on OUTn through the LED when the supply
voltage switches from one common line to the next common line. To prevent this unwanted charging current, the
TLC694x device uses an internal FET to pull up OUTn during the common-line switching period. As a result, no
charging current flows through LED and ghosting is eliminated.
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9.3.9 Thermal Shutdown
The thermal shutdown (TSD) function turns off all device constant-current outputs when the junction temperature
(TJ) exceeds 170°C (typical). It resumes normal operation when TJ falls below 155°C (typical).
9.3.10 IREF Resistor Short Protection (ISP)
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing though the
constant-current output when the IREF resistor is shorted accidently. The TLC694x device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the TLC694x device resumes normal operation.
9.4 Device Functional Modes
9.4.1 Normal Operating Mode
The TLC694x device is fully functional when VCC reaches 3 V and is below 5.5 V. After power on, all OUTn of the
TLC694x device are turned off. All the internal counters and function control registers are initialized. Write the
proper grayscale data and function control data to enable normal device operation.
9.4.2 Power-Save Mode (PSM)
The power-save mode (PSM) is enabled by setting PSM_EN to 1 in the function control register.
When powered on, the default value of this bit is 0. When this function is enabled, if all the GS data received for
the next frame are 0, then device enters power-save mode during the display of the next frame. When the device
is in power-save mode, it resumes normal mode when it detects non-zero GS data input. In power-save mode,
part of analog circuits are not operational; the device total current consumption, ICC, is 1 mA(typical).
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLC6948 device is a 16-channel constant-current sink LED driver supporting 1- to 48-multiplexing. Each
channel has an individually adjustable 65,536-step pulse-width-modulation (PWM) grayscale (GS) control. The
TLC6948 device implements 24 Kbits of display memory to increase the visual refresh rate and to decrease the
grayscale data writing frequency. This integrated memory makes TLC6948 a potential for high-density, fine-pitch
LED matrix applications.
10.2 Typical Application
The TLC6948 is typically connected in series to drive the LED matrix with only a few controller ports. 图 16
shows a typical application diagram with TLC6948 devices connected in cascade for an LED matrix.
VLED
Line 0
ꢀ
ꢀ
ꢀ
VLED
Line n
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
VLED
Line 47
ꢀ
OUT0
SIN
ꢀ
OUT15
SOUT
OUT0
SIN
ꢀ
OUT15
SOUT
OUT0
SIN
ꢀ
OUT15
SOUT
DATA
SCLK
VCC
VCC
VCC
SCLK TLC6948
SCLK TLC6948
SCLK TLC6948
LAT
VCC
GND
VCC
GND
VCC
GND
Controller
LAT
LAT
LAT
IC1
IC2
IC3
GSCLK
DATA BACK
GCLK
IREF
GCLK
IREF
GCLK
IREF
RIREF
RIREF
RIREF
3
图 16. Cascading Three TLC6948 Devices
10.2.1 Design Requirements
For this design example, use the following as the input parameters.
表 3. Design Parameters
DESIGN PARAMETER
VCC and VLED voltage
EXAMPLE VALUE
3 V to 5.5 V
SIN, SCLK, LAT, and GCLK voltage range
The maximum LED forward voltage, V(F)
Low level = GND, high level = VCC
Red LED 2V, green and blue LED 3V
The maximum current for each color LED,
IOLCmax
Red LED 10mA, green LED 6mA, blue LED 4mA.
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10.2.2 Detailed Design Procedures
10.2.2.1 Power Supply Voltage
The LED power supply voltage VLED must be higher than V(F) + V(KNEE). The device power supply voltage, VCC
should be equal or higher than VLED. One example value is VLED = VCC= 3.8 V. See TLC6946 Technical
Reference Manual for more details.
10.2.2.2 Channel Current and Brightness Control
See Global Brightness Control (BC) and Select RIREF for a Given BC. Select the reference-current-setting resistor
RIREF to set the maximum channel current for each color LED. Select the BC data for the best white balance of
the red, green, and blue LED lamp. See TLC6946 Technical Reference Manual for more details.
10.2.2.3 SCLK and GCLK Frequency
SCLK is the serial data shift-in clock signal; and GCLK is the PWM-control reference-clock signal. 公式 3 shows
the minimum frequency requirement for GCLK and SCLK. See TLC6946 Technical Reference Manual for more
details.
fGCLK = mìnì fVR
fSCLK = Nìnì 256ì fFPS
where
•
•
•
•
•
•
•
fGCLK is the minimum GCLK frequency for single-edge operating mode
fSCLK is the minimum SCLK frequency
m is the GCLK number of each sub-period, determined by the PWM mode selected
fVR is the visual refresh rate of the entire cascading series
N is the number of cascaded TLC6948 devices
n is the number of scan lines
fFPS is the frame rate
(3)
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10.2.3 Application Curves
图 17. OUTn Waveform for ES-PWM Mode (GSn = 0001h)
图 18. OUTn Waveform for ES-PWM Mode Zooming in One
Sub-period (GSn = 0001h)
图 19. OUTn Waveform for ES-PWM Mode (GSn = FFFFh)
图 20. OUTn Waveform for ES-PWM Mode Zooming in One
Sub-period (GSn = FFFFh)
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11 Power Supply Recommendations
Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to the VCC pin and GND
plane. Depending on panel size, several equally distributed electrolytic capacitors must be placed on the board
for a well-regulated LED supply voltage VLED. VLED voltage ripple must be less than 5% of its nominal value.
12 Layout
12.1 Layout Guidelines
Place the decoupling capacitor near the VCC pin and GND plane.
Place the current-programming resistor, RIREF, close to the IREF pin and the GND pin.
Make the GND trace as wide as possible for large GND currents.
Routing between the LED cathode and the device OUTn pin must be as short and straight as possible to reduce
wire inductance.
The thermal pad (QFN package) must be connected to the GND plane. Because the thermal pad is used as a
power ground pin internally, there is a large current flow through this pad when all channels turn on.
Furthermore, connect the thermal pad to a heat sink layer by thermal vias to reduce device temperature. One
suggested thermal via pattern is shown in Layout Examples. For more information about suggested thermal via
pattern and via size, see PowerPAD Thermally Enhanced Package.
MOSFETs must be placed in the in the middle of the board, which should be laid out as symmetrically as
possible.
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12.2 Layout Examples
GND
GND
VCC
RIREF
1
2
3
4
5
6
7
8
9
GND
SIN
VCC 24
To controller: SIN
To controller: SCLK
To controller: LAT
IREF 23
SOUT 22
GCLK 21
OUT15 20
OUT14 19
OUT13 18
OUT12 17
OUT11 16
OUT10 15
OUT9 14
OUT8 13
SCLK
LAT
To controller: SOUT
To controller: GCLK
OUT0
OUT1
OUT2
OUT3
OUT4
10 OUT5
11 OUT6
12 OUT7
VLED
VLED
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图 21. SSOP-24 Package Layout Example
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Layout Examples (接下页)
VCC
To controller: SIN
GND
To controller: SCLK
To controller: LAT
To controller: GCLK
To controller: SOUT
1
2
3
4
5
6
18
17
16
15
14
13
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
GND
OUT0
OUT1
OUT2
OUT3
VLED
VLED
OUT4
OUT5
OUT6
OUT7
OUT9
OUT8
GND
Copyright © 2018, Texas Instruments Incorporated
图 22. VQFN-24 Package Layout Example
24
版权 © 2018–2019, Texas Instruments Incorporated
TLC6946, TLC6948
www.ti.com.cn
ZHCSIC6A –JUNE 2018–REVISED JANUARY 2019
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
《TLC694x 16 通道 LED 驱动器技术参考手册》
《半导体和 IC 封装热指标》
13.2 相关链接
表 4 列出了快速访问链接。类别包括技术文档、支持和社区资源、工具与软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
TLC6946
TLC6948
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是适用于指定器件的最新数据。数据如有变更，恕不另行通知，
且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。
版权 © 2018–2019, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC6946DBQR
TLC6946RGER
ACTIVE
ACTIVE
SSOP
VQFN
DBQ
RGE
24
24
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 85
-40 to 85
TLC6946
NIPDAU
TLC
6946
TLC6948DBQR
TLC6948RGER
ACTIVE
ACTIVE
SSOP
VQFN
DBQ
RGE
24
24
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-1-260C-UNLIM
-40 to 85
-40 to 85
TLC6948
TLC
6948
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC6946DBQR
TLC6946RGER
TLC6948DBQR
TLC6948RGER
SSOP
VQFN
SSOP
VQFN
DBQ
RGE
DBQ
RGE
24
24
24
24
2500
3000
2500
3000
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
6.5
4.25
6.5
9.0
4.25
9.0
2.1
1.15
2.1
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
Q1
Q2
Q1
Q2
4.25
4.25
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC6946DBQR
TLC6946RGER
TLC6948DBQR
TLC6948RGER
SSOP
VQFN
SSOP
VQFN
DBQ
RGE
DBQ
RGE
24
24
24
24
2500
3000
2500
3000
356.0
367.0
356.0
367.0
356.0
367.0
356.0
367.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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Copyright © 2022，德州仪器 (TI) 公司
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