TLC6C598PWR [TI]
TLC6C598 8 位移位寄存器 LED 驱动器 | PW | 16 | -40 to 105;
| 型号： | TLC6C598PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TLC6C598 8 位移位寄存器 LED 驱动器 | PW | 16 | -40 to 105 驱动 驱动器 移位寄存器 |
| 文件： | 总23页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC6C598
ZHCSF21 –MAY 2016
TLC6C598 8 位移位寄存器 LED 驱动器
1 特性
3 说明
1
•
•
•
3V 至 5.5V 的宽 VCC范围
TLC6C598 器件是一款单片、中等电压、低电流功率 8
位移位寄存器，专为负载功率要求相对适中的系统（例
如，LED）而设计。
40V 的最大输出额定值
8 路功率双扩散金属氧化物半导体 (DMOS) 晶体管
输出：50mA 持续电流 (VCC = 5V) 或者 200mA 脉
宽调制 (PWM) 电流（单脉冲持续时间短于 1ms 且
平均电流低于 50mA）
此器件包含一个 8 位串入、并出移位寄存器，此寄存
器为一个 8 位 D 类存储寄存器提供数据。移位寄存器
和存储寄存器分别有单独的时钟。输出为低侧、漏极开
路 DMOS 晶体管输出：输出额定值为 40V 及 50mA
持续灌电流或者 200mA PWM 电流（VCC = 5V 时，单
脉冲持续时间短于 1ms 且平均电流低于 50mA）。该
器件内置热关断保护，在人体模型和 200V 机器模型测
试下可提供高达 2000V 的静电放电 (ESD) 保护。
•
•
•
•
•
热关断保护
针对多级的增强型级联
所有寄存器由单一输入清零
低功耗
缓开关时间（tr和 tf），这十分有助于减少电磁干扰
(EMI)
•
16 引脚薄型小外形尺寸 (TSSOP)-PW 封装
TLC6C598 的额定工作环境温度范围为 -40°C 至 105°
C。
2 应用
•
•
•
•
电器显示面板
器件信息(1)
器件型号
TLC6C598
封装
封装尺寸（标称值）
电梯显示面板
PLC 功能指示器
七段显示器
TSSOP (16)
5.00mm x 4.40mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
典型应用电路原理图
Power Supply
4/3
4/3
MCU Serial
Interface
8-Bit Shift Register
LED Driver
8-Bit Shift Register
LED Driver
Typical Cascade Topology
Power Supply
I/Os
8-Bit Shift-
Register
4/3
MCU Serial
Interface
3 ´ 8 LED Matrix
LED Driver
Typical Scan Topology
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLIS177
TLC6C598
ZHCSF21 –MAY 2016
www.ti.com.cn
目录
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Switching Characteristics.......................................... 6
6.8 Timing Waveforms .................................................... 7
6.9 Typical Characteristics.............................................. 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
9
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 器件和文档支持 ..................................................... 17
12.1 社区资源................................................................ 17
12.2 商标....................................................................... 17
12.3 静电放电警告......................................................... 17
12.4 Glossary................................................................ 17
13 机械、封装和可订购信息....................................... 17
7
8
4 修订历史记录
日期
修订版本
注
2016 年 5 月
*
最初发布版本
2
Copyright © 2016, Texas Instruments Incorporated
TLC6C598
www.ti.com.cn
ZHCSF21 –MAY 2016
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
CC
SER_IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
CLR
SRCK
DRAIN7
DRAIN6
DRAIN5
DRAIN4
RCK
G
SER_OUT
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CLR
7
I
Shift register clear, active-low. The storage register transfers data to the output buffer
when CLR is high. Driving CLR low clears all the registers in the device.
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
G
3
4
O
O
O
O
O
O
O
O
I
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
Open-drain output, LED current-sink channel, connect to LED cathode
5
6
11
12
13
14
8
Output enable, active-low. LED-channel enable and disable input pin. Having G low
enables all drain channels according to the output-latch register content. When high, all
channels are off.
GND
16
10
2
—
I
Power ground, the ground reference pin for the device. This pin must connect to the
ground plane on the PCB.
RCK
Register clock. The data in each shift register stage transfers to the storage register at the
rising edge of RCK.
SER IN
SER OUT
SRCK
VCC
I
Serial data input. Data on SER IN loads into the internal register on each rising edge of
SRCK.
9
O
I
Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade
several devices on the serial bus.
15
1
Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal
serial shift registers.
I
Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close
to the pin.
Copyright © 2016, Texas Instruments Incorporated
3
TLC6C598
ZHCSF21 –MAY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VCC
VI
Logic supply voltage
8
8
V
V
V
Logic input-voltage range
VDS
Power DMOS drain-to-source voltage
Continuous total dissipation
Operating junction temperature range
Storage temperature range
42
See Thermal Information
TJ
–40
–55
125
165
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
All pins
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Corner pins (1, 8, 9, and
16)
±750
Q100-011
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN MAX
UNIT
V
VCC
VIH
VIL
TA
Supply voltage
3
5.5
High-level input voltage
Low-level input voltage
Operating ambient temperature
2.4
V
0.7
V
–40 105
°C
6.4 Thermal Information
TLC6C598
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
129.4
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
55.4
Junction-to-board thermal resistance
65.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
9.9
ψJB
65.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
4
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TLC6C598
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ZHCSF21 –MAY 2016
6.5 Electrical Characteristics
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRAIN0 to DRAIN7. Drain-to-
source voltage
40
V
IOH = –20 μA
4.9
4.5
4.99
4.69
0.001
0.25
0.2
V
V
High-level output voltage, SER
OUT
VOH
VCC = 5 V
IOH = −4 mA
IOH = 20 μA
0.01
0.4
V
Low-level output voltage, SER
OUT
VOL
VCC = 5 V
IOH = 4 mA
V
IIH
IIL
High-level input current
Low-level input current
VCC = 5 V, VI = VCC
VCC = 5 V, VI = 0
μA
μA
–0.2
0.1
All outputs off
All outputs on
All outputs on
VCC = 5 V
1
ICC
Logic supply current
VCC = 5 V, no clock signal
μA
μA
μA
88
160
ICC(FRQ)
IDSx
Logic supply current at frequency fSRCK = 5 MHz, CL = 30 pF
200
VDS = 30 V
Off-state drain current
0.1
0.3
VDS = 30 V, TC = 105°C
VCC = 5 V
0.15
7.41
ID = 20 mA, VCC = 5 V, TA = 25°C,
Single channel ON
6
6.7
8.6
9.6
ID = 20 mA, VCC = 5 V, TA = 25°C,
All channels ON
8.3
9.34
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
Single channel ON
7.9
11.2
12.3
12.9
14.5
16.4
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
All channels ON
8.7
10.25
11.13
12.28
13.69
14.89
Static drain-source on-state
resistance
rDS(on)
Ω
ID = 20 mA, VCC = 5 V, TA = 105°C,
Single channel ON
9.1
ID = 20 mA, VCC = 5 V, TA = 105°C,
All channels ON
10.3
11.6
ID = 20 mA, VCC = 3.3 V, TA = 105°C,
Single channel ON
ID = 20 mA, VCC = 3.3 V, TA = 105°C,
All channels ON
12.8
150
18.2
200
TSHUTDOWN Thermal shutdown trip point
Thys Hysteresis
175
15
ºC
ºC
6.6 Timing Requirements
MIN
15
NOM
MAX
UNIT
tsu
th
Setup time, SER IN high before SRCK↑
ns
ns
ns
Hold time, SER IN high after SRCK↑
15
tw
SER IN pulse duration
40
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5
TLC6C598
ZHCSF21 –MAY 2016
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6.7 Switching Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Propagation delay time from G to output, low-to-high
level
tPLH
tPHL
220
ns
Propagation delay time from G to output, high-to-low
level
75
ns
CL = 30 pF, ID = 48 mA
tr
Rise time, drain output
210
128
49.4
20
ns
ns
ns
ns
ns
tf
Fall time, drain output
tpd
Propagation delay time, SRCK↓ to SER OUT
SER OUT rise time (10% to 90%)
SER OUT fall time (90% to 10%)
Serial clock frequency
CL = 30 pF, ID = 48 mA
CL = 30 pF
tor
tof
CL = 30 pF
20
f(SRCK)
tSRCK_WH
tSRCK_WL
CL = 30 pF, ID = 20 mA
10
MHz
ns
SRCK pulse duration, high
SRCK pulse duration, low
30
30
ns
6
版权 © 2016, Texas Instruments Incorporated
TLC6C598
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ZHCSF21 –MAY 2016
6.8 Timing Waveforms
图 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift register
clock (SRCK) because there is a phase inverter at SER OUT (see 图 13). As a result, it takes seven and a half
periods of SRCK for data to transfer from SER IN to SER OUT.
8
3
7
6
5
4
2
1
SRCK
SER IN
1
0
CLR
SER OUT
图 1. SER IN to SER OUT Waveform
图 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the test
circuit shown in 图 11.
5 V
50%
tPHL
G
Output
SRCK
50%
0 V
tPLH
10 V
90%
tr
90%
10%
10%
tf
0.5 V
5 V
50%
0 V
5 V
0 V
tsu
th
SER IN
50%
50%
tw
Switching Times, Input Setup and Hold Waveforms
50%
SRCK
50%
tpd
tpd
SER OUT
50%
50%
SER OUT Propagation Delay Waveform
图 2. Switching Times and Voltage Waveforms
版权 © 2016, Texas Instruments Incorporated
7
TLC6C598
ZHCSF21 –MAY 2016
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6.9 Typical Characteristics
500
350
300
250
200
150
100
50
TA= –40°C
All Channels Off
All Channels On
TA= 25°C
400
TA= 105°C
300
200
100
0
0
0.1
1
10
100
3.0
3.5
4.0
4.5
5.0
5.5
6.0
C001
Frequency (MHz)
Supply Voltage (V)
VCC = 5 V
V
图 3. Supply Current vs Frequency
图 4. Supply Current vs Supply Voltage
12
10
8
16
14
12
10
8
6
6
4
4
TA= –40°C
TA= 25°C
TA= 105°C
TA= –40°C
TA= 25°C
TA= 105°C
2
2
0
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Drain Current (mA)
Drain Current (mA)
Single channel on
VCC = 5 V
Single channel on
VCC = 3.3 V
图 5. Drain-to-Source On-State Resistance vs Drain Current
图 6. Drain-to-Source On-State Resistance vs Drain Current
14
18
16
14
12
10
8
12
10
8
6
6
4
TA= –40°C
4
2
0
TA = –40°C
TA = 25°C
TA = 105°C
2
0
TA= 25°C
TA= 105°C
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Drain Current (mA)
Drain Current (mA)
All channels on
VCC = 5 V
All channels on
VCC = 3.3 V
图 7. Drain-to-Source On-State Resistance vs Drain Current
图 8. Drain-to-Source On-State Resistance vs Drain Current
8
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TLC6C598
www.ti.com.cn
ZHCSF21 –MAY 2016
Typical Characteristics (接下页)
18
16
14
12
10
8
350
300
250
200
150
100
50
tPLH
t
PHL
t
r
t
f
6
4
2
0
TA = –40°C
TA = 25°C
TA = 105°C
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
–40
–20
0
20
40
60
80
100
120
Supply Voltage (V)
Ambient Temperature (°C)
All channels on
IDS = 20 mA
V
图 9. Drain-to-Source On-State Resistance vs Supply
图 10. Switching Time vs Ambient Temperature
Voltage
7 Parameter Measurement Information
图 11 and 图 12 show the resistive-load test circuit and voltage waveforms. One can see from 图 12 that with G
held low and CLR held high, the status of each drain changes on the rising edge of the register clock, indicating
the transfer of data to the output buffers at that time.
5 V
10 V
VCC
CLR
ID
RL = 200 W
SRCK
SER IN
RCK
Output
MCU
DRAIN
CL = 30 pF
(see Note A)
G
GND
Copyright © 2016, Texas Instruments Incorporated
A. CL includes probe and jig capacitance.
图 11. Resistive-Load Test Circuit
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ZHCSF21 –MAY 2016
www.ti.com.cn
Parameter Measurement Information (接下页)
8
7
6
5
4
3
2
1
SRCK
SER IN
G
RCK
0
1
0
0
CLR
DRAIN0
DRAIN1
DRAIN6
DRAIN7
0
0
图 12. Voltage Waveforms
10
版权 © 2016, Texas Instruments Incorporated
TLC6C598
www.ti.com.cn
ZHCSF21 –MAY 2016
8 Detailed Description
8.1 Overview
The TLC6C598 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive relatively
moderate load power such LEDs. The device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-
bit D-type storage register. Thermal shutdown protection is also built-into the device.
8.2 Functional Block Diagram
G
RCK
DRAIN0
CLR
D
D
SRCK
C1
C1
CLR
D
CLR
D
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER IN
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
GND
D
C1
CLR
SER OUT
Copyright © 2016, Texas Instruments Incorporated
图 13. Logic Diagram (Positive) of TLC6C598
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ZHCSF21 –MAY 2016
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8.3 Feature Description
8.3.1 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C
(typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds
the thermal trip threshold. Once the junction temperature decreases below 160°C (typical), the device begins to
operate again.
8.3.2 Serial-In Interface
The TLC6C598 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when
shift-register clear (CLR) is high.
8.3.3 Clear Registers
A logic low on the CLR pin clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.4 Output Channels
DRAIN0–DRAIN7. These pins can survive up to 40-V LED supply voltage.
8.3.5 Register Clock
RCK is the storage-register clock. Data in the storage register appears at the output whenever the output enable
(G) input signal is high.
8.3.6 Cascade Through SER OUT
By connecting the SER OUT pin to the SER IN input of the next device on the serial bus in cascade, the data
transfers to the next device on the falling edge of SRCK. This connection can improve the cascade application
reliability, as it can avoid the issue that the second device receives SRCK and data input on the same rising
edge of SRCK.
8.3.7 Output Control
Holding the output enable (pin G) high holds all data in the output buffers low, and all drain outputs are off.
Holding G low makes data from the storage register transparent to the output buffers. When data in the output
buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable
of sinking current. This pin also can be used for global PWM dimming.
8.4 Device Functional Modes
8.4.1 Operation With VCC < 3 V
This device works normally within the range 3 V ≤ VCC ≤ 5.5 V. When the operating voltage is lower than 3 V,
correct behavior of the device, including communication interface and current capability, is not assured.
8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
The device works normally in this voltage range, but reliability issues may occur if the device works for a long
time in this voltage range.
12
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TLC6C598
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ZHCSF21 –MAY 2016
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLC6C598 device is a serial-in, parallel-out, power and logic, 8-bit shift register with low-side open-drain
DMOS output ratings of 40-V and 50-mA continuous sink-current capabilities when VCC = 5 V. The device is
designed to drive resistive loads and is particularly well-suited as an interface between a microcontroller and
LEDs or lamps. The device also provides up to 2000 V of ESD protection when tested using the human body
model and 200 V when using the machine model.
9.2 Typical Application
图 14 shows a typical cascade application circuit with two TLC6C598 chips configured in cascade topology. The
MCU generates all the input signals.
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ZHCSF21 –MAY 2016
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Typical Application (接下页)
Battery 9 V–40 V
3 V–5.5 V
DRAIN0 DRAIN1
VCC
DRAIN6 DRAIN7
SER IN
SRCK
GND
MCU
G
SER OUT
CLR
RCK
DRAIN0 DRAIN1
VCC
DRAIN6 DRAIN7
SER IN
SRCK
GND
G
SER OUT
CLR
RCK
Copyright © 2016, Texas Instruments Incorporated
图 14. Typical Application Circuit
9.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
VBattery
9 V to 40 V
3.3 V
VCC_1
I(D0), I(D1), I(D2), I(D3) , I(D4), I(D5), I(D6), I(D7)
VCC_2
30 mA
5 V
I(D8), I(D9), I(D10), I(D11) , I(D12), I(D13), I(D14), I(D15)
50 mA
14
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ZHCSF21 –MAY 2016
9.2.2 Detailed Design Procedure
To begin the design process, the designer must decide on a few parameters, as follows:
•
•
•
Vsupply: LED supply voltage
VDx: LED forward voltage
I: LED current
With these parameters determined, the resistor in series with the LED can be calculated by using the following
equation:
RX = (VSupply - VDx ) / I
(1)
9.2.3 Application Curve
图 15. TLC6C598 Application Waveform
版权 © 2016, Texas Instruments Incorporated
15
TLC6C598
ZHCSF21 –MAY 2016
www.ti.com.cn
10 Power Supply Recommendations
The TLC6C598 device is designed to operate with an input voltage supply range from 3 V to 5.5 V. This input
supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There are no special layout requirements for the digital signal pins. The only requirement is placing the ceramic
bypass capacitors near the corresponding pins.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow
path from the package to the ambient is through the copper on the PCB. Maximizing the copper coverage is
extremely important when the design does not include heat sinks attached to the PCB on the other side of the
package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity
of the board.
All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent solder
voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Example
1
2
GND
VCC
SER IN
DRAIN0
DRAIN1
16
15
SRCK
3
4
DRAIN7
DRAIN6
DRAIN5
14
13
12
5
6
7
DRAIN2
DRAIN3
11
DRAIN4
RCK
CLR
10
9
8
G
SER OUT
图 16. TLC6C598 Example Layout
16
版权 © 2016, Texas Instruments Incorporated
TLC6C598
www.ti.com.cn
ZHCSF21 –MAY 2016
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件提供的最新数据。本数据随时可能发生变更并且
不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。
版权 © 2016, Texas Instruments Incorporated
17
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC6C598PWR
ACTIVE
TSSOP
PW
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
6C598I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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