TLC7226 [TI]
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS;
| 型号： | TLC7226 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS |
| 文件： | 总19页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢄꢅ ꢂ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢄꢅ ꢇ ꢆ ꢀ ꢁꢂ ꢃꢄ ꢄꢅ ꢈ
ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
features
DW OR N PACKAGE
(TOP VIEW)
D
D
D
D
D
Four 8-Bit D/A Converters
Microprocessor Compatible
TTL/CMOS Compatible
OUTB
OUTA
OUTC
OUTD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Single Supply Operation Possible
CMOS Technology
V
V
SS
DD
REF
AGND
DGND
DB7
DB6
DB5
A0
A1
applications
WR
DB0
DB1
DB2
DB3
D
D
D
Process Control
Automatic Test Equipment
Automatic Calibration of Large System
Parameters, e.g. Gain/Offset
DB4
description
FK PACKAGE
(TOP VIEW)
The TLC7226C, TLC7226I, and TLC7226M
consist of four 8-bit voltage-output digital-to-
analog converters (DACs) with output buffer
amplifiers and interface logic on a single
monolithic chip.
3
4
2
1
20 19
REF
AGND
DGND
DB7
V
DD
18
17
16
15
14
Separate on-chip latches are provided for each of
the four DACs. Data is transferred into one of
these data latches through a common 8-bit
TTL/CMOS-compatible 5-V input port. Control
inputs A0 and A1 determine which DAC is loaded
when WR goes low. The control logic is speed
compatible with most 8-bit microprocessors.
A0
5
6
7
A1
WR
DB0
DB6
8
9
10 11 12 13
Each DAC includes an output buffer amplifier
capable of sourcing up to 5 mA of output current.
The TLC7226 performance is specified for input reference voltages from 2 V to V
– 4 V with dual supplies.
DD
The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply
rail at a reference of 10 V.
The TLC7226 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common
8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.
Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal
dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space
requirements and offers increased reliability in systems using multiple converters. The Leadless Ceramic Chip
Carrier (LCCC) package provides for operation at military temperature range. The pinout is aimed at optimizing
board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at
the other.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
description (continued)
The TLC7226C is characterized for operation from 0°C to 70°C. The TLC7226I is characterized for operation
from –25°C to 85°C. The TLC7226M is characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(DW)
PLASTIC DIP
(N)
LCCC
(FK)
0°C to 70°C
–25°C to 85°C
–55°C to 125°C
TLC7226CDW
TLC7226IDW
—
TLC7226CN
TLC7226IN
—
—
—
TLC7226MFKB
functional block diagram
4
REF
_
+
2
1
OUTA
OUTB
8
8
8
8
Latch
A
DAC A
DAC B
_
+
Latch
B
8
7–14
DB0–DB7
_
+
20
19
OUTC
OUTD
8
8
8
8
Latch
C
DAC C
DAC D
_
+
Latch
D
15
17
16
WR
A0
Control
Logic
A1
schematic of outputs
EQUIVALENT ANALOG OUTPUT
V
DD
Output
450 µA
V
SS
2
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
Terminal Functions
TERMINAL
NAME NO.
AGND
I/O
DESCRIPTION
†
5
Analog ground. AGND is the reference and return terminal for the analog signals and supply.
DAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD.
Digital ground. DGND is the reference and return terminal for the digital signals and supply.
Digital DAC data inputs. DB0–DB7 are the input digital data used for conversion.
DACA output. OUTA is the analog output of DACA.
A0, A1
DGND
DB0–DB7
OUTA
OUTB
OUTC
OUTD
REF
17, 16
6
I
14–7
2
I
O
O
O
O
I
1
DACB output. OUTB is the analog output of DACB.
20
19
4
DACC output. OUTC is the analog output of DACC.
DACD output. OUTD is the analog output of DACD.
Voltage reference input. The voltage level on REF determines the full scale analog output.
Positive supply voltage input terminal
V
V
18
3
DD
Negative supply voltage input terminal
SS
WR
15
I
Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR
is low.
†
Terminal numbers shown are for the DW, N, and FK packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V : AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 17 V
DD
‡
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 24 V
SS
Supply voltage range, V : AGND or DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0.3 V
SS
Voltage range between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –17 V to 17 V
Input voltage range, V (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
I
DD
Reference voltage range: V (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
ref
ref
DD
V
(to V
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V
SS
Output voltage range, V (to AGND) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V
O
SS
DD
Continuous total power dissipation at (or below) T = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 500 mW
A
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
E suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N packages . . . . . . . . . . . . . . 260°C
Case temperature for 10 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The V
SS
terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device.
NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit
current to AGND is 60 mA.
2. For operation above T = 75°C, derate linearly at the rate of 2 mW/°C.
A
3
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
recommended operating conditions
MIN MAX
UNIT
Supply voltage, V
Supply voltage, V
11.4
–5.5
2
16.5
0
V
V
DD
SS
High-level input voltage, V
IH
V
Low-level input voltage, V
IL
0.8
V
Reference voltage, V
ref
0
2
V
DD
–4
V
Load resistance, R
kΩ
ns
ns
ns
ns
ns
L
Setup time, address valid before WR↓, t
(see Figure 6)
V
V
V
V
V
= 11.4 V to 16.5 V
= 11.4 V to 16.5 V
= 11.4 V to 16.5 V
= 11.4 V to 16.5 V
= 11.4 V to 16.5 V
*0
su(AW)
DD
DD
DD
DD
DD
*45
*0
Setup time, data valid before WR↑, t
(see Figure 6)
(see Figure 6)
su(DW)
Hold time, address valid before WR↑, t
h(AW)
*10
*50
0
Hold time, data valid before WR↑, t
(see Figure 6)
h(DW)
Pulse duration, WR low, t (see Figure 6)
w
C suffix
I suffix
70
–25
–55
85
Operating free-air temperature, T
°C
A
M suffix
125
* This parameter is not tested for M suffix devices.
electrical characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER
Input current, digital
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
V = 0 V or V
±1
µA
I
I
DD
V = 0.8 V or 2.4 V,
V
= 16.5 V,
I
V
DD
No load
Supply current
6
16
10
mA
(DD)
(SS)
= – 5 V,
SS
V = 0.8 V or 2.4 V, No load
Supply current
4
4
mA
kΩ
I
r
Reference input resistance
Power supply sensitivity
2
i(ref)
∆V
DD
= ±5%
0.01
%/%
C and I suffix
M suffix
65
All 0s loaded
All 1s loaded
*30
REF input
*300
8
C
Input capacitance
pF
i
C and I suffix
M suffix
Digital inputs
*12
* This parameter is not tested for M suffix devices.
4
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
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ꢘ
SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
operating characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Slew rate
*2.5
V•µs
Positive full scale
*5
*7
Settling time to 1/2 LSB
V
ref
= 10 V
µs
Negative full scale
Resolution
8
bits
LSB
Total unadjusted error
Linearity error
Full-scale error
Gain error
±2
±1
±2
Differential/integral
LSB
V
V
= 15 V ±5%,
V
= 10 V
= 10 V
DD
ref
LSB
±0.25
±20
±50
±20
50
LSB
Full scale
= 14 V to 16.5 V,
V
ref
ppm/°C
µV/°C
mV
DD
Temperature coefficient of gain
Zero-code error
Zero-code error
±80
Digital crosstalk glitch impulse area
V
ref
= 0
nV•s
* This parameter is not tested for M suffix devices.
single power supply, V
= 14.25 V to 15.75 V, V = AGND = DGND = 0 V, V = 10 V (unless otherwise noted)
SS ref
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply current, I
Slew rate
V = 0.8 V or 2.4 V, No load
I
5
13
mA
DD
*2
V•µs
Positive full scale
*5
Settling time to 1/2 LSB
µs
Negative full scale
*20
Resolution
8
bits
LSB
Total unadjusted error
Full-scale error
±2
±2
LSB
Full scale
V
DD
= 14 V to 16.5 V,
V
ref
= 10 V
±20
±50
ppm/°C
µV/°C
LSB
Temperature coefficient of gain
Zero-code error
Differential
Linearity error
±1
Digital crosstalk-glitch impulse area
50
nV•s
* This parameter is not tested for M suffix devices.
5
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
ꢘ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
t
su(DW)
V
DD
Data
0 V
t
h(DW)
V
DD
Address
0 V
t
h(AW)
t
su(AW)
t
w
V
DD
WR
0 V
NOTES: A. t = t = 20 ns over V
DD
range.
r
f
B. The timing measurement reference level is equal to V + V
IH
IL
divided by 2.
C. The selected input latch is transparent while WR is low. Invalid
data during this time can cause erroneous outputs.
Figure 1. Write-Cycle Voltage Waveforms
TYPICAL CHARACTERISTICS
OUTPUT CURRENT (SINK)
OUTPUT CURRENT
vs
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
700
600
500
400
300
200
200
150
T
V
= 25°C
A
= 15 V
DD
V
= 15 V
DD
Source Current
Short-Circuit
Limiting
100
50
V
= –5 V
SS
V
= 0
SS
0
–0.1
–0.2
T
V
= 25°C
A
= –5 V
SS
Digital In = 0 V
100
0
–0.3
–0.4
Sinking
Current Source
0
1
2
3
4
5
6
7
8
9
10
–2
–1
0
1
2
V
O
– Output Voltage – V
V
O
– Output Voltage – V
Figure 2
Figure 3
6
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
PRINCIPLES OF OPERATION
AGND bias for direct bipolar output operation
The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown
in Figure 4 by biasing AGND to V . This configuration provides an excellent method for providing a direct
SS
bipolar output with no additional components. The transfer values are shown in Table 1.
REF (V = 5 V)
ref
V
DD
4
18
‡
TLC7226
_
OUT
2
Output range
(5 V to –5 V)
AGND
+
DAC A
5
3
6
V
DGND
SS
–5 V
Digital inputs omitted for clarity.
‡
Figure 4. AGND Bias for Direct Bipolar Operation
Table 1. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
ANALOG OUTPUT
MSB
LSB
127
128
ref ǒ Ǔ
1111
1111
) V
) V
1
ref ǒ Ǔ
1000
1000
0111
0001
0000
1111
128
0 V
1
ref ǒ Ǔ
* V
128
127
128
ref ǒ Ǔ
0000
0000
0001
0000
* V
128
ref ǒ Ǔ+ * V
–V
ref
128
AGND bias for positive output offset
The TLC7226 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an
offset analog output voltage level. Figure 5 shows a circuit configuration to achieve this for channel A of the
TLC7226. The output voltage, V , at OUTA can be expressed as:
O
A ǒVIǓ
V
+ V
) D
(1)
O
BIAS
where D is a fractional representation of the digital input word (0 ≤ D ≤ 255/256).
A
Increasing AGND above system GND reduces the output range. V
specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output
– V must be at least 4 V to ensure
ref
DD
voltages of all the DACs in the TLC7226. Supply voltages V
to DGND.
and V for the TLC7226 should be referenced
DD
SS
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
PRINCIPLES OF OPERATION
AGND bias for positive output offset (continued)
V
V
DD
ref
4
18
†
TLC7226
V
I
_
2
OUTA
AGND
+
DAC A
3
5
6
V
bias
V
SS
DGND
†
Digital inputs omitted for clarity.
Figure 5. AGND Bias Circuit
interface logic information
Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of
the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the
selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the
addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value
corresponding to the data held in their respective latches.
Table 2. Function Table
CONTROL INPUTS
OPERATION
WR
A1
A2
H
X
X
No operation
Device not selected
DAC A transparent
DAC A latched
DAC B transparent
DAC B latched
DAC C transparent
DAC C latched
DAC D transparent
DAC D latched
L
↑
L
↑
L
↑
L
↑
L
L
L
L
L
H
H
L
L
H
H
L
H
H
H
H
L = low, H = high, X = irrelevant
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
PRINCIPLES OF OPERATION
interface logic information (continued)
17
A0
To Latch A
To Latch B
16
A1
To Latch C
To Latch D
15
WR
Figure 6. Input Control Logic
unipolar output operation
The unipolar output operation is the basic mode of operation for each channel of the TLC7226, with the output
voltages having the same positive polarity as V . The TLC7226 can be operated with a single power supply
ref
(V = AGND) or with positive/negative power supplies. The voltage at V must never be negative with respect
SS
ref
to AGND to prevent parasitic transistor turnon. Connections for the unipolar output operation are shown in
Figure 7. Transfer values are shown in Table 3.
Table 3. Unipolar Code
_
2
DAC LATCH CONTENTS
OUTA
OUTB
4
ANALOG OUTPUT
+
REF
DAC A
DAC B
DAC C
DAC D
MSB
LSB
255
256
ref ǒ Ǔ
1111
1111
) V
_
+
1
20
19
129
256
ref ǒ Ǔ
1000
0001
) V
) V
) V
) V
V
128
ref
2
ref ǒ Ǔ+ )
1000
0111
0000
1111
256
_
+
OUTC
OUTD
127
ref ǒ Ǔ
256
1
ref ǒ Ǔ
0000
0000
0001
0000
_
+
256
0 V
1
256
–8
NOTE A. 1 LSB + ǒVref Ǔ + V
ref ǒ Ǔ
2
Figure 7. Unipolar Output Circuit
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
PRINCIPLES OF OPERATION
linearity, offset, and gain error using single-ended power supplies
When an amplifier is operated from a single power supply, the voltage offset can still be either positive or
negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the
output voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However,
because the most negative supply rail is ground, the output cannot be driven to a negative voltage.
So when the output offset voltage is negative, the output voltage remains at zero volts until the input code value
produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in a transfer
function shown in Figure 8.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 8. Effect of Negative Offset (Single Power Supply)
This negative offset error, not the linearity error, produces the breakpoint. The transfer function would have
followed the dotted line if the output buffer could be driven to a negative voltage.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single power supply operation does
not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
in the unipolar mode is measured between full scale code and the lowest code which produces a positive output
voltage.
The code is calculated from the maximum specification for the negative offset.
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
APPLICATION INFORMATION
bipolar output operation using external amplifier
Each of the DACs of the TLC7226 can also be individually configured to provide bipolar output operation, using
an external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A of the TLC7226. In this case:
R2
R1
R2
R1
(2)
ǒDA
refǓ* ǒVrefǓ
V
+ 1 )
V
O
with R1 + R2
+ ǒ2D * 1Ǔ V
V
O
A
ref
where D is a fractional representation of the digital word in latch A.
A
Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track
over temperature. The TLC7226 can be operated with a single power supply or from positive and negative
power supplies.
REF
†
R1
†
R2
4
15 V
TLC7226
_
+
_
+
V
O
2
DAC A
–15 V
†
R1 = R2 = 10 kΩ ±0.1%
Figure 9. Bipolar Output Circuit
staircase window comparator
In many test systems, it is important to be able to determine whether some parameter lies within defined limits.
The staircase window comparator shown in Figure 10 is a circuit that can be used to measure the V and V
OH
OL
thresholds of a TTL device under test. Upper and lower limits on both V
and V can be programmed using
OH
OL
the TLC7226. Each adjacent pair of comparators forms a window of programmable size (see Figure 11). When
the test voltage (V ) is within a window, then the output for that window is higher. With a reference of 2.56 V
test
applied to the REF input, the minimum window size is 10 mV.
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
ꢘ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
APPLICATION INFORMATION
staircase window comparator (continued)
5 V
Reference Voltage
V
test
From DUT
10 kΩ
+
_
4
Window 1
REF
+
_
5 V
10 kΩ
V
V
2
OH
+
_
OUTA
Window 2
+
_
5 V
TLC7226
10 kΩ
OH
1
+
_
OUTB
Window 3
+
_
5 V
10 kΩ
V
V
OL
20
19
+
_
OUTC
OUTD
Window 4
+
_
5 V
10 kΩ
OL
+
_
Window 5
AGND
+
_
5
Figure 10. Logic Level Measurement
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
ꢘ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
APPLICATION INFORMATION
staircase window comparator (continued)
REF
Window 1
Window 2
OUTA
OUTB
Window 3
OUTC
OUTD
Window 4
Window 5
AGND
Figure 11. Adjacent Window Structure
The circuit can easily be adapted as shown in Figure 12 to allow for overlapping of windows. When the three
outputs from this circuit are decoded, five different nonoverlapping programmable window possibilities can
again be defined (see Figure 13).
5 V
Reference Voltage
V
10 kΩ
test
From DUT
+
_
4
Window 1
REF
OUTA
+
_
2
1
5 V
10 kΩ
+
_
OUTB
Window 2
TLC7226
OUTC
+
_
20
19
5 V
10 kΩ
+
_
OUTD
Window 3
AGND
+
_
5
Figure 12. Overlapping Window Circuit
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
APPLICATION INFORMATION
staircase window comparator (continued)
REF
Window 1
OUTB
Windows 1 and 2
OUTA
Window 2
OUTD
OUTC
Windows 2 and 3
Window 3
AGND
Figure 13. Overlapping Window Structure
output buffer amplifier
The unity-gain output amplifier is capable of sourcing 5 mA into a 2-kΩ load and can drive a 3300-pF capacitor.
The output can be shorted to AGND indefinitely or it can be shorted to any voltage between V
consistent with the maximum device power dissipation.
and V
SS
DD
multiplying DAC
The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and
– 4 V. When this configuration is used, V should be 14.25 V to 15.75 V. A low output-impedance buffer
V
DD
DD
should be used so that the input signal is not loaded by the resistor ladder. Figure 14 shows the general
schematic.
15 V
1/4 TLC7226
R1
15 V
_
+
V
ref
_
V
O
4
DAC
+
OP07
AC Reference
Input Signal
AGND
5
DGND
6
R2
Figure 14. AC Signal Input Scheme
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ꢋ
ꢘ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢊ
ꢎ
ꢁ
ꢏ
ꢐ
ꢑ
ꢒ
ꢇ
ꢀ
ꢌ
ꢇ
ꢓꢇ
ꢀꢋ
ꢁ
ꢑ
ꢀꢔ
ꢑ
ꢋ
ꢕ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢕ
ꢖ
ꢏꢍ
ꢀ
ꢏ
ꢍ
ꢗ
ꢘ
SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
0.410
0.510
0.610
0.710
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
16
9
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
4040000/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
15
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ꢉꢊ ꢋ ꢌꢍ ꢊ ꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓ ꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋ ꢁꢔ ꢓ ꢂꢔ ꢕꢖꢏ ꢍꢀ ꢏꢍꢗ
ꢘ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
16
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ꢉ ꢊꢋꢌꢍ ꢊꢎꢁ ꢏ ꢐ ꢑꢒꢇ ꢀ ꢌꢇ ꢓꢇ ꢀꢋꢁ ꢑꢀꢔ ꢑꢋꢕꢋꢁ ꢔ ꢓ ꢂꢔ ꢕꢖ ꢏꢍ ꢀꢏ ꢍ ꢗ
ꢘ
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SLAS060E – JANUARY 1995 – REVISED JANUARY 2003
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–ā15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001)
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Copyright 2003, Texas Instruments Incorporated
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