TLC7524EDR_技术文档

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

D, N, OR PW PACKAGE

(TOP VIEW)

D

Easily Interfaced to Microprocessors

On-Chip Data Latches

Monotonic Over the Entire A/D Conversion

Range

R

REF

OUT1

OUT2

GND

DB7

DB6

DB5

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FB

V

Segmented High-Order Bits Ensure

Low-Glitch Output

DD

WR

CS

DB0

DB1

DB2

Interchangeable With Analog Devices

AD7524, PMI PM-7524, and Micro Power

Systems MP7524

DB4

DB3

D

Fast Control Signaling for Digital

Signal-Processor Applications Including

Interface With TMS320

FN PACKAGE

(TOP VIEW)

CMOS Technology

KEY PERFORMANCE SPECIFICATIONS

Resolution

8 Bits

3

2

1

20 19

18

Linearity error

Power dissipation at V

Setting time

1/2LSB Max

5mW Max

100ns Max

80ns Max

V

GND

4

5

6

7

8

DD

= 5V

DD

WR

NC

DB7

NC

17

16

15

14

Propagation delay time

CS

DB6

DB5

DB0

description

9 10 11 12 13

The TLC7524C, TLC7524E, and TLC7524I are

CMOS, 8-bit, digital-to-analog converters (DACs)

designed for easy interface to most popular

microprocessors.

NC−No internal connection

The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random

access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,

which produce the highest glitch impulse. The devices provide accuracy to 1/2LSB without the need for thin-film

resistors or laser trimming, while dissipating less than 5mW typically.

Featuring operation from a 5V to 15V single supply, these devices interface easily to most microprocessor buses

or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many

microprocessor-controlled gain-setting and signal-control applications.

The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation

from −25°C to +85°C. The TLC7524E is characterized for operation from −40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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Copyright  1998−2007, Texas Instruments Incorporated

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1

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

functional block diagram

R

15

REF

2R

16

R

FB

S-1

S-2

S-3

S-8

R

1

2

OUT1

OUT2

12

13

CS

3

Data Latches

GND

WR

4

5

6

11

DB0

(LSB)

DB7

(MSB)

DB6

DB5

Data Inputs

Terminal numbers shown are for the D or N package.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V

DD

Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to V + 0.3V

I

DD

Reference voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

ref

Peak digital input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA

I

Operating free-air temperature range, T : TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

A

TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C

TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C

stg

Case temperature for 10 seconds, T : FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

C

Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . +260°C

package/ordering information

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI website at www.ti.com.

2

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

recommended operating conditions

V

= 5V

V

= 15V

DD

MIN NOM

DD

MIN NOM

UNIT

MAX

Supply voltage, V

DD

4.75

5

5.25

14.5

13.5

15

10

15.5

V

Reference voltage, V

ref

10

High-level input voltage, V

IH

2.4

V

Low-level input voltage, V

IL

0.8

1.5

V

CS setup time, t

40

0

40

0

ns

su(CS)

h(CS)

CS hold time, t

Data bus input setup time, t

su(D)

25

10

40

0

25

10

40

0

Data bus input hold time, t

h(D)

Pulse duration, WR low, t

w(WR)

TLC7524C

TLC7524I

TLC7524E

+70

+85

+70

+85

Operating free-air temperature, T

−25

−40

−25

−40

°C

A

electrical characteristics over recommended operating free-air temperature range, V = 10V,

ref

OUT1 and OUT2 at GND (unless otherwise noted)

V

DD

= 5V

V

= 15V

DD

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP MAX

MIN

TYP MAX

I

High-level input current

Low-level input current

V = V

DD

10

µA

IH

I

V = 0

I

−10

IL

DB0−DB7 at 0V,

10V

DB0−DB7 at V

WR, CS at 0V,

OUT1

OUT2

400

200

V

ref

=

Output leakage

current

I

nA

Ikg

DD

,

DD

V

ref

= 10V

Quiescent DB0−DB7 at V min or V max

1

2

mA

IH

IL

I

Supply current

Standby

DB0−DB7 at 0V or V

500

µA

DD

Supply voltage sensitivity,

∆gain/∆V

k

∆V

DD

=

10%

0.01

0.16

5

0.005

0.04 %FSR/%

SVS

DD

Input capacitance,

DB0−DB7, WR, CS

C

V = 0

I

5

pF

i

OUT1

OUT2

OUT1

OUT2

30

120

30

120

30

DB0−DB7 at 0V,

WR, CS at 0V

C

Output capacitance

pF

o

DB0−DB7 at V

DD

,

Reference input impedance

(REF to GND)

5

20

5

20

kΩ

3

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

operating characteristics over recommended operating free-air temperature range, V = 10V,

ref

OUT1 and OUT2 at GND (unless otherwise noted)

V

= 5V

DD

TYP

V

DD

= 15V

PARAMETER

TEST CONDITIONS

UNIT

TYP

MIN

MAX MIN

MAX

0.5

Linearity error

0.5

2.5

LSB

ns

Gain error

See Note 1

2.5

Settling time (to 1/2 LSB)

See Note 2

100

Propagation delay from digital input

to 90% of final analog output current

See Note 2

80

ns

Vref = 10V (100kHz sinewave)

WR and CS at 0V, DB0−DB7 at 0V

Feedthrough at OUT1 or OUT2

Temperature coefficient of gain

0.5

%FSR

T

= +25°C to MAX

0.004

0.001

%FSR/°C

A

NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = V − 1LSB.

ref

2. OUT1 load = 100Ω, C

= 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to V

or V to 0V.

ext

DD

operating sequence

t

su(CS)

t

h(CS)

CS

t

w(WR)

WR

t

su(D)

t

h(D)

DB0−DB7

4

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

voltage-mode operation

It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode,

a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the

reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage

mode.

R

REF (Analog Output Voltage)

2R

0

1

R

OUT1 (Fixed Input Voltage)

OUT2

Figure 1. Voltage Mode Operation

The relationship between the fixed-input voltage and the analog-output voltage is given by the following

equation:

V

= V (D/256)

I

O

where

V

= analog output voltage

= fixed input voltage

O

I

D = digital input code converted to decimal

In voltage-mode operation, these devices meet the following specification:

PARAMETER

Linearity error at REF

TEST CONDITIONS

MIN

MAX

UNIT

V

DD

= 5V, OUT1 = 2.5V, OUT2 at GND,

T

A

= +25°C

1

LSB

5

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,

analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2

bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order

bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted

current sources. Most applications only require the addition of an external operational amplifier and a voltage

reference.

The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference

current, I , is switched to OUT2. The current source I/256 represents the constant current flowing through the

ref

termination resistor of the R-2R ladder, while the current source I

represents leakage currents to the

Ikg

substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all

digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch

capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown

in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, I would

ref

be switched to OUT1.

The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control

signals. When CS and WR are both low, analog output on these devices responds to the data activity on the

DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the

analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched

until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state

of the WR signal.

These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for

2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input

coding for unipolar and bipolar operation respectively.

R

FB

R

OUT1

30 pF

I

Ikg

I

ref

REF

OUT2

120 pF

I/256

I

Ikg

Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low

6

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SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

V

ref

V

DD

R

= 2 kΩ

A

R

B

(see Note A)

C (see Note B)

R

FB

DB0−DB7

OUT1

OUT2

−

Output

CS

+

WR

GND

NOTES: A.

R and R used only if gain adjustment is required.

A B

B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent

ringing or oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multiplication)

V

DD

V

ref

20 kΩ

R

= 2 kΩ

A

R

B

20 kΩ

(see Note A)

−

+

C (see Note B)

R

FB

OUT1

Output

DB0−DB7

10 kΩ

−

+

CS

5 kΩ

OUT2

WR

GND

NOTES: A.

R and R used only if gain adjustment is required.

A B

B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation.

Figure 4. Bipolar Operation (4-Quadrant Operation)

Table 1. Unipolar Binary Code

Table 2. Bipolar (Offset Binary) Code

DIGITAL INPUT

(see Note 3)

(see Note 4)

ANALOG OUTPUT

MSB LSB

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

−V (255/256)

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

V

(127/128)

(1/128)

ref

−V (129/256)

ref

V

ref

−V (128/256) = −V /2

ref ref

−V (127/256)

ref

−V (1/256)

ref

0

−V (1/128)

ref

−V (127/128)

ref

−V

ref

NOTE 3: LSB = 1/256 (V

)

ref

NOTE 4: LSB = 1/128 (V

)

ref

7

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ꢊꢋ ꢌꢉ ꢀ ꢍ ꢎꢁꢀ ꢉ ꢏꢁꢐ ꢉ ꢑꢒ ꢓꢉ ꢒ ꢉ ꢀꢔꢁ ꢋꢀꢕ ꢋꢔꢑꢔ ꢁ ꢕꢒ ꢂꢕ ꢑꢖꢈ ꢗꢀ ꢈꢗꢘ

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

microprocessor interfaces

D0−D7

Z−80A

Data Bus

DB0−DB7

TLC7524

WR

OUT1

OUT2

WR

CS

Decode

Logic

IORQ

Address Bus

A0−A15

Figure 5. TLC7524: Z-80A Interface

Data Bus

D0−D7

6800

DB0−DB7

TLC7524

φ2

OUT1

OUT2

WR

CS

Decode

Logic

VMA

Address Bus

A0−A15

Figure 6. TLC7524: 6800 Interface

8

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ꢊ ꢋꢌꢉ ꢀ ꢍ ꢎꢁꢀ ꢉꢏ ꢁꢐꢉ ꢑꢒ ꢓꢉ ꢒꢉ ꢀꢔꢁ ꢋꢀꢕ ꢋꢔꢑꢔꢁ ꢕ ꢒ ꢂꢕ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢘ

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

PRINCIPLES OF OPERATION

microprocessor interfaces (continued)

A8−A15

8051

Address Bus

Decode

Logic

8-Bit

Latch

CS

OUT1

TLC7524

WR

OUT2

ALE

WR

DB0−DB7

Adress/Data Bus

AD0−AD7

Figure 7. TLC7524: 8051 Interface

9

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Revision History

DATE

REV

PAGE

Front Page

2

SECTION

DESCRIPTION

—

Deleted Available Options table.

Inserted Package/Ordering information.

6/07

D

:

NOTE Page numbers for previous revisions may differ from page numbers in the current version.

PACKAGE OPTION ADDENDUM

www.ti.com

28-May-2009

PACKAGING INFORMATION

Orderable Device

TLC7524CD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16

20

16

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC7524CDG4

TLC7524CDR

TLC7524CDRG4

TLC7524CFN

SOIC

PLCC

PDIP

SO

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

FN

N

46 Green (RoHS &

no Sb/Br)

CU SN

Level-1-260C-UNLIM

TLC7524CFNG3

TLC7524CFNR

TLC7524CFNRG3

TLC7524CN

46 Green (RoHS &

no Sb/Br)

1000 Green (RoHS &

no Sb/Br)

1000 Green (RoHS &

no Sb/Br)

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TLC7524CNE4

TLC7524CNS

N

25

Pb-Free

(RoHS)

NS

PW

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC7524CNSG4

TLC7524CNSR

TLC7524CNSRG4

TLC7524CPW

TLC7524CPWG4

TLC7524CPWR

TLC7524CPWRG4

TLC7524ED

SO

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

SOIC

PDIP

SOIC

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC7524EDG4

TLC7524EDR

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC7524EDRG4

TLC7524EN

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TLC7524ENE4

TLC7524ID

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-May-2009

Orderable Device

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TLC7524IDG4

TLC7524IDR

SOIC

D

16

20

16

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TLC7524IDRG4

TLC7524IFN

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PLCC

PDIP

FN

N

46 Green (RoHS &

no Sb/Br)

CU SN

Level-1-260C-UNLIM

TLC7524IFNG3

TLC7524IN

46 Green (RoHS &

no Sb/Br)

CU SN

Level-1-260C-UNLIM

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

TLC7524INE4

TLC7524IPW

TLC7524IPWG4

TLC7524IPWR

TLC7524IPWRG4

PDIP

N

25

Pb-Free

(RoHS)

TSSOP

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLC7524CDR

TLC7524CNSR

TLC7524CPWR

TLC7524EDR

TLC7524IDR

SOIC

SO

D

NS

PW

D

16

2500

2000

2500

2000

330.0

16.4

12.4

16.4

12.4

6.5

8.2

6.9

6.5

6.9

10.3

10.5

5.6

2.1

2.5

1.6

2.1

1.6

8.0

12.0

8.0

16.0

12.0

16.0

12.0

Q1

TSSOP

SOIC

TSSOP

10.3

5.6

D

TLC7524IPWR

PW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLC7524CDR

TLC7524CNSR

TLC7524CPWR

TLC7524EDR

TLC7524IDR

SOIC

SO

D

NS

PW

D

16

2500

2000

2500

2000

367.0

38.0

35.0

38.0

35.0

TSSOP

SOIC

TSSOP

D

TLC7524IPWR

PW

Pack Materials-Page 2

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLC7524EDR
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS 8位乘法数字 - 模拟转换器转换器
文件：	总21页 (文件大小：714K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC7524EDR [TI]

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