TLC7528EDWR [TI]
DUAL 8-BI MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS; 双8 -BI倍增数字 - 模拟转换器
| 型号： | TLC7528EDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 8-BI MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS |
| 文件： | 总27页 (文件大小：1031K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓ
ꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
DW, N OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
Easily Interfaced to Microprocessors
On-Chip Data Latches
Monotonic Over the Entire A/D Conversion
Range
AGND
OUTA
RFBA
REFA
DGND
OUTB
RFBB
REFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Interchangeable With Analog Devices
AD7528 and PMI PM-7528
V
DD
WR
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
DACA/DACB
(MSB) DB7
DB6
CS
DB0 (LSB)
DB1
D
D
Voltage-Mode Operation
CMOS Technology
DB5
DB2
DB4
DB3
KEY PERFORMANCE SPECIFICATIONS
FN PACKAGE
(TOP VIEW)
Resolution
Linearity Error
Power Dissipation at V
Settling Time at V
8 bits
1/2LSB
20mW
100ns
80ns
= 5V
DD
= 5V
DD
Propagation Delay Time at V
DD
= 5V
3
2 1 20 19
REFB
description
REFA
4
DGND
5
18
17
16
15
14
V
DD
The TLC7528C, TLC7528E, and TLC7528I are
dual, 8-bit, digital-to-analog converters (DACs)
designed with separate on-chip data latches and
feature exceptionally close DAC-to-DAC match-
ing. Data are transferred to either of the two DAC
data latches through a common, 8-bit, input port.
Control input DACA/DACB determines which
DAC is to be loaded. The load cycle of these
devices is similar to the write cycle of a
random-access memory, allowing easy interface
to most popular microprocessor buses and output
ports. Segmenting the high-order bits minimizes
glitches during changes in the most significant
bits, where glitch impulse is typically the
strongest.
WR
DACA/DACB
6
7
8
CS
(MSB) DB7
DB6
DB0 (LSB)
9 10 11 12 13
These devices operate from a 5V to 15V power supply and dissipates less than 15mW (typical). The 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than
a current output. Refer to the typical application information in this data sheet.
The TLC7528C is characterized for operation from 0°C to +70°C. The TLC7528I is characterized for operation
from −25°C to +85°C. The TLC7528E is characterized for operation from −40°C to +85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢐꢖ ꢔ ꢊꢋ ꢂ ꢀꢉ ꢔ ꢒ ꢊ ꢌꢀꢌ ꢘꢙ ꢚ ꢛꢜ ꢝ ꢞꢟ ꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟ ꢘꢛꢙ ꢧꢞ ꢟꢣ ꢨ
ꢐꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛ ꢜ ꢝ ꢟ ꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘ ꢛꢙꢠ ꢤꢣ ꢜ ꢟꢩ ꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢀꢣꢪ ꢞꢠ ꢉꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ
ꢠ ꢟ ꢞ ꢙꢧ ꢞ ꢜꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢐꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
Copyright 2000−2008, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
functional block diagram
14
DB0
REFA
4
3
2
13
12
11
RFBA
OUTA
8
8
Input
Data
DACA
Latch A
10
Buffer
Inputs
9
8
1
AGND
7
DB7
19
20
RFBB
OUTB
6
8
DACA/DACB
8
16
15
DACB
18
Latch B
Logic
Control
WR
CS
REFB
operating sequence
t
t
t
su(CS)
h(CS)
CS
t
)
su(DAC
h(DAC)
DACA/DACB
WR
t
w(WR)
t
t
h(D)
su(D)
Data In Stable
DB0−DB7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V
DD
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to V
V
DD
+ 0.3
DD
I
Reference voltage, V
Feedback voltage V
or V
or V
(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
refA
RFBA
refB
(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
RFBB
Input voltage (voltage mode out A, out B to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to V
+ 0.3
DD
Output voltage, V
or V
(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
OA
OB
Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA
Operating free-air temperature range, T : TLC7528C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A
TLC7528I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C
TLC7528E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C
stg
Case temperature for 10 seconds, T : FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
C
Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . +260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
package/ordering information
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
recommended operating conditions
V
= 4.75V to 5.25V
V
DD
MIN
= 14.5V to 15.5V
DD
UNIT
MIN
NOM
MAX
NOM
MAX
Reference voltage, V
refA
or V
refB
10
10
V
High-level input voltage, V
IH
2.4
13.5
V
Low-level input voltage, V
IL
0.8
1.5
V
CS setup time, t
50
0
50
0
ns
ns
ns
ns
ns
ns
ns
su(CS)
CS hold time, t
h(CS)
DAC select setup time, t
50
10
25
10
50
0
50
10
25
10
50
0
su(DAC)
DAC select hold time, t
h(DAC)
Data bus input setup time t
su(D)
Data bus input hold time t
h(D)
Pulse duration, WR low, t
w(WR)
TLC7628C
TLC7628I
TLC7628E
+70
+85
+85
+70
+85
+85
Operating free-air temperature, T
−25
−40
−25
−40
°C
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
electrical characteristics over recommended operating free-air temperature range,
= V = 10V, V and V at 0V (unless otherwise noted)
V
refA
refB
OA
OB
V
= 5V
V
= 15V
DD
DD
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
10
MAX
10
I
I
High-level input current
Low-level input current
V = V
DD
µA
µA
IH
I
V = 0
5
12
−10
5
12
−10
IL
I
Reference input impedance
REFA or REFB to AGND
20
400
400
20
200
200
kΩ
DAC data latch loaded with
00000000, V 10V
OUTA
OUTB
=
refA
DAC data latch loaded with
00000000, V 10V
I
Output leakage current
nA
Ikg
=
refB
Input resistance match
(REFA to REFB)
1%
0.04
2
1%
0.02
2
DC supply sensitivity, ∆gain/∆V
Supply current (quiescent)
Supply current (standby)
∆V
DD
=
10%
%/%
mA
DD
All digital inputs at V min or
IH
I
I
DD
V max
IL
All digital inputs at 0V or V
DD
0.5
10
0.5
10
mA
pF
DD
DB0−DB7
C
C
Input capacitance
WR, CS,
DACA/DACB
i
15
50
15
50
pF
DAC data latches loaded with
00000000
Output capacitance (OUTA, OUTB)
pF
o
DAC data latches loaded with
11111111
120
120
†
All typical values are at T = +25°C.
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
operating characteristics over recommended operating free-air temperature range,
= V = 10V, V and V at 0V (unless otherwise noted)
V
refA
refB
OA
OB
V
= 5V
DD
TYP
V
= 15V
DD
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
1/2
MIN
MAX
1/2
Linearity error
LSB
ns
Settling time (to 1/2LSB)
Gain error
See Note 1
See Note 2
100
100
2.5
2.5
LSB
REFA to OUTA
REFB to OUTB
−65
−65
0.007
−65
−65
AC feedthrough
See Note 3
See Note 4
See Note 5
dB
Temperature coefficient of gain
0.0035 %FSR/°C
Propagation delay (from digital input to
90% of final analog output current)
80
80
ns
REFA to OUTB See Note 6
REFB to OUTA See Note 7
77
77
77
77
Channel-to-channel
isolation
dB
Measured for code transition from
00000000 to 11111111,
= +25°C
Digital-to-analog glitch impulse area
Digital crosstalk
160
440
nV−s
T
A
Measured for code transition from
00000000 to 11111111,
30
60
nV−s
dB
T
A
= +25°C
Harmonic distortion
V = 6V, f = 1kHz,
i
T
A
= +25°C
−85
−85
NOTES: 1. OUTA, OUTB load = 100Ω, C
= 13pF; WR and CS at 0V; DB0−DB7 at 0V to V
DD
or V to 0V.
DD
ext
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = V − 1LSB.
ref
3.
4. Temperature coefficient of gain measured from 0°C to +25°C or from +25°C to +70°C.
5. = V = 10V; OUTA/OUTB load = 100Ω, C = 13pF; WR and CS at 0V; DB0−DB7 at 0V to V
V
ref
= 20V peak-to-peak, 100kHz sine wave; DAC data latches loaded with 00000000.
V
refA
or V to 0V.
DD
refB ext DD
6. Both DAC latches loaded with 11111111; V
7. Both DAC latches loaded with 11111111; V
= 20V peak-to-peak, 100kHz sine wave; V
= 20V peak-to-peak, 100kHz sine wave; V
= 0; T = +25°C.
= 0; T = +25°C.
refA
refB
refB
refA
A
A
PRINCIPLES OF OPERATION
These devices contain two identical, 8-bit-multiplying DACs, DACA and DACB. Each DAC consists of an
inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between
DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state.
Most applications require only the addition of an external operational amplifier and voltage reference. A
simplified DAC circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUTA. A small leakage current (I ) flows across internal junctions, and as with most semiconductor devices,
Ikg
doubles every 10°C. C is due to the parallel combination of the NMOS switches and has a value that depends
o
on the number of switches connected to the output. The range of C is 50pF to 120pF maximum. The equivalent
o
output resistance (r ) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder
o
resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line,
responds to the activity on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0−DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled regardless of the state of the WR signal.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉ
ꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
PRINCIPLES OF OPERATION
The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5V. These
devices can operate with any supply voltage in the range from 5V to 15V; however, input logic levels are not
TTL-compatible above 5V.
R
R
R
REFA
2R
2R
2R
2R
2R
R
FB
RFBA
S1
S2
S3
S8
OUTA
AGND
DACA Data Latches and Drivers
Figure 1. Simplified Functional Circuit for DACA
RFBA
R
FB
R
OUTA
REFA
I
C
I
OUT
Ikg
256
AGND
Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111
MODE SELECTION TABLE
DACA/DACB CS WR DACA
DACB
L
H
X
X
L
L
H
X
L
L
X
H
Write
Hold
Hold
Hold
Hold
Write
Hold
Hold
L = low level, H = high level, X = don’t care
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize
input coding for unipolar and bipolar operation, respectively.
V
I(A)
10 V
R1 (see Note A)
R2 (see Note A)
C1
RFBA
OUTA
AGND
17
14
(see Note B)
V
DD
REFA
DB0
−
+
8
Input
Buffer
8
V
OA
DACA
Latch
DB7
7
R4 (see Note A)
C2
RFBB
OUTB
(see Note B)
8
6
15
16
5
−
DACA/DACB
8
Control
Logic
DACB
Latch
V
OB
CS
+
WR
AGND
REFB
AGND
DGND
RECOMMENDED TRIM
RESISTOR VALUES
R3 (see Note A)
V
I(B)
10 V
R1, R3 500 Ω
R2, R4 150 Ω
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10pF to 15pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.
Figure 3. Unipolar Operation (2-Quadrant Multiplication)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
V
10 V
R6
20 kΩ
I(A)
(see Note B)
R1
R2 (see Note A)
C1
(see Note A)
RFBA
OUTA
R5
20 kΩ
17
14
(see Note C)
V
DD
R7
10 kΩ
DB0
−
Input
Buffer
8
8
DACA
Latch
A1
+
−
A2
+
AGND
(see Note B)
DB7
V
OA
7
6
R11
5 kΩ
R4 (see Note A)
C2
RFBB
DACA/
DACB
R8
20 kΩ
Control
Logic
15
CS
(see Note C)
16
5
−
OUTB
AGND
WR
8
8
−
DACB
REFB
Latch
A3
+
A4
+
V
OB
R9
10 kΩ
(see Note B)
DGND
AGND
R11
5 kΩ
R3
AGND
(see Note A)
R10
V
I(B)
10 V
20 kΩ
(see Note B)
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for
= 0V with code 10000000 in DACA latch. Adjust R3 for V = 0V with 10000000 in DACB latch.
V
OA
OB
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10pF to 15pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 4. Bipolar Operation (4-Quadrant Operation)
Table 1. Unipolar Binary Code
Table 2. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
DAC LATCH CONTENTS
ANALOG OUTPUT
ANALOG OUTPUT
†
LSB
‡
LSB
MSB
MSB
1 1 1 1 1 1 1 1
−V (255/256)
1 1 1 1 1 1 1 1
V (127/128)
I
I
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
−V (129/256)
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
V (1/128)
I
I
−V (128/256) = −V /2
0V
I
i
−V (127/256)
−V (1/128)
I
I
−V (1/256)
−V (127/128)
I
I
−V (0/256) = 0
−V (128/128)
I
I
†
−8
1LSB = (2 )V
‡
−7
1LSB = (2 )V
I
I
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
microprocessor interface information
8
Address Bus
A8−A15
DACA/DACB
CS
A
Address
Decode
Logic
A + 1
TLC7528
WR
CPU
8051
DB0
WR
DB7
ALE
Latch
8
Data Bus
AD0−AD7
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
Figure 5. TLC7528: Intel 8051 Interface
8
Address Bus
A8−A15
VMA
DACA/DACB
CS
A
Address
Decode
Logic
A + 1
TLC7528
WR
CPU
6800
DB0
DB7
φ2
8
Data Bus
AD0−AD7
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
Figure 6. TLC7528: 6800 Interface
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
8
Address Bus
A8−A15
IORQ
DACA/DACB
A
Address
Decode
CS
TLC7528
WR
Logic
A + 1
CPU
Z80-A
DB0
DB7
WR
8
Data Bus
D0−D7
NOTE A: A = decoded address for TLC7528 DACA
A + 1 = decoded address for TLC7528 DACB
Figure 7. TLC7528 To Z-80A Interface
programmable window detector
The programmable window comparator shown in Figure 8 determines if the voltage applied to the DAC
feedback resistors is within the limits programmed into the data latches of these devices. Input signal range
depends on the reference and polarity; that is, the test input range is 0 to −V . The DACA and DACB data
ref
latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the
output high.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
V
DD
V
CC
Test Input
0 to −V
3
17
ref
RFBA
1 kΩ
OUTA
2
−
+
4
14−7
15
DACA
REFA
8
Data Inputs
DB0−DB7
TLC7528
1
PASS/FAIL Output
CS
AGND
16
6
WR
DACA/DACB
OUTB
20
−
+
18
5
REFB
V
ref
DACB
DGND
RFBB
19
Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester)
digitally-controlled signal attenuator
Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo
audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0dB to 15.5dB range.
Attenuation dB = −20 log D/256, D = digital input code
10
RFBA
OUTA
3
2
17
4
V
DD
REFA
V A
I
DACA
A1
8
Output
14−7
DB0−DB7
Data Bus
TLC7528
15
16
6
CS
WR
DACA/DACB
OUTB
RFBB
20
19
REFB 18
DACB
A2
V
O
B
1
AGND
5
DGND
Figure 9. Digitally Controlled Dual Telephone Attenuator
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
Table 3. Attenuation vs DACA, DACB Code
CODE IN
CODE IN
DECIMAL
ATTEN (dB)
DAC INPUT CODE
ATTN (dB)
DAC INPUT CODE
DECIMAL
255
242
228
215
203
192
181
171
162
152
144
136
128
121
114
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
1 1 1 1 1 1 1 1
1 1 1 1 0 0 1 0
1 1 1 0 0 1 0 0
1 1 0 1 0 1 1 1
1 1 0 0 1 0 1 1
1 1 0 0 0 0 0 0
1 0 1 1 0 1 0 1
1 0 1 0 1 0 1 1
1 0 1 0 0 0 1 0
1 0 0 1 1 0 0 0
1 0 0 1 1 1 1 1
1 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0
0 1 1 1 1 0 0 1
0 1 1 1 0 0 1 0
0 1 1 0 1 1 0 0
8.0
8.5
0 1 1 0 0 1 1 0
0 1 1 0 0 0 0 0
0 1 0 1 1 0 1 1
0 1 0 1 0 1 1 0
0 1 0 1 0 0 0 1
0 1 0 0 1 1 0 0
0 1 0 0 1 0 0 0
0 1 0 0 0 1 0 0
0 1 0 0 0 0 0 0
0 0 1 1 1 1 0 1
0 0 1 1 1 0 0 1
0 0 1 1 0 1 1 0
0 0 1 1 0 0 1 1
0 0 1 1 0 0 0 0
0 0 1 0 1 1 1 0
0 0 1 0 1 0 1 1
102
96
91
86
81
76
72
68
64
61
57
54
51
48
46
43
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
108
programmable state-variable filter
This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass
outputs, and is suitable for applications requiring microprocessor control of filter parameters.
As shown in Figure 10, DACA1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control
the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the
cutoff-frequency equation to be true. With the TLC7528, this validity is easy to achieve.
1
f +
c
2p R1C1
The programmable range for the cutoff or center frequency is 0kHz to 15kHz with a Q ranging from 0.3 to 4.5.
This parameter defines the limits of the component values.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢈ
ꢊꢋꢌ ꢁ ꢆ ꢍꢎꢉ ꢀ ꢏ ꢋꢁꢀꢉ ꢐ ꢁꢑ ꢉꢒ ꢓ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢊ
ꢉ
ꢓꢉ
ꢀ
ꢌ
ꢁ
ꢍ
ꢀ
ꢔ
ꢍ
ꢌ
ꢒ
ꢌ
ꢁ
ꢔ
ꢓ
ꢂ
ꢔ
ꢒ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
C3
47 pF
R5
4
2
REFA
OUTA
V
I
DACA
(R )
S
17
Ω
30 k
V
3
1
A1
DD
+
RFBA
AGND
R4
8
Data In
Ω
30 k
TLC7528
DACB
R3
15
16
5
CS
20
19
High Pass
Out
OUTB
A2
Ω
10 k
+
WR
(R )
F
RFBB
REFB
DGND
18
6
DACA/DACB
Bandpass Out
DACA1 AND DACB1
C1
1000 pF
2
4
REFA
OUTA
DACA
(R )
1
17
A3
+
V
3
1
DD
C2
RFBA
AGND
8
Data In
TLC7528
DACB
1000 pF
15
16
5
CS
20
19
OUTB
WR
(R )
2
Low Pass Out
A4
+
RFBB
REFB
DGND
18
6
DACA/DACB
DACA2 and DACB2
Circuit Equations:
C
= C , R = R , R = R
1
2
1
2
4
5
R
R
R
3
4
F
Q =
R
fb(DACB1)
Where:
R
is the internal resistor connected between OUTB and RFBB
fb
R
F
−
G
R
S
NOTES: A. Op-amps A1, A2, A3, and A4 are TL287.
B. CS compensates for the op-amp gain-bandwidth limitations.
256 (DAC ladder resistance)
C. DAC equivalent resistance equals
DAC digital code
Figure 10. Digitally-Controlled State-Variable Filter
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢊ
ꢊ
ꢁ
ꢋ
ꢂ
ꢌ
ꢉ
ꢃ
ꢁ
ꢀ
ꢄ
ꢆ
ꢌ
ꢅ
ꢍ
ꢁ
ꢆ
ꢎ
ꢍ
ꢂ
ꢉ
ꢇ
ꢀ
ꢀ
ꢏ
ꢁ
ꢂ
ꢋ
ꢒ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢓ
ꢈ
ꢑ
ꢇ
ꢀ
ꢁ
ꢓ
ꢒ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢉ
ꢁ
ꢀ
ꢉ
ꢐ
ꢉ
ꢒ
ꢉꢓ
ꢀꢔ
ꢍ
ꢌ
ꢌ
ꢁ
ꢔ
ꢂ
ꢔ
ꢕ
ꢈ
ꢖ
ꢀ
ꢈ
ꢖ
ꢗ
SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008
APPLICATION INFORMATION
voltage-mode operation
It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at
the reference voltage terminal. Figure 11 is an example of a current multiplying D/A that operates in the voltage
mode.
R
R
R
REF
(Analog Output Voltage)
2R
2R
2R
2R
R
“0”
“1”
Out (Fixed Input Voltage)
AGND
Figure 11. Voltage-Mode Operation
The following equation shows the relationship between the fixed input voltage and the analog output voltage:
V
= V (D/256)
I
O
Where:
V
= analog output voltage
O
V = fixed input voltage (must not be forced below 0V.)
I
D = digital input code converted to decimal
In voltage-mode operation, these devices meet the following specification:
PARAMETER
Linearity error at REFA or REFB
TEST CONDITIONS
MIN
MAX
UNIT
V
DD
= 5V, OUTA or OUTB at 2.5V,
T
A
= +25°C
1
LSB
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Revision History
DATE
REV
PAGE
SECTION
DESCRIPTION
11/08
E
13
Front Page
3
ApplicationInformation
Corrected Figure 10.
—
—
Deleted Available Options table.
6/07
D
Inserted Package/Ordering information.
:
NOTE Page numbers for previous revisions may differ from page numbers in the current version.
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
TLC7528CDW
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
SOIC
SOIC
PLCC
PLCC
PLCC
PLCC
PDIP
PDIP
SO
DW
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC7528C
TLC7528C
TLC7528C
TLC7528C
TLC7528C
TLC7528C
TLC7528C
TLC7528C
TLC7528CN
TLC7528CN
TLC7528
TLC7528CDWG4
TLC7528CDWR
TLC7528CDWRG4
TLC7528CFN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
FN
FN
FN
FN
N
Green (RoHS
& no Sb/Br)
2000
2000
46
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLC7528CFNG3
TLC7528CFNR
TLC7528CFNRG3
TLC7528CN
46
Green (RoHS
& no Sb/Br)
CU SN
1000
1000
20
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
TLC7528CNE4
TLC7528CNS
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
NS
NS
NS
NS
PW
PW
PW
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TLC7528CNSG4
TLC7528CNSR
TLC7528CNSRG4
TLC7528CPW
SO
40
Green (RoHS
& no Sb/Br)
TLC7528
SO
2000
2000
70
Green (RoHS
& no Sb/Br)
TLC7528
SO
Green (RoHS
& no Sb/Br)
TLC7528
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
TLC7528C
TLC7528C
TLC7528C
TLC7528CPWG4
TLC7528CPWR
70
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
TLC7528CPWRG4
TLC7528EDW
TLC7528EDWG4
TLC7528EDWR
TLC7528EDWRG4
TLC7528EN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
SOIC
SOIC
SOIC
SOIC
PDIP
PW
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC7528C
TLC7528E
TLC7528E
TLC7528E
TLC7528E
TLC7528EN
TLC7528EN
TLC7528I
TLC7528I
TLC7528I
TLC7528I
TLC7528I
TLC7528I
TLC7528IN
TLC7528IN
TLC7528I
TLC7528I
TLC7528I
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
-25 to 85
25
Green (RoHS
& no Sb/Br)
2000
2000
20
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
TLC7528ENE4
TLC7528IDW
PDIP
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
PLCC
PLCC
PDIP
DW
DW
DW
DW
FN
FN
N
25
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC7528IDWG4
TLC7528IDWR
TLC7528IDWRG4
TLC7528IFN
25
Green (RoHS
& no Sb/Br)
2000
2000
46
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLC7528IFNG3
TLC7528IN
46
Green (RoHS
& no Sb/Br)
CU SN
20
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
TLC7528INE4
TLC7528IPW
PDIP
N
20
Pb-Free
(RoHS)
N / A for Pkg Type
TSSOP
TSSOP
TSSOP
PW
PW
PW
70
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TLC7528IPWG4
TLC7528IPWR
70
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
TLC7528IPWRG4
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-25 to 85
TLC7528I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC7528CNSR
TLC7528EDWR
TLC7528IDWR
TLC7528IPWR
SO
NS
DW
DW
PW
20
20
20
20
2000
2000
2000
2000
330.0
330.0
330.0
330.0
24.4
24.4
24.4
16.4
8.2
13.0
13.3
13.3
7.1
2.5
2.7
2.7
1.6
12.0
12.0
12.0
8.0
24.0
24.0
24.0
16.0
Q1
Q1
Q1
Q1
SOIC
SOIC
TSSOP
10.8
10.8
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC7528CNSR
TLC7528EDWR
TLC7528IDWR
TLC7528IPWR
SO
NS
DW
DW
PW
20
20
20
20
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
38.0
SOIC
SOIC
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
TLC7528EFNR
DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.1us SETTLING TIME, 8-BIT DAC, PQCC20, PLASTIC, LCC-20
TI
TLC7528EPWR
DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.1us SETTLING TIME, 8-BIT DAC, PDSO20, TSSOP-20
TI
©2020 ICPDF网 联系我们和版权申明