TLC7705QPWREP [TI]
MICROPOWER SUPPLY VOLTAGE SUPERVISORS; 微功率电源电压监控器
| 型号： | TLC7705QPWREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MICROPOWER SUPPLY VOLTAGE SUPERVISORS |
| 文件： | 总11页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢀ ꢁꢂ ꢃ ꢃ ꢄꢊ ꢆꢇ ꢈꢉ ꢀ ꢁꢂ ꢃꢃ ꢋꢋ ꢆꢇ ꢈ
ꢌ ꢍꢂꢎꢏ ꢈ ꢏꢐ ꢇꢎ ꢑꢒ ꢈꢈꢁꢓ ꢔꢏ ꢁꢀꢕꢖ ꢇ ꢑꢒꢈ ꢇ ꢎꢔ ꢍꢑ ꢏ ꢎ ꢑ
ꢗ
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
D
D
Temperature-Compensated Voltage
Reference
Programmable Delay Time by External
Capacitor
D
D
D
D
D
D
Extended Temperature Performance of
−40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Supply Voltage Range . . . 2 V to 6 V
Defined RESET Output from V
≥1 V
DD
Power-Down Control Support for Static
RAM With Battery Backup
Enhanced Product Change Notification
†
Qualification Pedigree
D
Maximum Supply Current of 16 µA
Power Saving Totem-Pole Outputs
Power-On Reset Generator
D
Automatic Reset Generation After
Voltage Drop
PW PACKAGE
(TOP VIEW)
D
Precision Voltage Sensor
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
CONTROL
RESIN
CT
V
DD
1
2
3
4
8
7
6
5
SENSE
RESET
RESET
GND
description
The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer
and microprocessor systems.
During power-on, RESET is asserted when V
circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (V
remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure
reaches 1 V. After minimum V
(≥ 2 V) is established, the
DD
DD
)
I(SENSE)
proper system reset. The delay time, t , is determined by an external capacitor:
d
4
t = 2.1 × 10 × C
d
T
Where
C is in farads
T
t is in seconds
d
Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed
SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold
voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage
and the delay time, t , has expired.
d
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control
support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor
contains additional logic intended for control of static memories with battery backup during power failure. By
driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL
driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is
automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the
battery.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇꢈꢉ ꢀ ꢁ ꢂꢃ ꢃ ꢄ ꢊ ꢆꢇ ꢈꢉ ꢀꢁ ꢂꢃ ꢃ ꢋ ꢋ ꢆꢇ ꢈ
ꢌ ꢍ ꢂꢎ ꢏꢈꢏꢐꢇ ꢎ ꢑ ꢒꢈ ꢈꢁꢓ ꢔ ꢏꢁꢀꢕꢖ ꢇ ꢑ ꢒꢈꢇ ꢎꢔꢍ ꢑꢏ ꢎꢑ
ꢗ
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
†
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
TSSOP − PW
TSSOP − PW
TSSOP − PW
Tape and reel
Tape and reel
Tape and reel
TLC7701QPWREP
TLC7705QPWREP
TLC7733QPWREP
7701QE
−40°C to 125°C
7705QE
7733QE
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type;
e.g., TLC7701QPWREP).
FUNCTION TABLE
¶
logic symbol
CONTROL
V
>V
RESET
RESIN
RESET
I(SENSE) IT+
≥1
COMP
S<V
7
2
3
L
L
L
L
False
True
H
H
H
L
L
L
S
SENSE
RESIN
CT
IT
V
Z1
IT
L
H
H
L
False
True
§
L
§
H
L
1
Z2
Z3
H
H
H
H
False
True
H
L
×
CX
1
L
H
H
H
L
L
≥1
≥1
5
6
RESET
RESET
H
H
False
True
2
1
§
H
CONTROL
§
RESET and RESET states shown are valid for t > t .
3
d
¶
This symbol is in accordance with ANSI/IEEE Std 91−1984 and
IEC Publication 617-12.
functional block diagram
8
V
DD
1
CONTROL
6
†
RESET
50 µA
5
†
RESET
2
RESIN
‡
R1
7
SENSE
1 MΩ
‡
R2
1.1 V
4
GND
3
CT
†
‡
Outputs are totem-pole configuration. External pullup or pulldown resistors are not required.
Nominal values:
R1 (Typ)
0
R2 (Typ)
∞
TLC7701
TLC7705 910 kΩ
TLC7733 750 kΩ
290 kΩ
450 kΩ
2
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
timing diagram
V
DD
and V
I(SENSE)
V
IT+
V
IT+
Threshold Voltages
V
IT−
V
res
t
t
d
t
d
RESET
Output
Output
Undefined
t
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Input voltage range, CONTROL, RESIN, SENSE (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Maximum low output current, I
Maximum high output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 mA
OL
OH
Input clamp current, I (V < 0 or V > V )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 mA
10 mA
IK
OK
I
I
DD
O
Output clamp current, I
O
DD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TL77xxQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 85°C
T = 125°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
PW
525 mW
4.2 mW/°C
273 mW
105 mW
recommended operating conditions at specified temperature range
MIN
2
MAX
UNIT
V
Supply voltage, V
DD
6
Input voltage, V
0
V
DD
V
I
‡
0.7×V
V
High-level input voltage at RESIN and CONTROL , V
DD
IH
‡
0.2×V
−2
V
Low-level input voltage at RESIN and CONTROL , V
DD
IL
High-level output current, I
mA
mA
ns/V
°C
OH
V
≥ 2.7 V
DD
Low-level output current, I
2
OL
Input transition rise and fall rate at RESIN and CONTROL, ∆t/∆V
Operating free-air temperature range, T
100
125
−40
A
‡
To ensure a low supply current, V should be kept <0.3 V and V > V
IL IH DD
−0.3 V.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
TLC77xx
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
MIN
1.8
2.5
4.3
3.7
MAX
V
V
V
V
V
V
V
V
= 2 V
DD
DD
DD
DD
DD
DD
DD
DD
= 2.7 V
= 4.5 V
= 4.5 V
= 2 V
I
= −20 µA
OH
V
OH
High-level output voltage
V
I
= −2 mA
OH
0.2
0.2
= 2.7 V
= 4.5 V
= 4.5 V
I
= 20 µA
OL
OL
V
V
Low-level output voltage
V
V
OL
0.2
I
= 2 mA
0.5
TLC7701
TLC7705
TLC7733
TLC7701
TLC7705
TLC7733
1.04
4.43
1.1
4.5
1.16
4.63
3.03
Negative-going input threshold voltage,
SENSE (see Note 3)
V
DD
= 2 V to 6 V
= 2 V to 6 V
IT−
2.855
2.93
30
V
V
Hysteresis voltage, SENSE
V
I
mV
V
hys
DD
70
‡
= 20 µA
1
Power-up reset voltage
res
OL
V = 0 V to V
I
2
15
10
2
RESIN
DD
V = V
7
5
CONTROL
I
DD
Input current
SENSE
I
µA
µA
I
V = 5 V
I
SENSE, TLC7701 only
V = 5 V
I
RESIN = V
SENSE = V
,
DD
≥ V max + 0.2 V
IT
I
I
Supply current
9
16
DD
DD
CONTROL = 0 V, Outputs open
V
DD
= 5 V, = 0 ,
V
CT
SENSE = V ,
DD
Supply current during t
RESIN = V
DD
CONTROL = 0 V, Outputs open
,
120
50
150
µA
DD(d)
d
C
Input capacitance, SENSE
V = 0 V to V
I
pF
I
DD
†
‡
Typical values apply at T = 25°C.
The lowest supply voltage at which RESET becomes active. The symbol V
semiconductor symbology. Rise time of V ≥ 15 µs/V.
A
is not currently listed within EIA or JEDEC standards for
res
DD
NOTES: 2. All characteristics are measured with C = 0.1 µF.
T
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be connected near the supply terminals.
4
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
switching characteristics at V
noted)
= 5 V, R = 2 kΩ, C = 50 pF, T = Full Range (unless otherwise
DD
L
L
A
MEASURED
TLC77xx
TYP
PARAMETER
TO
TEST CONDITIONS
UNIT
FROM
(INPUT)
MIN
MAX
(OUTPUT)
RESIN = 0.7 × V
DD
,
RESET
and
CONTROL = 0.2 × V ,
DD
C = 100 nF,
T
t
d
Delay time
V
≥ V
IT+
1.1
2.1
4.2
ms
I(SENSE)
RESET
T
A
= Full range,
See timing diagram
Propagation delay time,
low-to-high-level output
t
t
t
t
t
t
t
t
20
5
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
RESET
RESET
RESET
RESET
V
V
= V max + 0.2 V,
IT+
= V min − 0.2 V,
IT−
IH
Propagation delay time,
high-to-low-level output
IL
SENSE
RESIN = 0.7 × V
DD
CONTROL = 0.2 × V
,
µs
Propagation delay time,
low-to-high-level output
5
,
DD
†
CT = NC
Propagation delay time,
high-to-low-level output
20
20
60
65
20
Propagation delay time,
low-to-high-level output
µs
V
V
= 0.7 × V ,
DD
IH
Propagation delay time,
high-to-low-level output
= 0.2 × V
,
IL
DD
RESIN
SENSE = V max + 0.2 V,
ns
IT+
Propagation delay time,
low-to-high-level output
CONTROL = 0.2 × V
DD
CT = NC
,
†
Propagation delay time,
high-to-low-level output
µs
V
V
= 0.7 × V
,
DD
IH
Propagation delay time,
low-to-high-level output
t
58
58
ns
PLH
PHL
= 0.2 × V
,
IL
DD
CONTROL
RESET
SENSE = V max + 0.2 V,
IT+
RESIN = 0.7 × V
DD
Propagation delay time,
high-to-low-level output
,
t
ns
†
CT = NC
V
V
= V max + 0.2 V,
IT+
= V min − 0.2 V,
IT−
IH
IL
SENSE
RESIN
3
1
Low-level minimum pulse
duration to switch RESET
and RESET
µs
V
V
= 0.2 × V ,
DD
= 0.7 × V
DD
IL
IH
RESET
and
t
t
Rise time
Fall time
10% to 90%
90% to 10%
8
4
r
ns/V
f
RESET
†
NC = No capacitor, and includes up to 100-pF probe and jig capacitance.
5
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
5 V
DUT
R
L
C
L
(see Note A)
(see Note B)
NOTES: A. For switching characteristics, R = 2 kΩ.
L
B.
C = 50 pF includes jig and probe capacitance.
L
Figure 1. RESET AND RESET Output Configurations
I, Q, and Y suffixed devices
t
w(L)
0.7 × V
0.5 × V
0.2 × V
DD
DD
DD
M suffixed devices
t
t
w(L)
w(L)
2.7 V
1.5 V
0.4 V
V
V
V
max + 200 mV
IT+
IT+
V
IT−
min − 200 mV
IT−
(a) RESIN
(b) SENSE
Figure 2. Input Pulse Definition Waveforms
6
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ꢌ ꢍꢂꢎꢏ ꢈ ꢏꢐ ꢇꢎ ꢑꢒ ꢈꢈꢁꢓ ꢔꢏ ꢁꢀꢕꢖ ꢇ ꢑꢒꢈ ꢇ ꢎꢔ ꢍꢑ ꢏ ꢎ ꢑ
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
NORMALIZED INPUT THRESHOLD VOLTAGE
SUPPLY CURRENT
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
10
9
1.005
1.004
8
1.003
1.002
7
6
5
1.001
1
4
3
RESIN = V
= −1 V to 6.5 V
SENSE = GND
DD
2
0.999
0.998
0.997
CONTROL = GND
CT = Open = 100 pF
1
0
T
A
= 25°C
−1
−40
−20
0
20
40
60
80
100 120
−0.5
0.5
1.5
2.5
3.5
4.5
5.5
6.5
T
A
− Temperature − °C
V
DD
− Supply Voltage − V
Figure 3
Figure 4
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
6
5
5
4.5
4
V
= 4.5 V
DD
RESIN = 4.5 V
SENSE = 5 V
CONTROL = 0 V
CT = Open = 100 pF
0°C
3.5
3
4
3
−55°C
125°C
85°C
125°C
85°C
25°C
0°C
2.5
2
25°C
−40°C
2
1
0
1.5
1
−40°C
−55°C
V
DD
= 4.5 V
RESIN = 4.5 V
SENSE = 0.5 V
CONTROL = 0 V
CT = Open = 100 pF
0.5
0
−0.5
−1
−5
−1
0
5
10
15
20
25
30
5
0
−5 −10 −15 −20 −25 −30 −35 −40
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
Figure 5
Figure 6
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢇꢈꢉ ꢀ ꢁ ꢂꢃ ꢃ ꢄ ꢊ ꢆꢇ ꢈꢉ ꢀꢁ ꢂꢃ ꢃ ꢋ ꢋ ꢆꢇ ꢈ
ꢌ ꢍ ꢂꢎ ꢏꢈꢏꢐꢇ ꢎ ꢑ ꢒꢈ ꢈꢁꢓ ꢔ ꢏꢁꢀꢕꢖ ꢇ ꢑ ꢒꢈꢇ ꢎꢔꢍ ꢑꢏ ꢎꢑ
ꢗ
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE AT SENSE
8
V
= 4.5 V
DD
6
4
2
CT = Open = 100 pF
125°C
−55°C
0
−2
125°C
−55°C
−4
−6
−8
−10
−1
0
1
2
3
4
5
6
V − Input Voltage at SENSE − V
I
Figure 7
MINIMUM PULSE DURATION AT SENSE
vs
SENSE THRESHOLD OVERDRIVE
7
V
DD
= 2 V
Control = 0.4 V
RESIN = 1.4 V
CT = Open = 100 pF
6
5
4
3
2
1
0
0
50
100 150 200 250 300 350 400
Sense Threshold Overdrive − mV
Figure 8
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢀ ꢁꢂ ꢃ ꢃ ꢄꢊ ꢆꢇ ꢈꢉ ꢀ ꢁꢂ ꢃꢃ ꢋꢋ ꢆꢇ ꢈ
ꢌ ꢍꢂꢎꢏ ꢈ ꢏꢐ ꢇꢎ ꢑꢒ ꢈꢈꢁꢓ ꢔꢏ ꢁꢀꢕꢖ ꢇ ꢑꢒꢈ ꢇ ꢎꢔ ꢍꢑ ꢏ ꢎ ꢑ
ꢗ
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
V
DD
0.1 µF
0.1 µF
100 kΩ
V
DD
V
DD
TLC77xx
RESIN RESET
RESET
SENSE RESET
CT CONTROL
GND
TMS70C20
GND
NC
RESET
Figure 9. Reset Controller in a Microcomputer System
V
DD
0.1 µF
V
DD
TLC77xx
RESIN
0.1 µF
0.1 µF
SENSE
RESET
CONTROL
RESET
GND
V
DD
CT
RESET
CSH1
CS
32K ꢀ 8
CMOS RAM
TMS370
16
8
A0−A15
D0−D7
R/W
ADD0−15
DATA0−7
R/W
GND
GND
Figure 10. Data Retention During Power Down Using Static CMOS RAMs
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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