TLC976C [TI]
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR; 10位， 20 MSPS ，区CCD信号处理器
| 型号： | TLC976C |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR |
| 文件： | 总17页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
DGG PACKAGE
(TOP VIEW)
Correlated Double Sampling (CDS), AGC
and High Speed 10-Bit ADC in a Single
Package
SHV
GND1
SHR
1
56
55
54
53
52
51
50
49
48
47
46
5-V Analog Power Supply and 3.3-V Digital
Power Supply
VCC1
2
BLK-PULSE
OFFSET
VCC3
CLP2
3
Power Down Mode
DATA-IN
PIN
4
5
56-Pin TSSOP (DGG) Package with
Multichip Module Assembly for Isolation
DRIVE-OUT
GND3
AGCGAIN
OBCLP
AGCCLP
SH-PULSE
GND2
6
7
CDS-STBY
VRB-OUT
VRT-OUT
A-SUB
8
CDS/AGC
9
AGC Gain Range of 5 dB to 39 dB
Black Level Clamp Circuit
10
11
VCC2
Direct Connection to ADC Input
Voltage Reference for ADC
D-SUB 12
DVSS 13
D0 14
45 A-SUB
44 DVDD
43 AVSS
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D1
D2
AVSS
VIN
Analog-to-Digital Converter
10-Bit Resolution
D3
D-SUB
AVSS
VRB-IN
VRB-IN
VRT-IN
VRT-IN
AVSS
AVDD
AVDD
AD-STBY
OE
Maximum Conversion Rate . . . 20 MSPS
(MIN)
D4
DVSS
DVDD
D5
Differential Nonlinearity . . . 0.75 LSB (TYP)
Analog Input Voltage Range of 2 Vp-p
3.3 V CMOS Digital Interface
D6
D7
D8
Applications
D9
PC Camera
RESET
DVSS
AVDD
Digital Camera
Camcorder
CLK
CCD Scanner
description
The TLC976 is a multichip module (MCM) subsystem designed for interfacing Charge-Coupled Device (CCD)
in camcorder and digital camera systems. The TLC976 includes correlated double sampler (CDS), automatic
gain control (AGC), black level clamp circuit, 10 bit, 20 MSPS analog-to-digital converter (ADC), and internal
reference voltage generator for ADC.
The CDS/AGC can be connected directly to the ADC input or a separate signal can be connected directly to
the ADC input. A power-down mode is provided.
Assembled using the MCM process, the TLC976 provides isolation between the noisy digital domain and the
noise sensitive analog signals. The CDS/PGA, black level clamps are on one die and the ADC is on a separate
die. The separate dies significantly reduce the substrate noise to the analog section.
The TLC976 comes in a 56-pin TSSOP package with 0,50 mm pin pitch. This is about 25% smaller than using
two separate 32-pin quad flat packs (QFP).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
functional block diagram
SHR SHV
AGCGAIN AGCCLP OBCLP
AGCCLP
SH-PULSE
SH
SH
PIN
LPF
SH
AGC
BLK
BLK-PULSE
VRB-OUT
SH
DATA-IN
VRB
VRT
CLP1
VRT-OUT
CLP2
CLP2
CDS-STBY
OFFSET
DRV
DRIVE-OUT
RESET
Auto
Calibration
Circuit
Upper
Data
Latch
Upper
Sampling
Comparators
D9
D8
D7
D6
D5
Upper
Data
Latch
S&H
VIN
+
DAC
–
Lower
Data
Latch
Lower
Sampling
Comparators
D4
D3
D2
D1
D0
Lower
Data
Latch
VRT-IN
Reference
Voltage
VRB-IN
AD-STBY
OE
Clock
Generator
CLK
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
Terminal Functions
TERMINAL
NAME
AD-STBY
I/O
DESCRIPTION
NO.
31
I
ADC standby mode
L level in operation
H level in standby mode
AGCCLP
AGCGAIN
A-SUB
49
51
I
I
AGC clamp capacitor (connect 0.1 µF to GND)
AGC gain control
11, 45
28, 32, 33
Analog GND
AVDD
ADC analog power supply
Analog GND for ADC
AVSS
34, 39, 42,
43
BLK-PULSE
CDS-STBY
3
8
I
I
DRIVE-OUT terminal is clamped to 1.66 V internally when BLK-PULSE = L.
CDS/AGC standby mode control
L level in operation
H level in standby mode
CLK
29
54
I
I
CLK input for ADC
CLP2
D0–D9
CCD signal clamp control input
14–18,
21–25
O
Digital data output, D0 (pin 14): LSB, D9 (pin 25): MSB
DATA-IN
DRIVE-OUT
D-SUB
DVDD
53
I
CCD signal input
6
O
CDS/AGC output
12, 40
Analog GND
20, 44
ADC digital power supply
Digital GND for ADC
DVSS
13, 19, 27
GND1
2
I
CDS/AGC analog GND
CDS/AGC analog GND
GND for CDS output circuit
Control input for clamping optical black level after AGC
ADC output enable
GND2
47
7
GND3
OBCLP
OE
50
30
I
I
L level in operation
H level in Hi-Z
OFFSET
4
I
CDS/AGC output offset control:
DC voltage at OFFSET pin
DRIVE-OUT offset
–450 mV
0 V
0.5 V
3 V
–280 mV
550 mV
PIN
52
26
I
I
I
I
I
CCD signal input
RESET
SHV
Reset for calibration circuit. Restart of startup calibration.
CCD signal level sample clock input
Sample and hold pulse input
1
SH-PULSE
SHR
48
56
CCD reset level sample clock input
CDS/AGC analog power supply
CDS/AGC analog power supply
CDS/AGC analog power supply
ADC analog signal input
VCC1
55
VCC2
46
VCC3
5
VIN
41
I
O
I
VRB-OUT
VRB-IN
VRT-OUT
VRT-IN
9
ADC bottom reference voltage output (1.5 V typ)
Connect to VRB-OUT
37, 38
10
O
I
ADC top reference voltage output (3.5 V typ)
Connect to VRT-OUT
35, 36
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Analog supply voltage, VCC1, VCC2, VCC3, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to 7 V
Digital supply voltage, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to 7 V
Analog input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to AVCC1, 2,3 + 0.5 V
I
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344 mW
Storage temperature range, T
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 10.75 mW/°C.
recommended operating conditions
MIN NOM
MAX
5.25
3.6
UNIT
V
Analog supply voltage, VCC1, VCC2, VCC3, AVDD
ADC digital output supply voltage, DVDD
Difference, AGND to DGND
4.75
3
5
3.3
V
–100
2
100
mV
V
High-level input voltage
Low-level input voltage
0.8
70
V
ADC analog input voltage full scale range
2
25
25
0
V
High level
ADC CLK pulse width
ns
Low level
Operating temperature
°C
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, T = 25°C (unless
A
otherwise noted)
total device
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AGCGAIN = 0 V,
STBY = 0 V
VRT = VRB = Open,
CDS/AGC supply current
30
38
mA
Digital supply
Analog supply
3
32
6
35
11
ADC supply current
NTSC ramp input
mA
CDS/AGC standby current
ADC standby current
CDS-STBY = High
AD-STBY = HIGH,
5.6
mA
mA
CDS STBY = HIGH,
0.5
1
(VIN = VRT-IN = VRB-IN = Hi-Z)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, T = 25°C (unless
A
otherwise noted) (continued)
CDS input/AGC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
Input signal clamp voltage
2.7
High input
Low input
Minimum
Maximum
VIN = 3 V
VIN = 0 V
1
–1
7
A
Input current for SHR, SHV, CLP2
AGC gain
µA
AGCGAIN = 0 V
AGCGAIN = 3 V
5
dB
34
37
39
1
High-level input current, OBCLP, BLK pulse
Low-level input current, OBCLP, BLK pulse
CDS input clock frequency
µA
µA
–1
20
MHz
driver output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
High
Low
OFFSET = 3 V
OFFSET = 0 V
0.55
0.65
Output offset voltage
–0.35 –0.45
V
Internal black level
1.36
1.66
2
1.96
V
Nominal signal voltage at DRIVE-OUT
Vp-p
reference voltage
PARAMETER
VRT output voltage
VRB output voltage
TEST CONDITIONS
300 Ω, AVDD = VCC1–3 = 4.75 V
MIN
3.47
1.45
TYP
3.50
1.50
MAX
3.53
1.55
UNIT
V
V
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
electrical characteristics over recommended operating junction temperature range,
AVCC = VCC1–3 = 4.75 V, DVDD = 3.3 V, VRT = 3.5 V, VRB = 1.5 V, Fs = 20 MSPS, T = 25°C (unless
A
otherwise noted) (continued)
A/D converter
PARAMETER
Integral non-linearity
TEST CONDITIONS
Fs = 20 MSPS, VIN = 1.8 V – 3.8 V
MIN
TYP
MAX
UNIT
LSB
LSB
pF
±1.5
±2.5
Differential non-linearity
Analog input capacitance
Reference voltage output current
Reference voltage output impedance
Zero scale offset error
±0.75 ±1.25
10
6.5
300
20
mA
Ω
(VRT IN – VRB IN)
mV
mV
µA
Full scale offset error
20
High-level input current
DVDD = MAX,
DVDD = MAX,
OE = GND,
V
V
= DVDD
= 0 V
10
IH
Low-level input current
10
µA
IL
DVDD = MIN,
High-level output current
Low-level output current
3
5
mA
mA
V
= DVDD – 0.5 V
OH
OE = GND,
OL
DVDD = MIN,
V
= 0.4 V
VDD–
0.7V
High-level output voltage
DVDD = 3 V – 5.25 V,
I
I
= 2 mA
= 1 mA
V
V
OH
Low-level output voltage
DVDD = 3 V – 5.25 V,
OE = DVDD,
0.8
1
OL
DVDD = MAX,
High-level output leakage current
µA
V
OH
= DVDD
OE = DVDD,
OL
DVDD = MIN,
Low-level output leakage current
1
µA
V
= 0 V
DVDD–DGND
VRT–VRB
2.5
1
Automatic starting calibration voltage
V
A/D converter operating characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Sampling rate
V
= 1.8 V – 3.8 V,
Fin = 1 kHz ramp
0.5
20 MSPS
MHz
IN
Analog input bandwidth (–3 dB)
Data output, propagation delay
Differential gain
10
C
= 20 pF
15
ns
L
1%
0.3
5
NTSC 40 IRE mod ramp, FS = 14.3 MSPS
Differential phase
Degree
ns
Sampling delay time
Signal to noise ratio
Fin = 1 MHz
55
dB
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
TYPICAL CHARACTERISTICS
AGCGAIN
vs
VOLTAGE
45
40
35
30
25
20
15
10
5
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
AGCGAIN – V
3
Figure 1. AGC Characteristics
OUTPUT OFFSET VOLTAGE
vs
OFFSET CONTROL VOLTAGE
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1
1.5
2
2.5
3
Control Voltage at OFFSET Pin (V)
Figure 2. OFFSET IN Terminal Input/Output Characteristics
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
TYPICAL OPERATION
Optical Black
Dummy Black/Blanking Period
Pixel Period
Signal Period
CCD Reset Feedthrough
CCD Reset Level
CCD Signal Level
CCD Input
SHR Input
SHV Input
2 µs
(typ)
CLP2 Input
1.66 V
Optical Black Level
Black Level
(Internal)
AGC Output
SH-Pulse
(Input)
OBCLP Input
1.66 V
(Internal) BLK
10 µs
(typ)
BLK-PULSE
(Input)
1.66 V
DRIVE-OUT
(Output)
Figure 3. CCD Input Mode Timing Diagram
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
APPLICATION INFORMATION
AV
DD
0.1 µF
1
2
56
55
GND1
V
CC1
3
4
5
6
7
8
9
54
53
52
51
50
49
V
CC3
0.1 µF
GND3
48
47
46
0.1 µF
10
11
GND2
A-SUB
D-SUB
V
CC2
12
13
45
44
A-SUB
DV
SS
DV
DD
14
15
16
17
18
43
42
41
40
39
AGND
AV
AV
SS
SS
D-SUB
AV
SS
19
20
21
22
23
24
38
37
36
35
34
33
DV
DV
SS
DD
0.1 µF
AV
SS
DD
DD
0.1 µF
AV
AV
25
26
27
28
32
31
30
29
DV
AV
SS
DD
DGND
DV
DD
NOTE A: A-SUB and D-SUB should be connected to Analog GND.
Figure 4. Typical Connection Diagram
Table 1. Standby, Output Enable
PIN
8
PIN NAME
CDS-STBY
AD-STBY
OE
FUNCTION
Standby mode for CDS/AGC
Standby mode for AD converter
AD output
OPERATION
STAND-BY OR DISABLE
L
L
L
H
H
H
31
30
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
APPLICATION INFORMATION
0.1 µF
AGCCLP
OBCLP
SHR
SH
SHV
SH
AGCGAIN
AGCCLP
CCD-IN
1 µF
1 µF
SH-PULSE
PIN
LPF
SH
AGC
DATA-IN
BLK-PULSE
VRB-OUT
BLK
SH
CLP1
VRB
VRT
VRT-OUT
CLP2
CLP2
CDS-STBY
DRV
OFFSET-IN
DRIVE-OUT
RESET
Auto
Calibration
Circuit
Upper
Data
Latch
D9
D8
D7
D6
D5
Upper
Data
Latch
Upper
Sampling
Comparators
(see
Note A)
S&H
VIN
DAC
+
(see Note A)
–
D4
D3
D2
D1
D0
Lower
Sampling
Comparators
Lower
Data
Latch
Lower
Data
Latch
VRT-IN
VRB-IN
Reference
Voltage
AD-STBY
OE
Clock
Generator
CLK
NOTE A: The 0.1 µF capacitors are necessary when you need to protect the noise.
Figure 5. Typical Application
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
CDS/AGC signal processor
The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled
and held during both the reset reference interval and the video signal interval. By subtracting two resulting
voltage levels, the CDS removes low frequency noise from the output of the CCD sensor. Two sample/hold
control pulses (SHR and SHV) are required to perform the CDS function.
The CCD output is capacitively coupled to the TLC976. The AC coupling capacitor is clamped to establish
proper dc bias during the dummy pixel interval by the CLP2 input. The bias at the input to the TLC976 is set
to 2.7 V at V
= 4.75 V. Normally, the CLP2 is applied at the sensor’s line rate.
CC
The signal is sent to AGC after the CDS function is complete. The AGC gain can be adjusted from 5 dB to 39
dB by applying variable dc voltage from 0 V to 3 V at the AGCGAIN terminal.
A low-pass filter is installed at the AGC output to improve signal-to-noise ratio. After its output settles, it is
sampled and held by the SH-PULSE input for digitization. The SH-PULSE should synchronize with the ADC
clock.
The basic black level reference is established by clamping the AGC output to 1.66 V internally by the OBCLP
input during the optical black pixel period. A capacitor of 0.1 µF should be connected to the AGCCLP pin.
To prevent the black level from falling below the basic black level (1.66 V) during the blanking period, the AGC
outputleveliskeptat1.66VbytheBLKPULSEinput. ItisrecommendedthattheBLKPULSEbekeptlowduring
the entire blanking period.
The DRV block drives the ADC and adjusts the signal offset at the DRIVE OUT output. The offset can be
adjusted from –450 mV to 550 mV by applying control voltage on the OFFSET pin.
The VRT (3.5 V) and VRB (1.5 V) outputs provide voltage references for the ADC. They should be connected
to the VRT-IN and VRB-IN input pins externally.
analog-to-digital converter (ADC)
The A/DC in the TLC976 performs high-speed analog-to-digital conversion with 10-bit resolution using
semi-flash technique. The latency of the data output valid is 2.5 clocks.
Table 2. ADC Output Code
DIGITAL OUTPUT CODE
INPUT VOLTAGE
STEPS
MSB
LSB
VRT
0
1111111111
•
•
•
•
•
•
•
•
•
•
•
•
•
511
1000000000
•
512
0111111111
•
•
•
•
•
•
•
•
•
•
•
•
VRB
1023
0000000000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
t
t
wl
wh
CLOCK
N+2
N+3
N+4
N
N+1
INPUT SIGNAL
DATA OUTPUT
N–3
N–2
N–1
N
N+1
t
pd
Figure 6. ADC Operation Sequence
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
ADC internal calibration
start-up calibration at power up
After power is turned on, the start-up calibration starts under the following conditions:
1. The voltage between VRT and VRB is over 1 V when the voltage between AVDD and AVSS is over 2.5 V.
2. The voltage between DVDD and DVSS is over 2.5 V.
3. The RESET terminal (pin 26) is high.
4. The AD-STBY terminal (pin 31) is low.
The calibration sequence starts after condition 2 is met (see Figure 7). The following equation calculates the
time required for the start-up calibration after the above conditions are met.
Start-up calibration time = main clock pulse period × 16 × 16384
For example, if the main clock frequency is 15 MHz, the time required for startup calibration is 17.5 ms.
Reset = HIGH, AD-STBY = LOW
5 V
AV
DD
VRT
DV
DD
2.5 V
1 V
VRB
CALIBRATION START
Figure 7. Start-Up Calibration
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
PRINCIPLES OF OPERATION
start-up calibration using RESET terminal
If start-up characteristics are not stable, the start-up calibration can be performed using the AD-STBY terminal
(pin 31) or the RESET terminal (pin 26). Start-up calibration can be initiated properly by connecting RC
components to the RESET pin as shown in Figure 8. The RC components delay the start-up until the supply
voltage stablizes.
AV
DD
M
AV
DD
RESET
VRT
R
RESET
26
C
VRB
AV
SS
(t)
Figure 8. Start-Up Calibration Using RESET Terminal
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC976C
10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR
SLAS193 – OCTOBER 1998
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: B. All linear dimensions are in millimeters.
C. This drawing is subject to change without notice.
D. Body dimensions do not include mold protrusion not to exceed 0,15.
E. Falls within JEDEC MO-153
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLC976CDGG
OBSOLETE TSSOP
OBSOLETE TSSOP
DGG
56
56
TBD
TBD
Call TI
Call TI
Call TI
Call TI
TLC976CDGGR
DGG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2005, Texas Instruments Incorporated
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