TLIN2441-Q1 [TI]
具有集成电压稳压器和看门狗的汽车本地互联网络收发器;
| 型号： | TLIN2441-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成电压稳压器和看门狗的汽车本地互联网络收发器 稳压器 |
| 文件： | 总58页 (文件大小：3424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLIN2441-Q1
ZHCSJ75C –DECEMBER 2018 –REVISED JUNE 2022
TLIN2441-Q1 汽车类、具有集成稳压器和看门狗的
1 特性
2 应用
• AEC-Q100：符合汽车应用要求
• 车身电子装置和照明
• 混合动力、电动和动力总成系统
• 汽车信息娱乐系统和仪表组
• 电器
– 温度等级1：–40°C 至125°C TA
• 符合本地互连网络(LIN) 物理层规范ISO/DIS
17987-4，并符合适用于LIN 的SAE J2602 推荐实
践要求（请参阅SLLA494）
3 说明
• 支持12V 应用和24V 应用
• 由引脚或串行外设接口SPI 配置的集成看门狗监控
器
TLIN2441-Q1 是一款本地互连网络 (LIN) 物理层收发
器，符合 LIN 2.2A 和 ISO/DIS 17987–4 标准，具有
集成的低压降 (LDO) 稳压器和看门狗。 TLIN2441-Q1
看门狗可在窗口模式或超时模式下运行，并且可由引脚
或 SPI 控制。 引脚或 SPI 在加电时根据 9 号引脚的状
态（例如高电平、Z 状态、低电平）建立控制。
• 宽工作范围
– 5.5V 至36V 的电源电压
– ±58V LIN 总线故障保护
– 支持3.3V (TLIN24413-Q1) 或5V (TLIN24415-
Q1) 的LDO 输出
– 睡眠模式：超低电流消耗
LIN 是一根单线制双向总线，通常用于低速车载网络，
数据传输速率高达 20kbps。LIN 接收器支持数据传输
速率高达100kbps 的下线编程应用。TLIN2441-Q1 将
TXD 输入上的 LIN 协议数据流转化为 LIN 总线信号。
接收器将数据流转化为逻辑电平信号，此信号通过开漏
RXD 引脚发送到微处理器。TLIN2441-Q1 通过为功率
微处理器、传感器或其他器件提供电流高达 70mA 的
3.3V 或 5V 电压轨，来降低系统的复杂性。TLIN2441-
Q1 具有经过优化的限流波形整形驱动器，可降低电磁
辐射(EME)。
允许以下类型的唤醒事件：
• LIN 总线
• 通过EN 引脚的本地唤醒
• 通过WAKE 引脚的本地唤醒
– 上电和断电无干扰运行
• 保护特性：
– ESD 保护、VSUP 欠压保护
– TXD 显性超时(DTO) 保护、热关断
– 系统级未供电节点或接地断开失效防护
• VCC 电源在85°C 时为70mA、24VSUP
• 采用无引线VSON (14) 封装，具有改善的自动光学
检测(AOI) 功能
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TLIN2441-Q1
VSON (14)
3.00mm x 4.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VSUP
VBAT
VBAT
VSUP
VSUP
3 kΩ
SW
VDD
3.3 V
VSUP
VDD
10 nF
5 V
3 k
33 kΩ
100 nF
10 µF
10 µF
VDD
VCC VSUP
WAKE
100 nF
33 k
V
WAKE
SUP
VDD
VCC
nRST
nWDR
CLK
10 nF
LIMP
WDT
WDI
SDI
WDT can be connect to GND,
VCC or left floating depending
upon watchdog window timing
requirements
LIMP
SDO
nCS
I/O
MCU
VSUP
nINT
I/O
nWDR
EN
nINT
EN
Commander
MCU
VSUP
Node
Pullup
MCU w/o
pullup
MCU w/o
pullup
Commander Node
Pullup
PIN/nCS
LIN
VDD I/O
1 k
LIN Bus
VDD I/O
1 k
LIN
LIN Controller
Or
SCI/UART
LIN Controller
RXD
TXD
LIN Bus
RXD
TXD
200 pF
Or
Responder
NODE
RXD
TXD
RXD
TXD
SCI/UART
GND
GND
GND
GND
RESPONDER
NODE
200 pF
简化版原理图，SPI 模式
简化版原理图，引脚模式
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF28
TLIN2441-Q1
ZHCSJ75C –DECEMBER 2018 –REVISED JUNE 2022
www.ti.com.cn
Table of Contents
9.3 Feature Description...................................................25
9.4 Device Functional Modes..........................................30
9.5 Programming............................................................ 35
9.6 Registers...................................................................38
10 Application and Implementation................................41
10.1 Application Information........................................... 41
10.2 Typical Application.................................................. 41
11 Power Supply Recommendations..............................45
12 Layout...........................................................................46
12.1 Layout Guidelines................................................... 46
12.2 Layout Example...................................................... 47
13 Device and Documentation Support..........................48
13.1 Documentation Support.......................................... 48
13.2 接收文档更新通知................................................... 48
13.3 支持资源..................................................................48
13.4 Trademarks.............................................................48
13.5 Electrostatic Discharge Caution..............................49
13.6 术语表..................................................................... 49
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 ESD Ratings, IEC Specification..................................4
7.4 Recommended Operating Conditions.........................5
7.5 Thermal Information....................................................5
7.6 Power Supply Characteristics.....................................5
7.7 Electrical Characteristics.............................................7
7.8 AC Switching Characteristics....................................10
7.9 Typical Characteristics.............................................. 11
8 Parameter Measurement Information..........................13
8.1 Test Circuit: Diagrams and Waveforms.....................13
9 Detailed Description......................................................23
9.1 Overview...................................................................23
9.2 Functional Block Diagram.........................................24
Information.................................................................... 49
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (May 2020) to Revision C (June 2022)
Page
• 将提到的所有旧术语实例更改为“指挥官”和“响应者”。.............................................................................. 1
Changes from Revision B (May 2020) to Revision C (June 2022)
Page
• 将提到的所有旧术语实例更改为“指挥官”和“响应者”。.............................................................................. 1
Changes from Revision A (March 2019) to Revision B (May 2020)
Page
• 添加了：（参阅SLLA494）（位于特性列表）................................................................................................. 1
• Added : See errata TLIN1441-Q1 and TLIN2441-Q1 Duty Cycle Over VSUP ....................................................7
• Changed the capacitor value on pin 5 (LIN) From: 220 pF to 200 pF in 图10-1 and 图10-2 .........................41
• Changed the capacitor value on LIN From: 220 pF to 200 pF in 图12-1 ........................................................47
Changes from Revision * (December 2018) to Revision A (March 2019)
Page
• 更改了说明、ESD 等级、ESD 等级、IEC 规范以及电源特性表...................................................................... 1
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5 说明（续）
睡眠模式可实现超低电流消耗，该模式允许通过 LIN 总线或引脚实现唤醒。LIN 总线有两种状态：显性状态（电
压接近接地）和隐性状态（电压接近电池）。在受支配状态下，LIN 总线被内部上拉电阻器 (45kΩ) 和串联二极管
拉高，所以响应器应用无需外部上拉组件。按照 LIN 规范，控制器应用需要一个外部上拉电阻器 (1kΩ) 加上一个
串联二极管。
6 Pin Configuration and Functions
VSUP
LIMP
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
WAKE
EN/nINT
GND
nRST/nWDR
TXD
Thermal
Pad
LIN
RXD
WDT/CLK
nWDR/SDO
PIN/nCS
WDI/SDI
8
Not to scale
图6-1. DMT Package, 14-Pin (VSON), Top View
表6-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
VSUP
LIMP
HV Supply In Device supply voltage (connected to battery in series with external reverse-blocking diode)
2
HV O
Used for LIMP home, watchdog event causes this pin to switch VSUP
Enable Input when in Pin Mode/Processor Interrupt when in SPI Mode (open drain) - when
EN - Enable input - Setting pin high place device into normal mode and setting low is sleep
mode
3
EN/nINT
D I/O
4
5
6
7
GND
GND
HV I/O
D I
Ground
LIN
LIN bus single-wire transmitter and receiver
WDT/CLK
nWDR/SDO
Programmable watchdog window set input (3 levels)/SPI Clock input
Watchdog output trigger when in Pin Mode / SPI Responder Data Output when in SPI Mode
D O
Watchdog timer trigger input active on both rising and falling edges when in Pin Mode (Must
be driven at all times) /SPI Responder Data Input when in SPI Mode
8
9
WDI/SDI
PIN/nCS
D I
D I
Watchdog Configuration Control Set at Power Up. When tied to GND at power up device is
in Pin Mode. When High or in Z-State device is in SPI Mode and this pin becomes Chip
Select
10
11
12
13
14
RXD
D O
D I
RXD output (open-drain) interface reporting state of LIN bus voltage
TXD input interface to control state of LIN output
TXD
nRST/nWDR
WAKE
VCC
D O
HV I
Reset output (active low)/Watchdog output trigger if programmed in SPI Mode (active low)
High Voltage Local wake up pin active Low
Supply Out Output voltage from integrated voltage regulator
(1) HV - High Voltage, D I - Digital Input, D O - Digital Output, HV I/O - High Voltage Input/Output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating TA temperature range (unless otherwise noted)(1)
MIN
–0.3
–58
MAX
58
UNIT
VSUP
VLIN
Supply voltage range (ISO/DIS 17987)
V
V
V
V
V
LIN Bus input voltage (ISO/DIS 17987)
Regulated 5 V Output Supply
58
VCC50
VCC33
VWAKE
6
–0.3
–0.3
–0.3
Regulated 3.3 V Output Supply
WAKE pin input voltage range
4.5
58
58 and VO
≤VSUP+0.3
VLIMP
LIMP pin output voltage range
V
–0.3
VnRST
Reset output voltage
Logic input voltage
VCC + 0.3
V
V
–0.3
–0.3
–0.3
VLOGIC_INPUT
6
6
VLOGIC_OUTPUT
Logic output voltage
Digital pin output current
Reset output current
Ambient temperature
Junction temperature
Storage temperature range
V
IO
8
mA
mA
°C
°C
°C
IO(nRST)
5
–5
–40
–55
–65
TA
125
150
165
TJ
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM) classification level H2: VSUP, LIN, and WAKE with
respect to ground
±10000
Human body model (HBM) classification level 3A: all other pins, per AEC
Q100-002(1)
V(ESD)
Electrostatic discharge
±4000
±750
V
Charged device model (CDM) classification level
All pins
C5, per AEC Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings, IEC Specification
VALUE
UNIT
Electrostatic discharge (1), LIN, VSUP and WAKE
terminal to GND(2)
IEC 61000-4-2 contact discharge
IEC 61000-4-2 air-gap discharge
SAEJ2962-1 contact discharge
SAEJ2962-1 air discharge
Pulse 1
±15000
±15000
±8000
±15000
-450
V
V(ESD)
Powered electrostatic discharge SAEJ2962-1(4)
V
V
Pulse 2a
75
ISO7637-2 and IEC 62215-3 Transients
according to IBEE LIN EMC test spec(3)
Transient
Pulse 3a
-225
Pulse 3b
225
(1) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions per IEC
TS 62228. Different system-level configurations may lead to different results
(2) Testing performed at 3rd party IBEE Zwickau test house, test report available upon request.
(3) ISO7637 is a system-level transient test. Results given here are specific to the IBEE LIN EMC Test specification conditions. Different
system-level configurations may lead to different results.
(4) SAEJ2962-1 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request.
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7.4 Recommended Operating Conditions
over operating TA temperature range (unless otherwise noted)
MIN
5.5
0
NOM
MAX
36
UNIT
V
VSUP
Supply voltage
VLIN
LIN bus input voltage
36
V
VLOGIC5
VLOGIC33
IOH(DO)
IOL(DO)
IO(LIMP)
C(VSUP)
C(VCC)
C(VCC)
ESRCO
Δt/ΔV
TJ
Logic pin voltage
0
5.25
3.465
V
Logic pin voltage
0
V
Digital terminal HIGH level output current
Digital terminal LOW level output current
LIMP output current
-2
mA
mA
mA
nF
µF
µF
2
1
VSUP supply capacitance
100
1
VCC supply capacitance; 500 µA to full load
VCC supply capacitance; no load to full load
Output ESR capacitance requirements
Input transition rise and fall rate (WDI, WDT, WDR)
Operating junction temperature range
10
0.001
2
100
150
Ω
ns/V
°C
–40
7.5 Thermal Information
DMT
14 PINS
35.5
35.3
11.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
11.8
ψJB
RθJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Power Supply Characteristics
Over operating TA temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
45
UNIT
V
SUPPLY VOLTAGE AND CURRENT
Device is operational beyond the LIN
defined nominal supply voltage range See
图8-1 and 图8-2
Operational supply voltage (ISO/DIS 17987
Param 10,53)
VSUP
5.5
Normal and Standby Modes Normal Mode:
Ramp VSUP while LIN signal is a 10 kHz
square wave with 50 % duty cycle and 18 V
swing. See 图8-1 and 图8-2
5.5
5.5
1.8
36
V
Nominal supply voltage (ISO/DIS 17987
Param 10, 53):
VSUP
Sleep Mode
Ramp Up
36
4.2
2.5
V
V
V
UVSUPR
UVSUPF
Under voltage VSUP threshold
Under voltage VSUP threshold
3.5
2.1
Ramp Down
Delta hysteresis voltage for VSUP under
voltage threshold
UVHYS
1.5
V
Transceiver normal mode dominant plus
LDO output; where LDO load current is 70
mA
ISUP
Transceiver and LDO supply current
Supply current transceiver only
80
5.0
1.9
mA
Normal Mode: EN = VCC, bus dominant:
total bus load where RLIN ≥500 Ω and CLIN
≤10 nF
1.2
1
mA
mA
ISUPTRXDOM
Standby Mode: EN = 0 V, bus dominant:
total bus load where RLIN ≥500 Ω and CLIN
≤10 nF
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7.6 Power Supply Characteristics (continued)
Over operating TA temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Normal Mode: EN = VCC
Bus recessive: LIN = VSUP
,
450
750
µA
,
Standby Mode: EN = 0 V, LIN = recessive =
VSUP
45
70
55
ISUPTRXREC
Supply current transceiver only
Added Standby Mode current through the
RXD pull-up resistor with a value of 100 kΩ:
EN = 0 V, LIN = recessive = VSUP, RXD =
GND(1)
µA
5.5 V < VSUP ≤24 V, LIN = VSUP, WAKE =
VSUP, EN = 0 V, TXD and RXD floating
15
25
22
35
µA
µA
ISUPTRXSLP
Sleep mode supply current transceiver only
24 V < VSUP ≤36 V, LIN = VSUP, WAKE =
VSUP, EN = 0 V, TXD and RXD floating
REGULATED OUTPUT VCC
VCC
Regulated output
VSUP = 5.5 to 36 V, ICC = 1 to 70 mA
VSUP = 5.5 to 36 V, ΔVCC, ICC = 10 mA
ICC = 1 to 70 mA, VSUP = 28 V, ΔVCC
2
50
%
mV
mV
mV
mV
V
–2
Line regulation
∆VCC(∆VSUP)
∆VCC(∆VSUPL)
VDROP
Load regulation
50
Dropout voltage (5 V LDO output)
Dropout voltage (3.3 V LDO output)
Under voltage 5 V VCC threshold
Under voltage 5 V VCC threshold
Under voltage 3.3 V VCC threshold
Under voltage 3.3 V VCC threshold
Over voltage 5 V VCC threshold (2)
Over voltage 5 V VCC threshold (2)
Over voltage 3.3 V VCC threshold (2)
Over voltage 3.3 V VCC threshold (2)
Output current
300
350
4.7
600
700
4.9
V
SUP –VCC, ICC = 70 mA
SUP –VCC, ICC = 70 mA
VDROP
V
UVCC5R
UVCC5F
Ramp Up
Ramp Down
4.1
2.5
4.45
2.9
V
UVCC33R
UVCC33F
OVCC5R
OVCC5F
OVCC33R
OVCC33F
ICCOUT
Ramp Up
3.1
6.0
V
Ramp Down
2.75
5.6
V
Ramp Up
V
Ramp Down
5.28
5.5
V
Ramp Up
3.79
3.73
3.98
V
Ramp Down
3.58
0
V
VCC in regulation with 24 V VSUP; TA = 85°C
VCC short to ground
70
mA
mA
ICCOUTL
Output current limit
275
VRIP = 0.5 VPP, Load = 10 mA, ƒ= 100 Hz,
CO = 10 μF, VSUP = 12 V and temperature
= 27 ℃
PSRR
Power supply rejection ripple rejection (2)
60
dB
TSDR
Thermal shutdown temperature (2)
Thermal shutdown temperature (2)
Thermal shutdown hysteresis (2)
Internal junction temperature; rising
Internal junction temperature; falling
VSUP = 12 V and temperature = 27 ℃
165
°C
°C
°C
TSDF
150
TSDHYS
10
(1) RXD pin is an open drain output. In standby mode RXD is pulled low which has the device pulling current through VSUP through the
pull-up resisitor to VCC. The value of the pull-up resistor impacts the standby mode current. A 10 kΩ resistor value can add as much
at 500 µA of current.
(2) Specified by design
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7.7 Electrical Characteristics
over operating TA temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.2
5
UNIT
RXD OUTPUT TERMINAL (OPEN DRAIN)
Based upon a 2 kΩto 10 kΩexternal pull-
VOL
Output low voltage
VCC
up to VCC
IOL
Low level output current, open drain
Leakage current, high-level
LIN = 0 V, RXD = 0.4 V
LIN = VSUP, RXD = VCC
1.5
mA
µA
ILKG
0
–5
TXD INPUT TERMINAL
VIL
Low level input voltage
0.8
5.5
5
V
V
–0.3
2
VIH
IIH
High level input voltage
High level input leakage current
Internal pull-up resistor value
TXD = high
0
µA
kΩ
–5
125
RTXD
350
800
LIN TERMINAL (REFERENCED TO VSUP
)
LIN recessive, TXD = high, IO = 0 mA, VSUP
= 5.5 V to 45 V
VOH
HIGH level output voltage
0.85
VSUP
VSUP
V
LIN dominant, TXD = low, VSUP = 5.5 V to
45 V
VOL
LOW level output voltage
0.2
58
VSUP where impact of recessive LIN bus < 5%
(ISO/DIS 17987 Param 11, 54/56)
VSUP_NON_OP
TXD & RXD open VLIN = 5.5 V to 58 V
–0.3
TXD = 0 V, VLIN = 45 V, RMEAS = 440 Ω,
VSUP = 45 V,
IBUS_LIM
Limiting current (ISO/DIS 17987 Param 57)
40
120
200
mA
VBUSdom < 4.518 V; 图8-6
VLIN = 0 V, VSUP = 24 V Driver off/recessive;
图8-7
Receiver leakage current, dominant (ISO/DIS
17987 Param 58)
IBUS_PAS_dom
IBUS_PAS_rec1
IBUS_PAS_rec2
IBUS_NO_GND
IBUS_NO_BAT
VBUSdom
mA
µA
–1
Receiver leakage current, recessive (ISO/DIS
17987 Param 59)
VLIN ≥VSUP, 5.5 V ≤VSUP ≤45 V Driver
off; 图8-8
20
10
1
Receiver leakage current, recessive (ISO/DIS
17987 Param 59)
µA
VLIN = VSUP, Driver off; 图8-8
–10
–1
Leakage current, loss of ground (ISO/DIS 17987 GND = VSUP, VSUP = 24 V, 0 ≤VLIN ≤36
mA
µA
Param 60)
V; 图8-9
Leakage current, loss of supply (ISO/DIS 17987
Param 61)
10
0.4
0 V ≤VLIN ≤36 V, VSUP = GND; 图8-10
LIN dominant (including LIN dominant for
wake up); 图8-3, 图8-8
Low level input voltage (ISO/DIS 17987 Param
62)
VSUP
VSUP
High level input voltage (ISO/DIS 17987 Param
63)
VBUSrec
0.6
LIN recessive; 图8-3, 图8-8
Receiver center threshold (ISO/DIS 17987 Param
64)
VBUS_CNT
VHYS
0.475
0.5
0.525
0.175
1.0
VSUP
VSUP
V
VBUS_CNT = (VIL + VIH)/2; 图8-3, 图8-8
VHYS = (VIL - VIH); 图8-3, 图8-8
By design and characterization
Hysteresis voltage (ISO/DIS 17987 Param 65)
Serial diode LIN term pull-up path (ISO/DIS 17987
Param 21, 66)
VSERIAL_DIODE
0.4
0.7
45
Pull-up resistor to VSUP (ISO/DIS 17987 Param
26, 71)
RResponder
Normal and Standby modes
20
60
kΩ
IRSLEEP
CLIN,PIN
Pull-up current source to VSUP
Capacitance of the LIN pin
Sleep mode, VSUP = 24 V, LIN = GND
By design and characterization
µA
pF
–20
–2
45
EN INPUT TERMINAL
VIH
VIL
High level input voltage
2
5.5
0.8
500
8
V
V
Low level input voltage
Hysteresis voltage
VHYS
IIL
By design and characterization
EN = Low
30
–8
125
mV
µA
Low level input current
Internal pull-down resistor
REN
350
0.5
800
kΩ
LIMP OUTPUT TERMINAL (HIGH VOLTAGE OPEN DRAIN OUTPUT)
High level voltage drop LIMP with respect to VSUP ILIMP = - 0.5 mA
Leakage current LIMP = 0 V, Sleep Mode
1
V
ΔVH
ILKG(LIMP)
0.5
µA
–0.5
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7.7 Electrical Characteristics (continued)
over operating TA temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WAKE INPUT TERMINAL
Selective Wake-up or Standby Mode, WAKE
pin enabled
VIH
VIL
High-level input voltage
Low-level input voltage
V
V
V
SUP –2
Selective Wake-up or Standby Mode, WAKE
pin enabled
V
SUP –3
IIH
IIL
High-level input leakage current
Ligh-level input leakage current
WAKE = VSUP - 1 V
WAKE = 1 V
µA
µA
–25
5
–15
15
25
50
Wake up time from a wake edge on WAKE;
Standby or Sleep mode
tWAKE
WAKE hold time
µs
WDI, SDI, SCK, nCS INPUT TERMINAL
VIH
High-level input voltage
2.19
V
VIL
Low-level input voltage
0.8
1
V
IIH
High-level input leakage current
Low-level input leakage current
Input Capacitance
Inputs = VCC
µA
µA
pF
µA
–1
IIL
Inputs = 0 V, VCC = Active
4 MHz
-5
15
1
–50
CIN
10
ILKG(OFF)
Unpowered leakage current
Inputs = 5.25/3.465 V, VCC = VSUP = 0 V
–1
WDT INPUT TERMINAL
VIH
High-level input voltage
Inputs = VCC
0.8
VCC
VCC
VCC
µA
VIL
Low-level input voltage
Inputs = VCC
0.2
0.6
VIM(WDT)
IIH
WDT Mid-level input voltage(1)
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
Inputs = VCC
0.4
2.5
0.5
Inputs = VCC
25
IIL
Inputs = 0 V, VCC = Active
Inputs = 5.25/3.465 V, VCC = VSUP = 0 V
µA
–25
–1
–2.5
1
ILKG(OFF)
µA
SDO OUTPUT TERMINAL
VOH
High level output voltage
IO = 2 mA, VCC = Active
0.8
–1
–5
1.5
VCC
VCC
µA
VOL
Low level output voltage
IO = 2 mA, VCC = Active
0.2
1
ILKG(OFF)
Unpowered leakage current
Outputs = 5.25/3.465 V, VCC = VSUP = 0 V
nRST, nWDR (SPI Mode) TERMINAL (OPEN DRAIN OUTPUT)
ILKG
VOL
IOL
Leakage current, high-level
Low-level output voltage
LIN = VSUP, nRST = VCC
5
µA
VCC
mA
Based upon external pull up to VCC
LIN = 0 V, nRST = 0.4 V
0.2
Low-level output current, open drain
nINT, nWDR (Pin Mode) TERMINAL (OPEN DRAIN OUTPUT)
VOL
IOL
Low-level output voltage
0.2
5
VCC
mA
µA
Low-level output current, open drain
Leakage current, high-level
LIN = 0 V, nINT = 0.4 V
LIN = VSUP, nINT = VCC
1.5
ILKG
–5
WDI, WDT TIMING and SWITCHING CHARACTERISTIC (RL = 1 MΩ, CL = 50 pF and TA = -40°C to 125°C)
tW
td
Filter time to avoid false input
Time from nWDR low to high
30
2
µs
WDI pulse width; see 图8-19
nWDR pulse width delay time that sets the lower
window boundry starting point; see 图8-19
4
6
ms
WDT = GND
WDT = VCC
32
480
4.8
16
40
600
6
48
720
7.2
24
ms
ms
s
tWINDOW
Closed Window + Open Window; See 图8-19
WDT = Floating
WDT = GND
WDT = VCC
20
300
3
ms
ms
s
Watchdog timeout window (Open Window); See
图8-19
tWDOUT
240
2.4
360
3.6
WDT = Floating
Propagation delay time high to low level output
(VCC to nWDR delay)
tPHL
VCC = Active
40
65
µs
DUTY CYCLE CHARACTERISTICS(2)
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7.7 Electrical Characteristics (continued)
over operating TA temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THREC(MAX) = 0.744 x VSUP
,
THDOM(MAX) = 0.581 x VSUP
,
VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT) (See 图8-11, 图
8-12)
D112V
Duty Cycle 1 (ISO/DIS 17987 Param 27)
Duty Cycle 2 (ISO/DIS 17987 Param 28)
0.396
THREC(MIN) = 0.422 x VSUP
,
THDOM(MIN) = 0.284 x VSUP, VSUP = 5.5 V to
18 V,
D212V
0.581
tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2
x tBIT) (See 图8-11, 图8-12)
THREC(MAX) = 0.778 x VSUP, THDOM(MAX)
0.616 x VSUP
=
,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4
kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See 图8-11, 图
D312V
Duty Cycle 3 (ISO/DIS 17987 Param 29)
Duty Cycle 4 (ISO/DIS 17987 Param 30)
0.417
8-12)
THREC(MIN) = 0.389 x VSUP
,
THDOM(MIN) = 0.251 x VSUP
,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4
kbps),
D412V
0.59
D4 = tBUS_rec(MAX)/(2 x tBIT) (See 图8-11, 图
8-12)
THREC(MAX) = 0.710 x VSUP, THDOM(MAX)
=
0.554 x VSUP, VSUP = 15 V to 36 V, tBIT = 50
µs, D1 = tBUS_rec(MIN)/(2 x tBIT) (See 图
8-13, 图8-14
D124V
D224V
D324V
D424V
Duty Cycle 1 (ISO/DIS 17987 Param 72)
Duty Cycle 2 (ISO/DIS 17987 Param 73)
Duty Cycle 3 (ISO/DIS 17987 Param 74)
Duty Cycle 4 (ISO/DIS 17987 Param 75)
0.330
THREC(MIN) = 0.446 x VSUP, THDOM(MIN)
=
0.302 x VSUP, VSUP = 15.6 V to 36 V, tBIT
=
0.642
50 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See 图
8-13, 图8-14)
THREC(MAX) = 0.744 x VSUP, THDOM(MAX)
=
0.581 x VSUP, VSUP = 5.5 V to 36 V, tBIT = 96
µs, D3 = tBUS_rec(min)/(2 x tBIT) (See 图8-13,
图8-14)
0.386
THREC(MIN) = 0.442 x VSUP, THDOM(MIN)
=
0.284 x VSUP, VSUP = 5.5 V to 36 V, tBIT = 96
µs, D4 = tBUS_rec(MAX)/(2 x tBIT) (See 图
8-13, 图8-14)
0.591
(1) This is the measured voltage at the WDT pin when left floating. The WDT pin should be connected directly to VCC, GND or left floating.
(2) See errata TLIN1441-Q1 and TLIN2441-Q1 Duty Cycle Over VSUP
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7.8 AC Switching Characteristics
over operating TA temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE SWITCHING CHARACTERISTICS
trx_pdr
trx_pdf
Receiver rising/falling propagation delay time
(ISO/DIS 17987 Param 31,76)
RRXD = 2.4 kΩ, CRXD = 20 pF (See 图
8-13, 图8-14)
6
µs
Rising edge with respect to falling edge,
(trx_sym = trx_pdf –trx_pdr), RRXD = 2.4 kΩ,
CRXD = 20 pF (图8-13, 图8-14)
Symmetry of receiver propagation delay time
Receiver rising propagation delay time (ISO/DIS
17987 Param 32, 77)
trs_sym
2
150
60
µs
µs
µs
–2
LIN wakeup time (minimum dominant time on LIN
bus for wakeup)
tLINBUS
25
100
45
See 图8-17, 图9-5, and 图9-6
See 图9-6
Time to clear false wakeup prevention logic if LIN
bus had a bus stuck dominant fault (recessive
time on LIN bus to clear bus stuck dominant fault)
tCLEAR
tDST
10
20
Dominant state time out
Mode change delay time
80
15
ms
µs
Time to change from normal mode to sleep
mode through EN pin: See 图8-15
tMODE_CHANGE
Time to change from sleep mode to normal
mode through EN pin and not due to a wake
event; RXD pulled up to VCC: See 图8-15
Mode change delay time sleep mode to normal
mode
800
45
µs
µs
Time for normal mode to initialize and data
on RXD pin to be valid, includes
tMODE_CHANGE for standby mode to normal
mode See 图8-15
tNOMINT
Normal mode initialization time
Timer for inactivity coming out of sleep mode and
when coming out of failsafe mode to determine if
caused event has been cleared (1)
tINACT_FS
250
200
ms
ms
Upon power up time it takes for valid data
on RXD
tPWR
Power up time
1.5
5
SPI SWITCHING CHARACTERISTICS
fSCK
tSCK
tRSCK
tFSCK
tSCKH
tSCKL
tACC
tCSS
tCSH
tCSD
tSISU
tSIH
SCK, SPI clock frequency (1)
SCK, SPI clock period (1)
SCK rise time (1)
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
See 图8-18
40
40
SCK fall time (1)
SCK, SPI clock high (1)
SCK, SPI clock low (1)
First read access time from chip select (1)
Chip select setup time (1)
Chip select hold time (1)
Chip select disable time (1)
Data in setup time (1)
Data in hold time (1)
80
80
50
100
100
500
30
40
tSOV
tRSO
tFSO
Data out valid (1)
80
40
40
SO rise time (1)
SO fall time (1)
(1) Specified by design
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7.9 Typical Characteristics
130
125
120
115
110
105
100
95
72.5
70
-40°C
25°C
85°C
105°C
125°C
67.5
65
62.5
60
90
57.5
55
-40°C
25°C
85°C
105°C
125°C
85
80
75
52.5
5
10
15
20
25
30
35
40
D001
5
10
15
20
25
VSUP (V)
30
35
40
45
D004
VSUP (V)
VCC = 5 V
ICC Load = 125 mA Normal Mode
VCC = 5 V
ICC Load = 70 mA Normal Mode
图7-1. ISUP vs VSUP Across Temperature
图7-2. ISUP vs VSUP Across Temperature
72.5
70
32
30
28
26
24
22
20
18
16
14
12
67.5
65
62.5
60
57.5
55
-40°C
25°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
52.5
50
5
10
15
20
25
VSUP (V)
30
35
40
45
D030
5
10
15
20
25
VSUP (V)
30
35
40
45
D009
VCC = 3.3 V
ICC Load = 70 mA Normal Mode
VCC = 5 V
Sleep Mode
图7-3. ISUP vs VSUP Across Temperature
图7-4. ISUP vs VSUP Across Temperature
20
18
16
14
12
10
8
5.5
5
4.5
4
3.5
3
2.5
2
-40°C
27°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
1.5
1
6
4
0.5
5
10
15
20
25
VSUP (V)
30
35
40
45
D035
0
5
10
15
20
25
VSUP (V)
30
35
40
45
50
D002
VCC = 3.3 V
Sleep Mode
VCC = 5 V
图7-5. ISUP vs VSUP Across Temperature
图7-6. VCC vs VSUP Across Temperature
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3.5
3
2.5
2
1.5
1
0.5
0
-40°C
25°C
85°C
105°C
125°C
-0.5
0
5
10
15
20
VSUP (V)
25
30
35
40
D038
VCC = 3.3 V
图7-7. VCC vs VSUP Across Temperature
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8 Parameter Measurement Information
8.1 Test Circuit: Diagrams and Waveforms
VCC
3
14
1
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
VCC
EN/nINT
10
VSUP
RXD
5
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
8
9
WDI/SDI
PIN/nCS
LIN
WAKE
13
6
Jitter: < 25 ns
WDT/CLK
11 TXD
nWDR/SDO
GND
12 nRST/nWDR
7
4
2
LIMP
Measurement Tools
O-scope:
DMM
图8-1. Test System: Operating Voltage Range with RX and TX Access
Delta t = + 5 µs (tBIT
= 50 µs)
Trigger Point
RX
2 * tBIT = 100 µs (20 kBaud)
图8-2. RX Response: Operating Voltage Range
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
图8-3. LIN Bus Input Signal
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VCC
3
14
1
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
EN/nINT
10
VPS
VSUP
RXD
5
8
9
LIN
WAKE
WDI/SDI
PIN/nCS
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
13
6
Jitter: < 25 ns
11 TXD
WDT/CLK
nWDR/SDO
GND
12 nRST/nWDR
7
4
2
LIMP
Measurement Tools
O-scope:
DMM
图8-4. LIN Receiver Test with RX access
VCC
3
VCC
14
1
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
EN/nINT
VSUP
RXD
10
8
VPS1
5
LIN
WAKE
WDI/SDI
PIN/nCS
D
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
9
13
6
11 TXD
WDT/CLK
VPS2
RBUS
nWDR/SDO
GND
7
4
12 nRST/nWDR
2
LIMP
Measurement Tools
O-scope:
DMM
图8-5. VSUP_NON_OP Test Circuit
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VCC
3
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
14
1
EN/nINT
RXD
VSUP
VPS
10
8
RMEAS
5
WDI/SDI
PIN/nCS
TXD
LIN
9
WAKE 13
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
T = 10 ms
11
WDT/CLK
6
Jitter: < 25 ns
nWDR/SDO
GND
12 nRST/nWDR
7
4
2
LIMP
Measurement Tools
O-scope:
DMM
图8-6. Test Circuit for IBUS_LIM at Dominant State (Driver on)
VCC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
14
1
3
VCC
EN/nINT
RXD
10
VPS
VSUP
RMEAS = 499 Ω
5
8
9
LIN
WDI/SDI
PIN/nCS
WAKE
13
6
11 TXD
WDT/CLK
nWDR/SDO
GND
7
4
12 nRST/nWDR
2
LIMP
Measurement Tools
O-scope:
DMM
图8-7. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V
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Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VCC
3
VPS1
14
1
VCC
EN/nINT
VSUP
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
RXD
10
8
1 kΩ
5
LIN
VPS2
WDI/SDI
PIN/nCS
WAKE
13
6
9
VPS2 2 V/s ramp
[8 V ‰ 36 V]
11 TXD
WDT/CLK
V Drop across resistor
< 20 mV
7
4
nWDR/SDO
GND
12 nRST/nWDR
2
LIMP
Measurement Tools
O-scope:
DMM
图8-8. Test Circuit for IBUS_PAS_rec
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VCC
3
VPS1
14
1
VCC
EN/nINT
10
VSUP
RXD
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
1 kΩ
5
8
9
LIN
WAKE
WDI/SDI
13
6
PIN/nCS
VPS 2 V/s ramp
[0 V ‰ 36 V]
11 TXD
WDT/CLK
V Drop across resistor
< 1V
nWDR/SDO
GND
12 nRST/nWDR
7
4
2
LIMP
Measurement Tools
O-scope:
DMM
图8-9. Test Circuit for IBUS_NO_GND Loss of GND
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VCC
3
14
1
VCC
EN/nINT
VSUP
RXD
10
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
VPS
10 kΩ
5
8
LIN
WAKE
WDI/SDI
13
6
PIN/nCS
VPS 2 V/s ramp
[0 V ‰ 36 V]
9
11 TXD
WDT/CLK
V Drop across resistor
< 1V
nWDR/SDO
GND
12 nRST/nWDR
7
4
2
LIMP
Measurement Tools
O-scope:
DMM
图8-10. Test Circuit for IBUS_NO_BAT Loss of Battery
VCC
3
14
1
VCC
EN/nINT
RXD
10
VSUP
VPS1
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
RMEAS
5
8
LIN
WDI/SDI
WAKE
13
6
9
PIN/nCS
TXD
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
VPS2
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
11
WDT/CLK
Jitter: < 25 ns
7
4
nWDR/SDO
GND
12 nRST/nWDR
2
LIMP
Measurement Tools
O-scope:
DMM
图8-11. Test Circuit Slope Control and Duty Cycle
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tBIT
tBIT
RECESSIVE
TXD (Input)
DOMINANT
THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
LIN Bus
Signal
VSUP
THREC(MIN)
Thresholds
RX Node 2
THDOM(MIN)
tBUS_REC(MIN)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
D = tBUS_REC(MIN)/(2 x tBIT
)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
D = tBUS_REC(MAX)/(2 x tBIT
)
图8-12. Definition of Bus Timing
VCC
VCC
14
1
3
VCC
EN/nINT
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
2.4 kΩ
10
VSUP
VPS
RXD
5
8
9
LIN
WAKE
WDI/SDI
20 pF
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 Hz
13
6
PIN/nCS
Jitter: < 25 ns
11 TXD
WDT/CLK
nWDR/SDO
GND
12 nRST/nWDR
7
4
2
LIMP
Measurement Tools
O-scope:
DMM
图8-13. Propagation Delay Test Circuit
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THREC(MAX)
Thresholds
RX Node 1
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
LIN Bus
Signal
VSUP
Thresholds
RX Node 2
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
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图8-14. Propagation Delay
Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
tNOMINT
Transition
Normal
Sleep
Standby
Transition
Normal
MODE
Wake Request
RXD = Low
Mirrors
Bus
RXD
Indeterminate Ignore
Floating
Indeterminate Ignore
Mirrors Bus
图8-15. Mode Transitions
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EN
Weak Internal Pullup
TXD
Weak Internal Pullup
VSUP
LIN
RXD
Floating
tMODE_CHANGE
+
Sleep
MODE
Normal
tNOMINIT
图8-16. Wakeup Through EN
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0.6 x VSUP
LIN
0.6 x VSUP
VSUP
0.4 x VSUP
0.4 x VSUP
t < tLINBUS
tLINBUS
TXD
Weak Internal Pullup
EN
Floating
RXD
MODE
Sleep
Standby
Normal
图8-17. Wakeup through LIN
tCSD
nCS
tCSH
tFSCK
tRSCK
tCSS
CLK
SDI
tSISU
tSIH
LSB In
MSB In
tSOV
tACC
tFSO
tRSO
SDO
MSB Out
LSB Out
图8-18. SPI AC Characteristic for Read and Write
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Watchdog Window
Closed Window
Open Window
tWDOUT min
Watchdog Window
Closed Window
Open Window
tWDOUT max
tWINDOW min
tWINDOW max
Safe Trigger area
WDI
Change of state
tW
tW is the filter time for the
input to be recognized to
avoid false triggers
WDI Trigger
Rising or Falling
Edge
nWDR
td
图8-19. Watchdog Window Timing Diagram
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9 Detailed Description
9.1 Overview
The TLIN2441-Q1 LIN transceiver is a Local Interconnect Network (LIN) physical layer transceiver, compliant to
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 with integrated wake-up and protection features. The
LIN bus is a single-wire, bidirectional bus that typically is used in low-speed in-vehicle networks with data rates
that range up to 20 kbps. The LIN receiver works up to 100 kbps supporting in-line programming. The device
converts the LIN protocol data stream on the TXD input into a LIN bus signal using a current-limited wave-
shaping driver which reduces electromagnetic emissions (EME). The receiver converts the data stream to logic-
level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus has two states:
dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN
bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode.
Ultra-low current consumption is possible using the sleep mode. The TLIN2441-Q1 provides three methods to
wake up from sleep mode: EN pin, WAKE pin and LIN bus. The device integrates a low dropout voltage
regulator with a wide input from VSUP providing 5 V ±2% or 3.3 V ±2% with up to 70 mA of current depending
upon system implementation.
The TLIN2441-Q1 integrates a window based watchdog supervisor which has a programmable delay and
window ratio determined by pin strapping or SPI communication. The device watchdog is controlled by pin
configuration or SPI depending upon the state of pin 9 at power up. At power up, if pin 9 is externally pulled to
ground, the device is configured for pin control of the device. If pin 9 is connected to the nCS pin of the
processors and not driven at power up, the internal pull up configures the device for 3.3 V SPI control. If the
processor uses 5 V IO a 500k Ωpull up resistor to VCC is used for the 5 V version of the device. This allows the
5 V version of the device to work with both 3.3 V SPI or 5 V SPI. SPI communication is used for device
configuration. In pin configuration nRST is asserted high when VCC increases above UVCC and stays high as
long as VCC is above this threshold.
When the watchdog is controlled by the device pins, the state of the WDT pin determines the window time. WDI
is used as the watchdog input trigger which is expected in the open window. If a watchdog event takes place, the
nWDR pin goes low to reset the processors. When using SPI writing FFh to register 15h, WD_TRIG, during the
open window restarts the watchdog timer. The supervised processor must trigger the WDI pin or WD_TRIG
register within the defined window. When using SPI, the nRST pin becomes the watchdog event output trigger
for the processor. The watchdog timer does not start until after the first input trigger on WDI or the WD_TRIG
register.
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9.2 Functional Block Diagram
VCC
250 kO
VSUP
5.0 V or 3.3 V LDO
nRST/nWDR
VSUP
UV
DET
CNTL
POR
RXD
LIMP
VSUP
VSUP/2
Comp
EN_TRX
VSUP
45 kQ
Filter
Wake Up
State &
LIMP CTL
WAKE
WAKE
Fault Detection
& Protection
VCC
LIN
350 kO
DR/
Slope
CTL
Dominant
State
Timeout
TXD
GND
图9-1. Transceiver plus VREG Functional Block Diagram
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EN_TRX
EN/nINT
350 kꢀ
nINT
VCC
WDT is a 3 level
input
CLK
WDT/CLK
WDT
VCC
WDI/SDI
WDI/SDI
SPI Controller
VCC
SDO
nWDR/SDO
nWDR
nCS
VCC
PIN/nCS
VCC
PIN
Watchdog Programming Select
Pin vs SPI decision on power up
图9-2. Input and Output High Level Functional Block Diagram
9.3 Feature Description
9.3.1 LIN Pin
This high-voltage input or output pin is a single-wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 58 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking
diodes, even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter meets thresholds and AC parameters according to the LIN specification. The transmitter is a low-
side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN responder node applications. An external pull-
up resistor and series diode to VSUP must be added when the device is used for a commander node application.
9.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are ratio-metric with the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAEJ2602
specifications. This allows the TLIN2441-Q1 to be used for high-speed downloads at the end-of-line production
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or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP
must be added when the device is used for commander node applications as per the LIN specification.
图9-3 shows a commander node configuration and how the voltage levels are defined
Voltage drop across the
Simplified Transceiver
VLIN_Bus
diodes in the pullup path
VSUP
VSUP
VSUP/2
RXD
VBattery
VSUP
VLIN_Recessive
Receiver
Filter
1 kꢀ
45 kΩ
LIN Bus
LIN
VCC
350 kꢀ
TXD
GND
Transmitter
with slope control
VLIN_Dominant
t
图9-3. Commander Node Configuration with Voltage Levels
9.3.2 TXD (Transmit Input)
TXD is the interface to the node processor’s LIN protocol controller that is used to control the state of the LIN
output. When TXD is low, the LIN output is dominant (near ground). When TXD is high, the LIN output is
recessive (near VSUP). See 图9-3. The TXD input structure is compatible with processors that use 3.3 V and 5 V
VI and VO. TXD has an internal pull-up resistor. The LIN bus is protected from being stuck dominant through a
system failure driving TXD low through the dominant state time-out timer.
9.3.3 RXD (Receive Output)
RXD is the interface to the processor's LIN protocol controlleror SCI and UART, which reports the state of the
LIN bus voltage. LIN recessive (near VSUP) is represented by a high level on the RXD and LIN dominant (near
ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.
This allows the device to be used with 3.3 V and 5 VI/O processors. If the processor's RXD pin does not have an
integrated pull-up, an external pull-up resistor to the processors I and O supply voltage is required. In standby
mode, the RXD pin is driven low to indicate a wake-up request from the LIN bus .
9.3.4 WAKE (High Voltage Local Wake Up Input)
WAKE pin is used for a high voltage device local wake up (LWU). This function is explained further in docato-
extra-info-title Local Wake Up (LWU) via WAKE Terminal, see 节9.4.5.2 section. The pin is both rising and falling
edge trigger, meaning it recognizes a LWU on either edge of WAKE pin transition.
9.3.5 WDT/CLK (Pin Programmable Watchdog Delay Input/SPI Clock)
When PIN/nCS is connected to ground at power up, this pin becomes the pin programmable watchdog delay
input. This pin sets the upper boundary of the window watchdog. It can be connected to VCC, GND or left
floating. When connected directly to VCC or GND or left open, the window frame takes on one of three value
ranges: GND – 32 ms to 48 ms, VCC – 480 ms to 720 ms or left open – 4.8 s to 7.2 s. The closed versus
open windows are based upon 50%/50%.
When PIN/nCS is connected to a high-Z output pin from a processor this pin becomes the SPI input clock.
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9.3.6 WDI/SDI (Watchdog Timer Input/SPI Serial Data In)
When PIN/nCS is connected to ground at power up, this pin becomes the watchdog timer input trigger. This
resets the timer with either a positive or negative transition from the processor. A filter time of tW is used to avoid
false triggers.
When PIN/nCS is connected to a high-Z output pin from a processor, this pin becomes the SPI serial data input
pin for programming the device and providing a trigger event for the watchdog same as the WDI.
9.3.7 PIN/nCS (Pin Watchdog Select/SPI Chip Select)
This pin determines if the TLIN2441-Q1 watchdog is programmed by pin strapping or by SPI. At power up, the
device monitors this pin and determine which method is to be used. When tied to GND, the device is pin
programmable, and when connected to a high-Z processor I/O pin, the device is set up to support SPI. In SPI
mode if the LDO is being used to power up other circuitry than the processor a mismatch can take place if using
the 5 V version of the device and the processor supports 3.3 V. All I/O in the device are set up to work with a 3.3
V processor but if the 5 V LDO is being used for the processor requiring the I/O to be 5 V then an external
resistor pulled up to VCC. This makes the I/O 5 V.
备注
The behavior of the microprocessor used must be understood if connecting to this pin to control
whether the device is to be pin controlled or SPI controlled. There is an internal pull-up that sets the
device in SPI control mode. If the processor pin drives low during power up, the device is in pin control
mode. To specify pin control mode place and external pull-down resister to ground.
VCC
(5 V)
3.3 V
3.3 V
3.3 V
5 V SPI
PIN Mode
3.3 V SPI
PIN/nCS
PIN/nCS
PIN/nCS
GND
图9-4. PIN/nCS Configuration
9.3.8 LIMP (LIMP Home output –High Voltage Open Drain Output)
This pin is connected to external circuitry for a limp home mode if the watchdog has timed out causing a reset.
For the Limp pin to be turned off, the watchdog error counter must reach zero from correct input triggers in both
pin control and SPI control modes. In SPI control Mode, other options can be selected in reg'h0B[4:3]. This
feature can be disabled in SPI mode by setting reg'h0B[5] = 1. The only two modes that the LIMP pin changes
state are in normal and failsafe modes. When in normal mode the LIMP pin is off unless there is a watchdog
failure event that triggers it on. If programmed by SPI any event that trigger the failsafe mode also turns on the
LIMP pin.
9.3.9 nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)
When PIN/nCS is connected to ground at power up, this pin becomes the watchdog timeout reset output pin.
When the watchdog times out, this pin goes low for time of td and then release back to VCC
.
When PIN/nCS is connected to a high-Z output pin from a processor, this pin becomes the SPI serial data output
pin.
9.3.10 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse-battery blocking
diode
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(see 图 9-3). The VSUP pin is a high-voltage-tolerant pin. A decoupling capacitor with a value of 100 nF is
recommended to be connected close to this pin to improve the transient performance. If there is a loss of power
at the ECU level, the device has ultra low leakage from the LIN pin, which does not load the bus down. This is
optimal for LIN systems in which some of the nodes are unpowered (ignition supplied) while the rest of the
network remains powered (battery supplied). When VSUP drops low enough the regulated output drops out of
regulation. The LIN bus works with a VSUP as low as 5.5 V, but at a lower voltage, the performance is
indeterminate and not ensured. If VSUP voltage level drops enough, it triggers the UVSUP, and if it keeps
dropping, at some point it passes the POR threshold.
9.3.11 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage. If there is a loss of ground at the ECU level, the
device has ultra low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems
in which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied).
9.3.12 EN/nINT (Enable Input/Interrupt Output in SPI Mode)
When PIN/nCS is connected to ground at power up, this pin becomes the transceiver enable control. EN controls
the operational modes of the device. When EN is high, the device is in normal operating mode allowing a
transmission path from TXD to LIN and from LIN to RXD. When EN is low, the device is put into sleep mode and
there are no transmission paths available. The device can enter normal mode only after wake up. EN has an
internal pull-down resistor to ensure the device remains in low power mode even if EN floats. EN should be held
low until VSUP reaches the expected systen voltage level.
When PIN/nCS is connected to a high-Z output pin from a processor, this pin becomes processor interrupt output
pin in SPI communication mode. When the TLIN2441-Q1 requires the attention of the processor, this pin is
pulled low.
9.3.13 nRST/nWDR (Reset Output/Watchdog Timeout Reset Output)
The nRST pin serves as a VCC monitor for under voltage events in Pin Control Mode and is the default function
for SPI mode. This pin is internally pulled up to VCC. When used a nRST and an under voltage event takes
place, the signal is pulled low. The signal returns to VCC value once the voltage on VCC exceeds the under
voltage threshold. If a thermal shutdown event takes place, the signal is pulled to ground. When the device is
configured by SPI, the pin can be programmed to become the watchdog output trigger to reset the processor.
When the watchdog times out, this signal is pulled low for time of td and then released back to VCC. If both are
needed for SPI configuration it is recommended to add an external circuit off the LIMP pin to serve as the
watchdog output trigger to reset the processor. Note the LIMP pin output is a high voltage output based upon
VSUP and care must be taken when connecting to a lower voltage device.
9.3.14 VCC (Supply Output)
The VCC terminal can provide 5 V or 3.3 V with up to 70 mA from 24 VSUP at 85°C to power up external devices
when using high-k boards and thermal management best practices .
9.3.15 Protection Features
The device has several protection features that are described as follows.
9.3.15.1 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state time-out timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-up to ensure the device fails to a
known recessive state if TXD is disconnected. During this fault, the transceiver remains in normal mode
(assuming no change of state request on EN), the RXD pin reflects the LIN bus and the LIN bus pull-up
termination remains on. The TLIN2441-Q1 can turn off this feature when in SPI mode by using register h0B[0].
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9.3.15.2 Bus Stuck Dominant System Fault: False Wake Up Lockout
The device contains logic to detect bus stuck dominant system faults and prevents the device from waking up
falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus. If the bus
is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears”the bus stuck dominant,
preventing excessive current use. 图9-5 and 图9-6 show the behavior of this protection.
RXD
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
图9-5. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
RXD
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
图9-6. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
9.3.15.3 Thermal Shutdown
The LIN transmitter is protected by limiting the current; however, if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state and turns
off the VCC regulator. The nRST pin is pulled to ground during a TSD event. Once the over-temperature fault
condition has been removed and the junction temperature has cooled beyond the hysteresis temperature, the
transmitter is re-enabled. During this fault the device enters a TSD off mode. Once the junction temperature
cools, the device enters standby mode as per the state diagram. In SPI mode the device can be configured to
support a failsafe mode. If programmed the device enters this mode upon an TSD event which puts the device
into a sleep mode with LIMP turned on, see 图 9-7. In SPI mode the device can be configured to support a
failsafe mode. If programmed the device enters this mode upon an TSD event which puts the device into a sleep
mode with LIMP turned on, see 图9-7.
9.3.15.4 Under Voltage on VSUP
The device contains a power-on reset circuit to avoid false bus messages during under voltage conditions when
VSUP is less than UVSUP
.
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9.3.15.5 Unpowered Device and LIN Bus
In automotive applications, some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remain powered by the battery. The device has extremely low unpowered leakage current from the bus,
so an unpowered node does not affect the network nor load it down.
9.4 Device Functional Modes
nRST: Float
The TLIN2441-Q1 has three functional modes of operation: normal, sleep, and standby. The next sections
describes these modes as well as how the device moves between the different modes. 图 9-7 graphically shows
the relationship while 表9-1 shows the state of pins.
表9-1. Operating SPI Mode
LIN BUS
Termination
nRST/
Mode
RXD
Transmitter
Watchdog SPI Pins
nINT Pin
WAKE Pin
LIMP
Comment
nWDR Pin
nRST is internally connected to the
LDO output which in sleep mode is
off
Weak current
pull-up
Sleep
Floating
Off
Off
Off
On
Floating
On
Off
Previous state
prior to entering
STBY
wake-up event detected,
waiting on processors to set EN
Standby
Normal
TSD Off
Failsafe
Low
Off
On
Off
On
Off
Off
On
On
On
Off
On
On
On
On
On
On
On
On
On
45 kΩ (typical)
45 kΩ (typical)
Floating
LIN Bus
Data
Off but can be
active
On
LIN transmission up to 20 kbps
nRST is floating but if OVCC is
reached this value may show up on
nRST pin
45 kΩ
(typical)
NA
Floating
Floating
Off
On
Weak current
pull-up
Failsafe mode is sleep mode with
LIMP on
Floating
Off
表9-2. Operating PIN Mode
LIN BUS
Termination
Mode
EN
RXD
Transmitter
Watchdog
nRST Pin
WAKE Pin
LIMP
Comment
nRST is internally
connected to the LDO
output which in sleep
mode is off
Sleep
Low
Floating
Low
Weak current pull-up
Off
Off
Floating
On
Off
Previous state
Wake-up event detected,
prior to entering waiting on processors to
Standby
Normal
Low
Off
On
Off
On
On
On
On
On
45 kΩ (typical)
45 kΩ (typical)
STBY
set EN
LIN Bus
Data
Off but can be
active
LIN transmission up to 20
kbps
High
nRST is floating but if
OVCC is reached this
value may show up on
nRST pin
TSD Off
NA
Floating
Off
Off
Floating
On
Off
45 kΩ (typical)
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Unpowered System
VSUP < UVSUP
WD: Off
VCC ≤ UVCC
After timer
timesout
250 ms
timer
Sleep
VCC > UVCC
Does not wait for
timer to timeout
Pin Control Mode
EN Pin State
SPI Control Mode
VSUP > UVSUP
EN = High
Note
*
VSUP ≥ UVSUP
Pin 9 = High
h‘0B[1]
Fail-Safe Mode
EN
To come out of Fail-Safe Mode the fault
must be cleared and the a wake event
must take place
Pin 9 = GND
WD: Off
LIMP: Off
Pin 9 State
*
If after 250ms all faults are not cleared
device will re-enter Fail-Safe Mode
h‘0B[1] = 1 Enables
VSUP > UVSUP
EN = Low
VSUP > UVSUP
h‘0B[1] = 0 (Disabled)
Fail Safe Mode
But does not enter this
mode
TSD Event
Any Non Fail-Safe
Enabled State
Tj > TSD
SOFT_RST
Tj > TSD
Standby Mode
TSD Off Mode
Fail-Safe Mode h‘0B[1] = 1
Standby Mode
Driver: Off
RXD: Low
Termination: 45 kΩ
reg0B[7:6] = 00
WD: Off
Driver: Off
RXD: Floating
LDO: Off
Termination: 45 kΩ
LIMP: Off
Tj < TSD
Driver: Off
RXD: Floating
Termination: Weak pullup
WD: Off
Tj < TSD
Note *
Driver: Off
RXD: Low
Termination: 45 kΩ
WD: Off
LDO: On
UVCC Events after
250ms timer expires
LDO: On
LIMP: State of the previous mode
LDO: Off
LIMP: On
LIMP: State of the previous mode
VSUP < UVSUP
VCC > OVCC
VSUP < UVSUP
LIN Bus Wake up
Or
WAKE toggled to GND
or VSUP
SPI Write
reg0B[7:6] = 00
VCC Overvoltage
Event
Unpowered State
Unpowered State
EN = High >
tMODE_CHANGE
LIN Bus Wake up or
WAKE toggled to GND or
VSUP
SPI Write
reg0B[7:6] = 10
VSUP < UVSUP
VSUP < UVSUP
VSUP < UVSUP
VSUP < UVSUP
Failsafe mode disabled
UVCC Events after
250ms timer expires
Normal Mode
Sleep Mode
Normal Mode
Sleep Mode
Driver: Off
RXD: Floating
Termination: Weak pullup
reg0B[7:6] = 01
WD: Off
Driver: On
RXD: LIN Bus Data
Termination: 45 kΩ
WD: On
LDO: On
LIMP: Off until first WD failure
Driver: Off
RXD: Floating
Termination: Weak pullup
WD: Off
Driver: On
RXD: LIN Bus Data
Termination: 45 kΩ
reg0B[7:6] = 10
WD: On
LDO: On
EN = Low > tMODE_CHANGE
SPI Write
reg0B[7:6] = 01
#
EN = High > tMODE_CHANGE
LDO: Off
LIMP: Off
VCC Overvoltage
Event
LDO: Off
LIMP: Off
LIMP: Off until first WD failure or
action forcing Failsafe if selected
Three consecutive correct
WD input triggers
UVCC Events after
250ms timer expires
VCC Overvoltage
Event
Three consecutive correct
WD input triggers
WD Failure Event
LIMP: On
Note
#
After entering Sleep Mode from a UVCC
event the 250ms timer will restart. After
it times out the EN pin will be monitored
and if high the device will enter normal
mode.
WD Failure Event
LIMP: On
图9-7. State Diagram with Failsafe
9.4.1 Normal Mode
If the EN pin is high at power up, the device powers up in normal mode and if low powers up in standby mode. In
normal operational mode, the receiver and transmitter are active and the LIN transmission up to the LIN
specified maximum of 20 kbps is supported. The receiver detects the data stream on the LIN bus and outputs it
on RXD for the LIN controller. A recessive signal on the LIN bus is a digital high and a dominant signal on the
LIN bus is a digital low. The driver transmits input data from TXD to the LIN bus. Normal mode is entered as EN
transitions high in Pin control mode or if reg0B[7:6] = 10 in SPI communication Mode. While in Pin control the
device is in sleep or standby mode for > tMODE_CHANGE
.
9.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN2441-Q1. Even with extremely low current consumption in
this mode, the device can still wake up from the LIN bus through a wake-up signal or if EN is set high for >
tMODE_CHANGE for the device. There is a 250 ms timer, tINACT_FS, that if UVCC is still present after this time the
device re-enters sleep mode. The LIN bus is filtered to prevent false wake up events. The wake-up events must
be active for the respective time periods (tLINBUS).
The sleep mode is entered by setting EN low for longer than tMODE_CHANGE when in pin control mode or by
setting reg0B[7:6] = 01 in SPI communication mode. In SPI control mode the device enters sleep mode through
a SPI write to the MODE register 8'h0B[7:6].
While the device is in sleep mode, the following conditions exist:
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short-circuited to ground). However, the weak current pull-up is active to prevent false wake up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
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• EN (in Pin Control Mode) input and LIN wake up receiver are active.
• WAKE pin is active.
9.4.3 Standby Mode
This mode is entered whenever a wake up event occurs through LIN bus while the device is in sleep mode. The
LIN bus responder termination circuit is turned on when standby mode is entered. Standby mode is signaled
through a low level on RXD. See Standby Mode Application Note for more application information.
When EN (in Pin Control Mode) is set high for longer than tMODE_CHANGE while the device is in standby mode the
device returns to normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are
enabled.
During power up, if EN is low the device goes into standby mode, and if EN is high, the device goes into normal
mode. EN has an internal pull-down resistor ensuring EN is pulled low if the pin is left floating in the system.
When in SPI communication mode the TLIN2441-Q1 enters standby mode by writing a 00 to reg0B[7:6] from
normal mode.
9.4.4 Failsafe Mode
When the TLIN2441-Q1 has certain fault conditions, the device enters a failsafe mode if this feature is enabled.
This mode turns on LIMP and brings all other function into lowest power mode state. Fault conditions are over
voltage on VCC, thermal shutdown, and four consecutive VCC undervoltage events. Once the fault conditions are
cleared, the device can be put back into standby mode from a wake event. If a fault condition is still in effect, the
device re-enters failsafe mode after 250 ms, tINACT_FS
.
9.4.5 Wake-Up Events
There are three ways to wake-up from sleep mode:
• Remote wake-up initiated by the falling edge of a recessive (high) to dominant (low) state transition on the
LIN bus where the dominant state is held for the tLINBUS filter time. After this tLINBUS filter time has been met
and a rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up
event eliminating false wake ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake-up through EN being set high for longer than tMODE_CHANGE
.
• Local wake up through WAKE pin being set high for longer than tMODE_CHANGE
.
9.4.5.1 Wake-Up Request (RXD)
When the TLIN2441-Q1 encounters a wake-up event from the LIN bus, RXD goes low and the device transitions
to standby mode until EN is reasserted high and the device enters normal mode. Once the device enters normal
mode, the RXD pin releases the wake-up request signal and the RXD pin then reflects the receiver output from
the LIN bus.
9.4.5.2 Local Wake Up (LWU) via WAKE Terminal
The WAKE terminal is a high voltage input terminal which can be used for local wake up (LWU) request via a
voltage transition. The terminal triggers a LWU event on a high to low or low to high transition. This terminal may
be used with a switch to ground or VSUP. If the terminal is not used, it should be connected to VSUP to avoid
unwanted parasitic wake up.
The LWU circuitry is active in sleep mode and standby mode. If a valid LWU event occurs, the device transitions
to standby mode. The LWU circuitry is not active in normal mode. To minimize system level current consumption,
the internal bias voltages of the terminal follows the state on the terminal with a delay of tWAKE(MIN). A constant
high level on WAKE has an internal pull up to VSUP and a constant low level on WAKE has an internal pull-down
to ground. On power up, this may look like a LWU event and could be flagged as such.
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Wake
Threshold
Not Crossed
t ≤ tWAKE
No Wake
UP
t ≥ tWAKE
Wake UP
Wake
Local Wake Request
RXD
*
Mode
Sleep Mode
Standby Mode
图9-8. Local Wake Up (LWU) - Rising Edge
Wake
Threshold
Not Crossed
t ≤ tWAKE
No Wake
UP
t ≥ tWAKE
Wake UP
WAKE
Local Wake Request
*
RXD
Mode
Sleep Mode
Standby Mode
图9-9. Local Wake Up (LWU) - Falling Edge
9.4.6 Mode Transitions
When the device is transitioning between modes, the device needs the time tMODE_CHANGE and tNOMINT to allow
the change to fully propagate from the EN pin through the device into the new state.
9.4.7 Voltage Regulator
The device has an integrated high-voltage LDO that operates over a 5.5 V to 36 V input voltage range for both
3.3 V and 5 V VCC. The device has an output current capability of 70 and support fixed output voltages of 3.3 V
(TLIN24413-Q1) or 5 V (TLIN24415-Q1). It features thermal shutdown and short-circuit protection to prevent
damage during over-temperature and over-current conditions
9.4.7.1 VCC
The VCC pin is the regulated output based on the required voltage. The regulated voltage accuracy is ± 2%. The
output is current limited. In the event that the regulator drops out of regulation, the output tracks the input minus
a drop based on the load current. When the input voltage drops below the UVSUP threshold, the regulator shuts
down until the input voltage returns above the UVSUPR level. The device monitors situations where VCC may drop
below the UVCC level thus causing the nRST pin to be pulled low. If after tINACT_FS timer times out and UVCC is
still present, the device enters sleep mode. This timer is approximately 250 ms at a minimum. When in PIN
mode the timer restarts and once times out, determines the state of the EN pin and enter the mode based upon
this state. In SPI mode and failsafe is turned off, it enters sleep mode. If failsafe is turned on, the device enters
failsafe mode. An over voltage on VCC, OVCC is also monitored. If the device is in Pin mode, it enters sleep
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mode. Once in sleep mode, the device waits for 250 ms and then check the status of the EN pin. If high, the
device enters normal mode. If the OVCC event is still present, the device enters sleep mode and wait for 250 ms
and check the EN pin status. This continues until either the EN pin is low or the OVCC event is cleared. If the
device is in SPI mode, the state the device enters depends upon whether failsafe is enabled. If enabled, the
device enters failsafe mode, if not it enters sleep mode. If the voltage exceeds the absolute max on the VCC pin,
the device could be damaged.
9.4.7.2 Output Capacitance Selection
For stable operation over the full temperature range and with load currents up to 70 mA on VCC a certain
capacitance is expected and depends upon the minimum load current. To support no load to full load a value of
10 µF and ESR smaller than 2 Ω is needed. For 500 µA to full load an 1 µF capacitance can be used. The low
ESR recommendation is to improve the load transient performance.
9.4.7.3 Low-Voltage Tracking
At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage
based on the load current (IL) and power-switch resistor. This tracking allows for a smaller input capacitance and
can possibly eliminate the need for a boost converter during cold-crank conditions.
9.4.7.4 Power Supply Recommendation
The device is designed to operate from an input-voltage supply range between 5.5 V and 36 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device. The recommended
minimum capacitance at the pin is 100 nF . The max voltage range is for the LIN functionality. Exceeding 24V for
the LDO reduces the effective current sourcing capability due to thermal considerations.
9.4.8 Watchdog
The TLIN2441-Q1 has an integrated watchdog function. This can be programmed by pin control or SPI
communication control based upon the state of the PIN/nCS pin at power up. The device provides a default
window based watchdog as well as a selectable time-out watchdog using the SPI programming. The watchdog
timer does not start until the first input trigger event when in normal operation mode. The watchdog timer is only
operational in normal mode and is off in standby and sleep modes. The LIMP pin provides a limp home
capability when connected to external circuitry. When in sleep or standby mode, the limp pin is off. When the
error counter reaches the watchdog trigger event level, the LIMP pin turns on connecting VSUP to the pin as
described in the LIMP pin section.
9.4.8.1 Watchdog Error Counter
The TLIN2441-Q1 has a watchdog error counter. This counter is an up down counter that increments for every
missed window or incorrect input watchdog trigger event. For every correct input trigger, the counter decrements
but does not drop below zero. The default trigger for this counter to trigger a nWDR output trigger is for every
event. On every WD error event, the nWDR pin goes low as a watchdog error output trigger. For Pin control, the
value is on every event. In SPI communication mode, this counter can be changed to the fifth or ninth
consecutive incorrect input trigger. The error counter can be read at register 8'14[4:1].
The error counter is set at four by default. This means that when the watchdog error count is set at five and the
first input failure is treated as if the fifth event has taken place. When set at nine and no correct inputs, the fifth
event is treated as the failure event. This allows the system to check the counter after the first input trigger to see
if a valid input was sent. nINT is pulled low on each incorrect watchdog input while VCC and nWDR behaves
according to register configuration
9.4.8.2 Pin Control Mode
When using pin control for programming the watchdog, the WDT pin is used for this function. WDT sets the total
window size of the window watchdog. It can be connected to VCC, GND or left open. The electric table provides
the window values. The ratio between the upper (open window) and lower (closed window) is 50/50. WDI pin is
used by they controller to trigger the watchdog input. The WDI input is an edge-triggered event and supports
both rising and falling edges. A filter time of tW is used to avoid noise or glitches causing a false trigger. A pulse
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would be treated as a two input trigger events and cause the nWDR pin to be pulled low. nWDR pin is connected
to the controller reset pin and if a watchdog event happens this pin is pulled low.
9.4.8.3 SPI Control Programming
When pin 9 (PIN/nCS) is connected to a high-Z processor I/O the device is configured for SPI communication.
Registers 8’h13 through 8’h15 control the watchdog function when the device is in SPI communication mode.
These register are provided in 表 9-3. The device watchdog can be set as a time-out watchdog or window
watchdog by setting 8’h13[6] to the method of choice. The timer is based upon reg8’h13[3:2] WD prescaler
and reg8’h14[7:5] WD timer and is in ms. See 表9-3 for the achievable times.
表9-3. Watchdog Window and Time-out Timer Configuration (ms)
WD_TIMER
reg13[5:4] WD_PRE
(ms)
reg14[7:5]
000
00
4
01
8
10
12
11
16
001
32
64
96
128
010
128
256
512
2048
10240
RSVD
256
384
512
011
384
512
768
100
1024
4096
20240
RSVD
1536
6144
RSVD
RSVD
2048
8192
RSVD
RSVD
101
110
1111
9.4.8.4 Watchdog Timing
The TLIN2441-Q1 provides two methods for setting up the watchdog when in SPI communication mode, Window
or Time-out. If more frequent, < 64 ms, input trigger events are desired it is suggested to us the Time-out timer.
When using Time-out watchdog the input trigger can occur anywhere before the timeout and is not tied to an
open window.
When using the window watchdog it is important to understand the closed and open window aspects. The device
is set up with a 50%/50% open and closed window and is based on an internal oscillator with a ±10% accuracy
range. To determine when to provide the input trigger, this variance needs to be taken into account. Using the 64
ms nominal total window provides a closed and open window that are each 32 ms. Taking the ± 10% internal
oscillator into account means the total window could be 57.6 ms or 70.4 ms. The closed and open window would
then be 22.4 ms or 35.2 ms. From the 57.6 ms total window and 35.2 ms closed window the total open window is
22.4 ms. The trigger event needs to happen at the 46.4 ms ±11.2 ms. The same method is used for the other
window values. 图8-19 provides the above information graphically.
9.5 Programming
The TLIN2441-Q1 is 7 bit address access SPI communication port.
The Addresses for each area of the device are as follows
• Register 8’h00 through 0A are Device ID and Revision Registers
• Register 8’h0B through 10 are device configuration registers and Interrupt Flags
• Register 8’h11 through 12 are for read and write scratch pad
• Register 8'h13 through 15 are for the watchdog read and write scratch pad
9.5.1 SPI Communication
The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select
Not), SDI (SPI Data In), SDO (SPI Data Out) and CLK (SPI Clock). Each SPI transaction is an 8 bit word
containing a seven bit address with a R/W bit followed by a data byte. The data shifted out on the SDO pin for
the transaction always starts with the register h'0C[7:0] which is the interrupt register. This register provides the
high level interrupt status information about the device. The data byte which are the ‘response’ to the
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address and R/W byte are shifted out next. Data bytes shifted out during a write command is content of the
registers prior to the new data being written and updating the registers. Data bytes shifted out during a read
command are the content of the registers and the registers are updated.
The SPI data input data on SDI is sampled on the low to high edge of CLK. The SPI output data on SDO is
changed on the high to low edge of CLK.
9.5.1.1 Chip Select Not (nCS)
This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high the
SPI Data Output (SDO) pin of the device is high impedance allowing an SPI bus to be designed. When nCS is
low the SDO driver is activated and communication may be started. The nCS pin is held low for a SPI
transaction. A special feature on this device allows the SDO pin to immediately show the Global Fault Flag on a
falling edge of nCS.
9.5.1.2 Serial Clock Input (CLK)
This input pin is used to input the clock for the SPI to synchronize the input and output serial data bit streams.
The SPI Data Input is sampled on the rising edge of CLK and the SPI Data Output is changed on the falling
edge of the CLK. See 图9-10.
ACTIONs: C = data capture, S = data shift,
SPI CLOCKING
MODE 0 (CPOL = 0, CPHA = 0)
L = load data out, P = process captured data
nCS
CLK
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SDI, SDO
ACTION
L
C
S
C
S
C
S
C
S
C
S
C
S
C
S
C
L
C
S
C
S
C
S
C
S
C
S
C
S
C
S
C
P
P
INTERNAL
CLK
INTERNAL_CLK = !CS xor CLK
图9-10. SPI Clocking
9.5.1.3 Serial Data Input (SDI)
This input pin is used to shift data into the device. Once the SPI is enabled by a low on nCS, the SDI samples
the input shifted data on each rising edge of the SPI clock (SCK). The data is shifted into an 8 bit shift register.
After eight (8) clock cycles and shifts, the addressed register is read giving the data to be shifted out on SDO.
After eight clock cycles, the shift register is full and the SPI transaction is complete. If the command code was a
writes the new data is written into the addressed register only after exactly 8 bits have been shifted in by CLK
and the nCS has a rising edge to deselect the device. If there are not exactly 8 bits shifted in to the device the
during one SPI transaction (nCS low), the SPI command is ignored, the SPIERR flag is set and the data is not
written into the device preventing any false actions by the device.
9.5.1.4 Serial Data Output (SDO)
This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS,
the SDO is immediately driven high or low showing the Global Fault Flag status which is also the first bit (bit 7) to
be shifted out if the SPI is clocked. On the first falling edge of CLK, the shifting out of the data continues with
each falling edge on CLK until all 8 bits have been shifted out the shift register.
See 图9-11 and 图9-12 for read and write method.
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nCS
CLK
SDI
R/W
= 1
ADDRESS [6:0]
DATA [7:0]
SDO
Z[0C[7:0]
Interrupt
Register
图9-11. SPI Write
nCS
CLK
SDI
R/W
= 0
ADDRESS [6:0]
SDO
Z[0C[7:0]
Interrupt
Register
DATA [7:0]
图9-12. SPI Read
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9.6 Registers
The following tables contain the registers that the device use during SPI communication
表9-4. Device ID and Revision
ADDRESS
‘h00
‘h01
‘h02
‘h03
‘h04
‘h05
‘h06
‘h07
‘h08
‘h09
‘h0A
REGISTER
VALUE
54
ACCESS
Reserved
R
R
R
R
R
R
R
R
R
R
R
Reserved
43
Reserved
41
Reserved
4E
Reserved
32
DEVICE_ID[7:0] "4"
DEVICE_ID[7:0] "4"
DEVICE_ID[7:0] "1"
DEVICE_ID[7:0] “3”"5"
Rev_ID Major
REV_ID Minor
34
34
31
33,35
01
00
表9-5. Device Configuration and Flag Registers
ADDRESS
BIT(S)
DEFAULT
DESCRIPTION
ACCESS
MODE: Modes of Operation
00 = Standby Mode
01 = Sleep Mode
10 = Normal Mode
11 = Reserved
7:6
2'b00
R/W/U
LIMP_DIS: LIMP Disable
0 = LIMP Enabled
5
1'b0
R/W/U
R/W
1 = LIMP Disabled
LIMP_SEL_RESET: Selects the method LIMP is reset/
turned off
00 = On the third successful input trigger the error counter
receives
'h0B
4:3
2'b00
01 = First correct input trigger
10 = SPI write 1 to h'0B[2]
11 = Reserved
2
1
1'b0
1'b0
LIMP Reset - Writing a one resets LIMP but then clears
R/WC
R/W
FAILSAFE_EN: Fail safe mode enable
0 = Disabled
1 = Enabled
DTO_DIS: Dominant timeout Disable
0 = DTO Enabled
0
1'b0
R/W
1 = DTO Disabled
7
6
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
8'h00
DTO Interrup
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R
UVCC Interrupt
TSD Interrupt
SPIERR Interrupt
WDERR Interrupt
OVCC Interrupt
LWU Interrupt
WUP Interrupt
Reserved
5
4
'h0C
'h0D
3
2
1
0
7:0
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ADDRESS
表9-5. Device Configuration and Flag Registers (continued)
BIT(S)
DEFAULT
DESCRIPTION
ACCESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
7
6
1'b1
DTO Interrupt Mask
UVCC Interrupt Mask
TSD Interrupt Mask
1'b1
5
1'b1
4
1'b1
SPIERR Interrupt Mask
WDERR Interrupt Mask
OVCC Interrupt Mask
LWU Interrupt Mask
WUP Interrupt Mask
Reserved
'h0E
3
1'b1
2
1'b1
1
1'b1
0
1'b1
'h0F
'h10
7:0
7:4
8'h00
4'b0000
Reserved
R
nRST_nWDR_SEL: Pin 12 configuration select when in
SPI mode.
00 = nRST (Default)
01 = nWDR
3:2
1'b0
R/W
10 = Both nRST for UVCC and nWDR for watchdog failure
event
11 = Reserved
1
0
1'b0
1'b0
Reserved
R
SOFT_RST: Soft reset of device. Writing a 1 resets the
registers to default values
R/WC
表9-6. Device Watchdog Registers
ADDRESS
'h11
BIT(S)
7:0
DEFAULT
DESCRIPTION
ACCESS
R/W
8'h00
Read and Write Capable Scratch Pad
Read and Write Capable Scratch Pad
'h12
7:0
8'h00
R/W
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表9-6. Device Watchdog Registers (continued)
ADDRESS
BIT(S)
DEFAULT
DESCRIPTION
ACCESS
WD_DIS - Watchdog Function Disable
0 = Enabled
7
1'b0
R/W
1 = Disabled
WD_WINDOW_TIMEOUT_SEL: Configures Watchdog as
either a Window or Time-out watchdog
0 = Window
1 = Timeout
6
1'b0
R/W
R/W
WD_PRE: Watchdog prescalar
00 = Factor 1
01 = Factor 2
10 = Factor 3
11 = Factor 4
5:4
2'b00
WD_ERR_CNT_SET Sets the watchdog event error
counter that upon overflow the watchdog output trigger
event taked place. Increases with each error and
decreases with each correct WD trigger. Does not go
below zero.
00 = Immediate trigger on each WD event
01 = 2-Bit: Triggers on the fifth error event
10 = 3-Bit: Triggers on the ninth error event
11 = Reserved
'h13
3:2
2'b00
R/W
WD_ACTION: Selection Action when Watchdog times out
or misses a window
00 = nINT is pulled low
1:0
7:5
2'b10
R/W
R/W
01 = VCC is turned off for 100 ms and turned back on
10 = nWDR is toggled high →low →high
11 = Reserved
WD_TIMER - Sets the window or timeout times and is
based upon the WD_PRE setting - See 表9-3
3'b000
'h14
'h15
WD_ERR_CNT: Watchdog error counter: Keeps a running
count of the errors up to 15 errors
4:1
0
4'b0100
1'b0
R
R
Reserved
WD_TRIG: Writes to these bits resets the watchdog timer
(FF)
7:0
8'h00
WC
备注
For WD_ACTION turning off VCC for 100 ms and turning it back on, causes SPI communication to
stop during the off time.
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TLIN2441-Q1 can be used as both a responder device and a commander device in a LIN network. The
device comes with the ability to support a remote wake-up requestsand local wake up request. It can provide the
power to the local processoras well as providing watchdog supervision for the processor.
10.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for responder node applications.
For commander node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. 图
10-1 show the device in pin control mode for a responder application. 图 10-2 shows the device in SPI control
mode in a responder application.
SW
3 k
VSUP
GND
10
F
10 nF
33 k
GND
10
F
10
F
GND
WAKE
GND
GND
VCC
VSUP
100 nF(4)
VDD
14
8
13
1
WDI
10 k
RESPONDER
NODE(3)
GND
I/O
LIN
5
2
GND
EN
I/O
I/O
3
200 pF
GND
nRST
12
nWDR
Reset
7
LIMP
WDT
MCU w/o
pullup(2)
VDD I/O
MCU
6
LIN Controller
Or
11
10
RXD
TXD
SCI/UART(1)
GND
GND
4
9
GND
GND
(1) If RXD on MCU or LIN responder has internal pullup; no external pullup resistor is needed.
(2) If RXD on MCU or LIN responder does not have an internal pullup requires external pullup resistor.
(3) Commander node applications require and external 1 k pullup resistor and serial diode.
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF
图10-1. Typical LIN Controller in Pin Control Mode
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SW
3 k
VSUP
GND
10
F
10 nF
33 k
GND
10
F
10 F
GND
WAKE
GND
GND
VCC
VSUP
100 nF(4)
VDD
14
13
1
nCS
SDI
9
RESPONDER
NODE(3)
8
SDO
SPI
GND
7
6
CLK
LIN
5
2
200 pF
GND
nINT
3
I/O
nWDR
LIMP
12
I/O
MCU w/o
MCU
pullup(2)
VDD I/O
LIN Controller
Or
11
10
RXD
TXD
SCI/UART(1)
GND
4
GND
GND
(1) If RXD on MCU or LIN responder has internal pullup; no external pullup resistor is needed.
(2) If RXD on MCU or LIN responder does not have an internal pullup requires external pullup resistor.
(3) Commander node applications require and external 1 k pullup resistor and serial diode.
(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF
图10-2. Typical LIN Controller in SPI Control Mode
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10.2.1 Design Requirements
10.2.1.1 Normal Mode Application Note
When using the TLIN2441-Q1 in systems which are monitoring the RXD pin for a wake-up request, special care
should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition period
between states as the receivers are switched. The application software should not look for an edge on the RXD
pin indicating a wake-up request until tMODE_CHANGE. This is shown in 图8-15 when transitioning to normal mode
there is an initialization period shown as tNOMINIT
.
10.2.1.2 Standby Mode Application Note
If the TLIN2441-Q1 detects an under voltage on VSUP, the RXD pin transitions low and would signal to the
software that the device is in standby mode and should be returned to sleep mode for the lowest power state.
10.2.1.3 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for commander and responder node applications;
thus, there are different maximum consecutive dominant bits for each application case and thus different
minimum data rates.
10.2.2 Detailed Design Procedures
For processors or LIN responder nodes with an internal pull-up on RXD, no external pull-up resistor is needed.
For processors or LIN responder nodes without internal pull-up on RXD, an external pull-up resistor is required.
Commander node applications require an external 1 kΩ pull-up resistor and serial diode.
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10.2.3 Application Curves
Characteristic curves below show the LDO performance between 0 V and 5.5 V when ramping up and ramping
down.
5
4.5
4
3.6
3.3
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
3.5
3
2.5
2
1.5
1
-40°C
25°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
0.5
0
-0.5
-0.3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D013
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D028
VSUP (V)
VSUP (V)
VCC = 5 V
ICC Load = 70 mA Ramp Up
VCC = 3.3 V
ICC Load = 70 mA Ramp Up
图10-3. VCC vs VSUP Across Temperature
图10-4. VCC vs VSUP Across Temperature
5
4.5
4
3.6
3.3
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
3.5
3
2.5
2
1.5
1
-40°C
25°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
0.5
0
-0.5
-0.3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D014
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D022
VSUP (V)
VSUP (V)
VCC = 5 V
ICC Load = 70 mA Ramp Down
VCC = 3.3 V
ICC Load = 70 mA Ramp Up
图10-5. VCC vs VSUP Across Temperature
图10-6. VCC vs VSUP Across Temperature
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
-40°C
25°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
0
0
-5
-5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D005
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D024
VSUP (V)
VSUP (V)
VCC = 5 V
ICC Load = 70 mA Ramp Up
VCC = 3.3 V
ICC Load = 70 mA Ramp Up
图10-7. ISUP vs VSUP Across Temperature
图10-8. ISUP vs VSUP Across Temperature
9
7.5
8.5
8
7
6.5
6
7.5
7
5.5
5
6.5
6
4.5
4
5.5
5
3.5
3
4.5
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
-40°C
25°C
85°C
105°C
125°C
-40°C
25°C
85°C
105°C
125°C
0.5
0
-0.5
-1
-0.5
-1
-1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D046
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
D033
VSUP (V)
VSUP (V)
VCC = 5 V
Sleep Mode
Ramp Down
VCC = 3.3 V
Sleep Mode
Ramp Down
图10-9. ISUP vs VSUP Across Temperature
图10-10. ISUP vs VSUP Across Temperature
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图10-11. Recessive to Dominant Propagation
图10-12. Dominant to Recessive Propagation
Delay
Delay
11 Power Supply Recommendations
The TLIN2441-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 5.5 V
to 45 V. A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible.
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12 Layout
PCB design should start with understanding that frequency bandwidth from approximately 3 MHz to 3 GHz is
needed thus high frequency layout techniques must be applied during PCB design. Placement at the connector
also prevents these noisy events from propagating further into the PCB and system.
12.1 Layout Guidelines
• Pin 1 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
• Pin 2 (LIMP): This pin is connected to external circuitry for a limp home mode if the watchdog has timed out
causing a reset
• Pin 3 (EN/nINT): When in pin control mode, this pin is the EN and is an input pin that is used to place the
device in a low power sleep mode. If this feature is not used, the pin should be pulled high to the regulated
voltage supply of the microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally,
a series resistor may be placed on the pinto limit current on the digital lines in the event of an over voltage
fault. When in SPI communication mode, this pin becomes an output interrupt pin that is provided to the
processor.
• Pin 4 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
• Pin 5 (LIN): This pin connects to the LIN bus. For responder node applications, a 200 pF capacitor to ground
is implemented. For commander node applications, an additional series resistor and blocking diode should be
placed between the LIN pin and the VSUP pin. See 图9-3.
• Pin 6 (WDT/CLK): In pin control mode, this pin can be connected to VCC, GND or left open. In SPI
communication mode, this pin is connected directly to the processor as the SPI CLK input.
• Pin 7 (nWDR/SDO): In pin control mode. this pin is connected to the processors reset pin. In SPI
communication mode. this pin is connected directly to the processor as the SPI serial data output from the
TLIN2441-Q1
• Pin 8 (WDI/SDI): In pin control mode, this input pin is connected to the processor. A 10 kΩresistor should be
connected to GND to avoid false triggers upon power up. In SPI communication mode, this pin is connected
directly to the processor as the SPI serial data input into the TLIN2441
• Pin 9 (PIN/nCS): For pin control mode, this pin should be connected directly to ground. For SPI
communication mode, this pin should be connected directly to the processor.
• Pin 10 (RXD): The pin is an open-drain output and requires and external pull-up resistor in the range of 1 kΩ
to 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an integrated
pull-up, an external resistor should be placed between RXD and the regulated voltage supply for the
microprocessor. If RXD is connected to the VCC pin a higher pull-up resistor value can be used to reduce
standby current.
• Pin 11 (TXD): The TXD pin is the transmit input signal to the device from the processors. A series resistor
can be placed to limit the input current to the device in the event of an over voltage on this pin. A capacitor to
ground can be placed close to the input pin of the device to filter noise.
• Pin 12 (nRST/nWDR): By default this pin connects to the processors GPIO to function as an interrupt or
reset pin for an under voltage event. For SPI communication mode, this pin can be programmed as a
processor reset due to a watchdog failure event.
• Pin 13 (WAKE):This pin connects to VSUP through a resistor divider with the center tap connected to a switch
to ground or VVSUP and is used as the local wake up pin. A 10 nF capacitor to ground should be placed at
this center tap as shown in the application drawings.
• Pin 14 (VCC): Output source, either 3.3 V or 5 V depending upon the version of the device and has
decoupling capacitors to ground.
备注
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
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12.2 Layout Example
VSUP
VSUP
VCC
10 µF
100 nF
GND
GND
To
WAKE
Switch
LIMP
EN
33 kΩ
nRST
TXD
GND
GND
RXD
LIN
WDT
PIN/nCS
GND
GND
nWDR
WDI
VCC
GND
GND
图12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
TLIN1441-Q1 and TLIN2441-Q1 Duty Cycle Over VSUP
For related documentation see the following:
• LIN Standards:
– ISO/DIS 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
– ISO/DIS 17987-4: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
– SAE J2602-1: LIN Network for Vehicle Applications
– LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification
• EMC requirements:
– SAE J2962-2: TBD
– HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for LIN
– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz -
Part 4: Direct RF power injection method
– IEC 61967-4
– CISPR25
• Conformance Test requirements:
– ISO/DIS 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
– SAE J2602-2: LIN Network for Vehicle Applications Conformance Test
TLINx441 LDO Performance, SLLA427
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Feb-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLIN24413DMTRQ1
TLIN24413DMTTQ1
TLIN24415DMTRQ1
TLIN24415DMTTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
DMT
DMT
DMT
DMT
14
14
14
14
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TL413
SN
SN
SN
TL413
TL415
TL415
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Feb-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLIN24413DMTRQ1
TLIN24413DMTTQ1
TLIN24415DMTRQ1
TLIN24415DMTTQ1
VSON
VSON
VSON
VSON
DMT
DMT
DMT
DMT
14
14
14
14
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.2
3.2
3.2
3.2
4.7
4.7
4.7
4.7
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLIN24413DMTRQ1
TLIN24413DMTTQ1
TLIN24415DMTRQ1
TLIN24415DMTTQ1
VSON
VSON
VSON
VSON
DMT
DMT
DMT
DMT
14
14
14
14
3000
250
367.0
213.0
367.0
213.0
367.0
191.0
367.0
191.0
38.0
35.0
38.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DMT 14
3 x 4.5, 0.65 mm pitch
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225088/A
www.ti.com
PACKAGE OUTLINE
DMT0014A
VSON - 0.9 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
A
A
2X
3.9
15
SYMM
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
14X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
4223033/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
(
0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223033/B 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4223033/B 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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