概述
数据手册
替代型号TLK4211EA 概述
4.25 Gbps Cable and PC Board Equalizer 4.25 Gbps的电缆和PC主板均衡器
TLK4211EA 数据手册
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www.ti.com
SLLS655–NOVEMBER 2005
4.25 Gbps Cable and PC Board Equalizer
FEATURES
APPLICATIONS
•
1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre
Channel Systems
•
•
•
Multi-Rate Operation Up To 4.25 Gbps
Compensates Up To 12 dB Loss At 2.1 GHz
•
High Speed Links In Communication and Data
Systems
Suitable To Receive 4.25-Gbps Data Over Up
To 30 Inches (0,76 Meters) Of FR4 PC Boards
•
•
Backplane Interconnect
Rack-to-Rack Interconnect
•
Suitable To Receive 4.25-Gbps Data Over Up
To 30 Feet (9,1 Meters) Of CX4 Cable
•
•
•
•
•
•
•
•
Ultra-Low Power Consumption
Input Offset Cancellation
High Input Dynamic Range
Output Disable
Output Polarity Select
CML Data Outputs
Single 3.3-V Supply
Surface Mount Small Footprint 3 mm × 3 mm
16-Pin QFN Package
DESCRIPTION
The TLK4211EA is a versatile high-speed limiting equalizer for applications in digital high-speed links with data
rates up to 4.25 Gbps.
This device provides a high frequency boost of 12 dB at 2.1 GHz as well as sufficient gain to ensure a fully
differential output swing for input signals as low as 200 mVp-p (at the input of the interconnect line).
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 2000 mVp-p.
The TLK4211EA is available in a small footprint 3 mm × 3 mm 16-pin QFN package. It requires a single 3.3-V
supply.
This power efficient equalizer is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
BLOCK DIAGRAM
A simplified block diagram of the TLK4211EA is shown in Figure 1.
This compact, low-power 4.25-Gbps equalizer consists of a high-speed data path with offset cancellation
circuitry, a bandgap voltage reference, and bias current generation block.
The equalizer requires a single 3.3-V supply voltage. All circuit parts are described in detail in below.
COC2 COC1
Bandgap Voltage
Reference and
Bias Current
Generation
VCC
OUTPOL
Offset
Cancellation
GND
VCC
DIN+
DIN−
DOUT+
DOUT−
+
+
+
+
−
−
−
−
Fixed Equilizer
Stage
Gain Stage
Gain Stage
Gain Stage
CML
Output
Buffer
Stage
DISABLE
B0052-02
Figure 1. Simplified Block Diagram of the TLK4211EA
HIGH-SPEED DATA PATH
The high-speed data signal with frequency dependent loss is applied to the data path by means of the input
signal pins DIN+/DIN–. The data path consists of the fixed equalizer input stage with 100-Ω differential on-chip
line termination, three gain stages, which provide the required gain to ensure a limited output signal, and a CML
output stage. The equalized and amplified data output signal is available at the output pins DOUT+/DOUT–,
which provide 2 × 50-Ω back-termination to VCC. The output stage also includes a data polarity switching
function, which is controlled by the OUTPOL input, and a disable function controlled by the signal applied to the
DISABLE input pin.
An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even for
small input data signals.
The low frequency cutoff is as low as 10 kHz with the built-in filter capacitor.
For applications which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
BANDGAP VOLTAGE AND BIAS GENERATION
The TLK4211EA equalizer is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This
voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
PACKAGE
The TLK4211EA is available in a small footprint 3 mm × 3 mm, 16-pin QFN package with a lead pitch of 0,5 mm.
The pin out is shown below in Figure 2.
2
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
RGT PACKAGE
(TOP VIEW)
16 15 14 13
1
2
3
4
12
VCC
DIN+
DIN−
VCC
VCC
11
10
9
DOUT+
DOUT−
OUTPOL
EP
5
6
7
8
P0019-02
Figure 2. Pin Out of TLK4211EA in a 3 mm × 3 mm 16-Pin QFN Package
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
VCC
1, 4 , 12
Supply
3.3-V ±10% supply voltage
DIN+
DIN–
NC
2
3
Analog in
Analog in
Non-inverted data input. On-chip 100-Ω terminated to DIN–
Inverted data input. On-chip 100-Ω terminated to DIN+
Not connected
5, 7, 13
6
DISABLE
GND
CMOS in
Supply
Disables CML output stage when set to high level
Circuit ground.
8, 16
Output data signal polarity select (internally pulled up):
Setting to high-level or leaving pin open selects normal polarity.
Low-level selects inverted polarity.
OUTPOL
9
CMOS in
DOUT–
DOUT+
10
11
CML out
CML out
Inverted data output. On-chip 50-Ω back-terminated to VCC.
Non-inverted data output. On-chip 50-Ω back-terminated to VCC.
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this
pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins
14 and 15).
COC1
14
Analog
Analog
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this
pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins
14 and 15).
COC2
EP
15
EP
Exposed die pad (EP) must be grounded.
3
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
VCC
Supply voltage(2)
Voltage at DIN+, DIN–(2)
Voltage at DISABLE, OUTPOL, DOUT+, DOUT–, COC1, COC2(2)
–0.3 V to 4 V
0.5 V to 4 V
–0.3 V to 4 V
VDIN+, VDIN–
VDISABLE, VOUTPOL, VDOUT+
VDOUT–, VCOC1, VCOC2
,
VCOC,DIFF
Differential voltage between COC1 and COC2
Differential voltage between DIN+ and DIN–
Continuous current at inputs and outputs
ESD rating at all pins
±1 V
±2.5 V
VDIN,DIFF
IDIN+, IDIN–, IDOUT+, IDOUT–
– 25 mA to 25 mA
2.5 kV (HBM)
125°C
ESD
TJ(max)
TSTG
TA
Maximum junction temperature
Storage temperature range
–65°C to 85°C
–40°C to 85°C
260°C
Characterized free-air operating temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
TL
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX
3.6
UNIT
V
VCC
TA
Supply voltage
3.3
Operating free-air temperature
CMOS input high voltage
CMOS input low voltage
–40
2.1
85
°C
V
0.6
V
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions, typical operating condition is at VCC = 3.3 V and TA = 25°C(unless otherwise noted)
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
TYP
3.3
30
MAX UNIT
VCC
ICC
3
3.6
38
V
mA
Ω
Supply current
DISABLE = low, including CML output current
Differential
RIN
Data input resistance
Data output resistance
100
50
ROUT
Single-ended to VCC
Ω
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions, typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
COC = open
50
Low frequency –3 dB
bandwidth
kHz
COC = 0.22 µF
0.8
Data rate
4.25
Gbps
mVp-p
mVp-p
dB
VIN,MIN
VIN,MAX
Data input sensitivity(1)
Data input overload
High frequency boost
BER < 10–12, voltage at the input of the interconnect line
Voltage at the input of the interconnect line
f = 2.1 GHz
200
250
2000
12
0.25
780
DISABLE = high
10
Differential data output
voltage swing
VOD
mVp-p
DISABLE = low
580
1200
(1) The given differential input signal swing is measured at the input of the interconnect line. The high frequency components of the signal
at the output of the interconnect line (which is connected the input pins DIN+/DIN– of the TLK4211EA) may be attenuated by 0 dB up to
12 dB at 2.1 GHz dependent of the interconnect line length.
4
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
AC ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions, typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
20
MAX
UNIT
No board or cable
12 inches of 7 mils wide microstrip interconnect line on
standard FR4
30
Deterministic jitter,
4.25 Gbps, K28.5 pattern,
VIN = 200 mVpp
(differential voltage at the
cable input)
24 inches of 7 mils wide microstrip interconnect line on
standard FR4
30
30
psp-p
36 inches of 7 mils wide microstrip interconnect line on
standard FR4
DJ
RJ
30 feet CX4 cable
No board or cable
20
20
25
Deterministic jitter,
3.3 Gbps, K28.5 pattern,
VIN = 200 mVpp
(differential voltage at the
cable input)
48 inches of 7 mils wide microstrip interconnect line on
standard FR4
psp-p
30 feet CX4 cable
20
Random jitter
Input = 200 mVp-p, 36 inches of 7 mils wide stripline
interconnect line on standard FR4 (voltage at the input of the
interconnect line)
4.5
psRMS
Latency
From DIN± to DOUT±
250
55
ps
ps
ps
ns
tr
Output rise time
Output fall time
Disable response time
20% to 80%, without microstrip line loss at input
20% to 80%, without microstrip line loss at input
85
85
tf
55
TDIS
20
5
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
APPLICATION INFORMATION
Figure 3 shows the TLK4211EA connected with an ac-coupled interface to the data signal source via a microstrip
interconnect line. The output load is ac-coupled as well.
The ac coupling capacitors C1 through C4 in the input and output data signal lines are the only required external
components. In addition, if a low cutoff frequency is required, as an option, an external filter capacitor COC may
be used.
C
OC
Optional
VCC
VCC
VCC
0 Inch to 30 Inches
Stripline on FR4
C
C
C
C
1
3
DIN+
DIN−
DIN+
DIN−
DOUT+
DOUT+
DOUT−
OUTPOL
TLK4211EA
16-Pin QFN
2
4
DOUT−
VCC
OUTPOL
DISABLE
S0072-02
Figure 3. Basic Application Circuit With AC Coupled I/Os
6
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted).
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT 4.25 GBPS
USING A K28.5 PATTERN
No Stripline
No Stripline
Time − 1 ns/Div
Time − 100 ps/Div
12 Inches x 7 mil Stripline
12 Inches x 7 mil Stripline
Time − 1 ns/Div
Time − 100 ps/Div
24 Inches x 7 mil Stripline
24 Inches x 7 mil Stripline
Time − 1 ns/Div
Time − 100 ps/Div
36 Inches x 7 mil Stripline
36 Inches x 7 mil Stripline
Time − 1 ns/Div
Time − 100 ps/Div
G001
Figure 4. Equalizer Input and Output Signals With Different Interconnect Lines Patterns
7
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted).
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT 3.3 GBPS
USING A K28.5 PATTERN
No Stripline
No Stripline
Time − 1 ns/Div
Time − 100 ps/Div
24 Inches x 7 mil Stripline
24 Inches x 7 mil Stripline
Time − 1 ns/Div
Time − 100 ps/Div
48 Inches x 7 mil Stripline
48 Inches x 7 mil Stripline
Time − 1 ns/Div
Time − 100 ps/Div
G002
Figure 5. Equalizer Input and Output Signals With Different Interconnect Lines and Data
8
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted).
TRANSFER CHARACTERISTIC OF
STRIPLINE INTERCONNECT LINES
RANDOM JITTER
vs
INPUT AMPLITUDE
0
−5
10
9
8
7
6
5
4
3
2
1
0
12” Stripline
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
24” Stripline
36” Stripline
36” Stripline
48” Stripline
0” Stripline
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
1
2
3
4
5
6
f − Frequency − GHz
V
ID
− Differential Input Voltage − V
P−P
G003
G004
Figure 6.
Figure 7.
DETERMINISTIC JITTER 4.25 GBPS
vs
INPUT AMPLITUDE (K28.5 PATTERN)
DETERMINISTIC JITTER 4.25 GBPS
vs
STRIPLINE INTERCONNECT LINE LENGTH
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
15
2
− 1 PRBS
0” Stripline
36” Stripline
K28.5
0
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0
5
10 15 20 25 30 35 40 45 50
Stripline Length − Inches
V
ID
− Differential Input Voltage − V
P−P
G005
G006
Figure 8.
Figure 9.
9
TLK4211EA
www.ti.com
SLLS655–NOVEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted).
DIFFERENTIAL INPUT RETURN GAIN
DIFFERENTIAL OUTPUT RETURN GAIN
vs
vs
FREQUENCY
FREQUENCY
0
−5
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
0
1
2
3
4
5
6
0
1
2
3
4
5
6
f − Frequency − GHz
f − Frequency − GHz
G007
G008
Figure 10.
Figure 11.
10
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLK4211EARGTR
TLK4211EARGTRG4
TLK4211EARGTT
NRND
NRND
NRND
QFN
QFN
QFN
RGT
RGT
RGT
16
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TLK4211EARGTTG4
NRND
QFN
RGT
16
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLK4211EARGTT
QFN
RGT
16
250
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
QFN RGT 16
SPQ
Length (mm) Width (mm) Height (mm)
338.1 338.1 20.6
TLK4211EARGTT
250
Pack Materials-Page 2
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TLK4211EA 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| TLK1101E | TI | 11.3-Gbps Cable and PC Board Equalizer | 功能相似 |
|
| TLK6201EA | TI | 6.25-Gbps Cable and PC Board Equalizer | 功能相似 |
|
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| TLK4250GPV | TI | QUAD 1.0 to 2.5 Gbpss TRANSCEIVER | 获取价格 |
|
| TLK4250IGPV | TI | QUAD 1.0 to 2.5 Gbpss TRANSCEIVER | 获取价格 |
|
| TLK4250IZPV | TI | 暂无描述 | 获取价格 |
|
| TLK6002 | TI | Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver | 获取价格 |
|
| TLK6002ZEU | TI | Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver | 获取价格 |
|
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