TLV0834CDR [TI]
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL; 3伏的8位模拟数字转换器带串行控制
| 型号： | TLV0834CDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| 文件： | 总16页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
8-Bit Resolution
2.7-V to 3.6-V V
Remote Operation With Serial Data Link
Inputs and Outputs Are Compatible With
TTL and MOS
CC
Easy Microprocessor Interface or
Stand-Alone Operation
Conversion Time of 32 µs at
f
= 250 kHz
(CLK)
Operates Ratiometrically or With V
Reference
CC
Functionally Equivalent to the ADC0834
and ADC0838 at 3-V Supply Without the
Internal Zener Regulator Network
4- or 8-Channel Multiplexer Options With
Address Logic
Total Unadjusted Error . . . ±1 LSB
Input Range 0 V to V
With V
Reference
CC
CC
description
Thesedevicesare8-bitsuccessive-approximationanalog-to-digitalconverters, eachwithaninput-configurable
multichannel multiplexer and serial input/output. The serial input/output is configured to interface with standard
shift registers or microprocessors. Detailed information on interfacing with most popular microprocessors is
readily available from the factory.
The TLV0834 (4-channel) and TLV0838 (8-channel) multiplexer is software-configured for single-ended or
differential inputs as well as pseudodifferential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TLV0834C and TLV0838C are characterized for operation from 0°C to 70°C. The TLV0834I and TLV0838I
are characterized for operation from –40°C to 85°C.
TLV0834 . . . D OR N PACKAGE
(TOP VIEW)
TLV0834 . . . PW PACKAGE
(TOP VIEW)
TLV0838 . . . PW, DW, OR N PACKAGE
(TOP VIEW)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
V
CC
NC
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
NC
CS
V
CC
DI
NC
CS
CH0
CH1
CH2
V
DI
CLK
SARS
DO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CH0
CLK
SARS
DO
CH1
CH2
CH3
REF
ANLG GND
CH3
REF
DGTL GND
DGTL GND
NC
10 ANLG GND
NC
8
9
NC – No internal connection
DGTL GND
AVAILABLE OPTIONS
PACKAGE
SMALL
OUTLINE
(D)
SMALL
OUTLINE
(DW)
T
A
PLASTIC DIP
(N)
TSSOP
(PW)
0°C to 70°C
TLV0834CD
TLV0834ID
TLV0838CDW TLV0834CN TLV0838CN TLV0834CPW TLV0838CPW
TLV0838IDW TLV0834IN TLV0838IN TLV0834IPW TLV0838IPW
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Start
Flip-Flop
CS
CLK
CS
CLK
SARS
DI
R
D
(see Note A)
S
R
5-Bit Shift Register
CLK
START
SGL\DIF
ODD\EVEN
SELECT0 SELECT1
TLC0838
Only
SE
To Internal
Circuits
CLK
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
TLC0834
S
R
Analog
MUX
Time
Delay
TLC0838
EN
CS
CS
Comparator
Bits 0–7
CS
R
CS
R
CS
EN
R
CLK
CLK
REF
SAR
Ladder
and
Decoder
EOC
Logic
DO
9-Bit
Shift
Register
Bits 0–7
Bit 1
and
D
Latch
LSB
First
MSB
First
One
Shot
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
functional description
The TLV0834 and TLV0838 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–)
polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLV0838 can be used for a pseudodifferential input. In this mode, the voltage on the
common input is considered to be the negative differential input for all channel inputs. This voltage can be any
reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. Thecomparatoroutputindicateswhethertheanaloginputisgreaterthanorlessthantheresistive-ladder
output. Astheconversionproceeds, conversiondataissimultaneouslyoutputfromDO, withthemostsignificant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLV0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held
high on the TLV0838, the value of the LSB remains on the data line. When SE is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits
go tothehigh-impedancestate. Ifanotherconversionisdesired, CSmustmakeahigh-to-lowtransitionfollowed
by address information.
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
sequence of operation
TLV0834
1
2
3
4
5
6
7
10
11
12
13
14
15
18
19
20
21
CLK
CS
t
c
t
su
+Sign
Bit
SELECT
Bit 1
Start
Bit SGL ODD
Don’t Care
DI
DIF EVEN
1
Hi-Z
SARS
MUX Settling Time
MSB-First Data
LSB-First Data
Hi-Z
Hi-Z
MSB
7
LSB
MSB
7
DO
6
2
1
0
1
2
6
TLV0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
ODD/EVEN
CHANNEL NUMBER
CH0 CH1 CH2 CH3
SELECT BIT 1
SGL/DIF
+
–
–
+
L
L
L
L
L
L
H
H
L
H
L
+
–
–
+
H
+
H
H
H
H
L
L
H
H
L
H
L
+
+
+
H
H = high level, L = low level, – or + = terminal polarity for the selected input channel
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
sequence of operation (continued)
TLV0838
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLK
t
c
t
su
CS
MUX
Addressing
t
su
+
Sign
Bit
SEL SEL
Start
Bit
1
Bit
0
Bit SGL ODD
Don’t Care
DI
DIF EVEN
1
0
Hi-Z
Hi-Z
SARS
SE
LSB-First Data
MSB-First Data
Hi-Z
DO
Hi-Z
LSB
0
MSB
7
MSB
7
6
2
1
1
2
3
4
5
6
SE Used to Control LSB-First Data
SE
MUX Settling Time
MSB-First Data
LSB Held
LSB
LSB-First Data
MSB
7
DO
MSB
7
6
2
1
0
1
2
3
4
5
6
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
TLV0838 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SELECTED CHANNEL NUMBER
SELECT
0
1
2
3
COM
SGL/DIF
ODD/EVEN
1
L
0
L
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
L
L
L
L
+
–
+
–
L
H
L
+
–
+
–
+
L
L
H
H
L
+
–
+
–
+
L
L
H
L
+
–
+
–
+
L
H
H
H
H
L
+
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
–
–
–
–
–
–
–
–
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
+
L
H
L
+
H
H
+
H
+
H = high level, L = low level, – or + = polarity of external input
absolute maximum ratings over recommended operating free-air temperature range (unless
†
otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Input voltage range: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V
CC
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
(see clock frequency operating conditions)
2.7
2
3.3
3.6
High-level input voltage, V
IH
V
Low-level input voltage, V
0.8
250
600
60%
V
IL
Clock frequency, f
Clock frequency, f
V
V
= 2.7 V
= 3.3 V
10
10
kHz
kHz
(CLK)
CC
(CLK)
CC
Clock duty cycle (see Note 2)
Pulse duration, CS high, t
40%
220
350
90
ns
ns
ns
w
Setup time, CS low, SE low, or data valid before CLK↑, t
su
Hold time, data valid after CLK↑, t
h
C suffix
I suffix
0
70
85
Operating free-air temperature, T
°C
A
–40
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
electrical characteristics over recommended range of operating free-air temperature, V
= 3.3 V,
CC
f
= 250 kHz (unless otherwise noted)
(CLK)
digital section
C SUFFIX
I SUFFIX
†
PARAMETER
UNIT
TEST CONDITIONS
‡
TYP
‡
TYP
MIN
2.8
MAX
MIN
2.4
MAX
V
V
V
V
V
= 3 V,
= 3 V,
= 3 V,
I
I
I
= –360 µA
= –10 µA
= 1.6 mA
CC
CC
CC
OH
OH
OL
V
V
High-level output voltage
V
OH
2.9
2.8
Low-level output voltage
0.34
1
0.4
1
V
OL
I
I
I
I
High-level input current
= 3.6 V
= 0
0.005
–0.005
–15
0.005
–0.005
–15
16
µA
µA
mA
mA
IH
IH
IL
Low-level input current
–1
–1
IL
High-level output (source) current
Low-level output (sink) current
At V
OH
, DO = 0 V, T = 25°C
–6.5
8
–6.5
8
OH
OL
A
A t V , DO = V , T = 25°C
16
OL
CC
A
V
= 3.3 V,
T
A
= 25°C
= 25°C
0.01
3
0.01
–0.01
5
3
High-impedance-state output
current (DO or SARS)
O
O
I
µA
OZ
V
= 0,
T
A
–0.01
–3
–3
C
C
Input capacitance
Output capacitance
pF
pF
i
5
o
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
All typical values are at V = 3.3 V, T = 25°C.
CC
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
electrical characteristics over recommended range of operating free-air temperature, V
(CLK)
= 3.3 V,
CC
f
= 250 kHz (unless otherwise noted) (continued)
analog and converter section
†
‡
TYP
PARAMETER
Common-mode input voltage
TEST CONDITIONS
MIN
MAX
UNIT
–0.05
to
V
IC
See Note 3
V
V
CC
+0.05
On channel
Off channel
On channel
Off channel
V = 3.3 V
1
–1
–1
1
I
V = 0
I
I
Standby input current (see Note 4)
Input resistance to REF
µA
kΩ
I(stdby)
V = 0
I
V = 3.3 V
I
r
1.3
2.4
5.9
i(REF)
total device
‡
PARAMETER
MIN TYP
MAX
UNIT
I
Supply current
0.2
0.75
mA
CC
†
All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
NOTES: 3. When channel IN– is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are
two on-chip diodes that conduct forward current for analog input voltages one diode drop above V . Care must be taken during
CC
levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input
diodeto conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
testing at low V
CC
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum V
3.25 V for all variations of temperature and load.
of
CC
4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state condition.
operating characteristics, V
(unless otherwise noted)
= 3.3 V, f
= 250 kHz, t = t = 20 ns, T = 25°C
CC
(CLK) r f A
§
PARAMETER
Supply-voltage variation error
TEST CONDITIONS
MIN
TYP
MAX
±1/4
±1
UNIT
LSB
LSB
LSB
V
= 3 V to 3.6 V
±1/16
CC
Total unadjusted error (see Note 5)
Common-mode error
V
= 3.3 V,
T
= MIN to MAX
ref
Differential mode
A
±1/16
±1/4
500
200
80
MSB-first data
LSB-first data
Propagation delay time, output data after
CLK↓ (see Note 6)
t
pd
C
= 100pF
ns
ns
L
L
C
= 10 pF,
R
R
= 10 kΩ
= 2 kΩ
L
L
t
Output disable time, DO or SARS after CS↑
dis
c
C = 100 pF,
250
L
clock
periods
t
Conversion time (multiplexer-addressing time not included)
8
§
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
CLK
CS
50%
50%
GND
t
t
su
su
V
CC
0.4 V
2 V
GND
t
t
h
h
V
CC
2 V
DI
0.4 V
0.4 V
GND
Figure 1. Data-Input Timing
V
CC
50%
50%
CLK
DO
GND
t
pd
t
pd
V
CC
50%
50%
GND
t
su
V
CC
50%
SE
GND
Figure 2. Data-Output Timing
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Test
Point
S1
S2
R
L
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
t
t
r
r
V
V
CC
CC
90%
90%
10%
50%
CS
CS
50%
10%
GND
CC
GND
t
t
dis
dis
V
CC
V
S1 closed
S2 open
90%
S1 open
S2 closed
DO and SARS
DO and SARS
10%
GND
GND
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
LINEARITY ERROR
vs
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
1.5
16
14
V
= 3.3 V
= 250 kHz
= 25°C
CC
V
I(+)
= V
= 0 V
I(–)
f
T
(CLK)
A
1.25
12
1.0
10
8
0.75
6
4
0.5
0.25
2
0
0
0.01
0.1
1
10
0
1
2
3
4
V
ref –
Reference Voltage – V
V
ref
– Reference Voltage – V
Figure 4
Figure 5
LINEARITY ERROR
vs
LINEARITY ERROR
vs
CLOCK FREQUENCY
FREE-AIR TEMPERATURE
0.5
0.45
0.4
2.0
1.8
1.6
1.4
1.2
1
V
= 3.3 V
= 3.3 V
ref
V
= 3.3 V
= 250 kHz
ref
V
CC
f
(CLK)
85°C
0.35
0.3
0.8
0.6
0.4
25°C
–40°C
0.2
0
0.25
0
100
200 300 400 500 600 700 800
– Clock Frequency – kHz
–50
–25
0
25
50
75
100
f
T
A
– Free-Air Temperature – °C
(CLK)
Figure 6
Figure 7
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
TLV0831
SUPPLY CURRENT
vs
TLV0831
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
0.3
0.5
0.4
0.3
f
= 250 kHz
(CLK)
CS = High
V
T
A
= 3.3 V
CC
= 25°C
V
= 3.6 V
CC
V
V
= 3.3 V
= 3 V
CC
0.2
0.2
CC
0.1
0
0.1
–50
–25
T
0
25
50
75
100
0
100
f
200
300
400
500
– Free-Air Temperature – °C
– Clock Frequency – kHz
A
(CLK)
Figure 8
Figure 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
16.5
V
CC
= 3.3 V
16
15.5
15
I
OL (DO = 3.3 V)
–I
OH (DO = 0 V)
–I
OH (DO = 2.4 V)
14.5
I
OL (DO = 0.4 V)
14
–50
–25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
Figure 10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0834C, TLV0834I, TLV0838C, TLV0838I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS147B – SEPTEMBER 1996 – REVISED OCTOBER 2000
TYPICAL CHARACTERISTICS
1
0.5
0
V
= 3.3 V
= 25°C
= 250 kHz
= 3.3 V
ref
–0.5
–1
T
A
f
(CLK)
V
DD
0
32
64
96
128
160
192
224
256
Output Code
Figure 11. Differential Nonlinearity With Output Code
1
V
T
= 3.3 V
= 25°C
ref
A
f
= 250 kHz
0.5
0
(CLK)
= 3.3 V
V
DD
–0.5
–1
0
32
64
96
128
160
192
224
256
Output Code
Figure 12. Integral Nonlinearity With Output Code
1
V
T
= 3.3 V
ref
= 25°C
A
0.5
0
f
= 250 kHz
(CLK)
= 3.3 V
V
DD
–0.5
–1
0
32
64
96
128
160
192
224
256
Output Code
Figure 13. Total Unadjusted Error With Output Code
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
TLV0834CD
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
50
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLV0834CDR
TLV0834CN
SOIC
PDIP
D
N
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLV0834CPW
TLV0834CPWR
TLV0834ID
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
D
16
16
14
70
2000
50
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLV0834IDR
TLV0834IN
ACTIVE
ACTIVE
SOIC
PDIP
D
N
14
14
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLV0834IPW
TLV0834IPWR
TLV0838CDW
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
DW
16
16
20
90
2000
25
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TLV0838CDWR
TLV0838CN
ACTIVE
ACTIVE
SOIC
PDIP
DW
N
20
20
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NA-NA-NA
TLV0838CPW
TLV0838CPWR
TLV0838IDW
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
DW
20
20
20
70
2000
25
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TLV0838IDWR
TLV0838IN
ACTIVE
ACTIVE
SOIC
PDIP
DW
N
20
20
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NA-NA-NA
TLV0838IPW
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
70
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
TLV0838IPWR
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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amplifier.ti.com
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Copyright 2005, Texas Instruments Incorporated
相关型号：
TLV0834CNE4
IC 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14, Analog to Digital Converter
TI
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