TLV1543IDB_技术文档

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

DB, DW, FK, J, OR N PACKAGE

(TOP VIEW)

D

3.3-V Supply Operation

10-Bit-Resolution A/D Converter

11 Analog Input Channels

Three Built-In Self-Test Modes

Inherent Sample and Hold

Total Unadjusted Error . . . 1 LSB Max

On-Chip System Clock

A0

A1

V

CC

EOC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

A2

I/O CLOCK

ADDRESS

DATA OUT

A3

A4

A5

15 CS

End-of-Conversion (EOC) Output

Pin Compatible With TLC1543

CMOS Technology

14

13

12

11

A6

REF+

REF−

A10

A7

A8

GND

A9

description

FN PACKAGE

(TOP VIEW)

The TLV1543C, TLV1543I, and TLV1543M are

CMOS 10-bit, switched-capacitor, successive-

approximation, analog-to-digital converters.

These devices have three inputs and a 3-state

output [chip select (CS), input-output clock (I/O

CLOCK), address input (ADDRESS), and data

output (DATA OUT)] that provide a direct 4-wire

interface to the serial port of a host processor. The

devices allow high-speed data transfers from the

host.

3

2

1

20 19

18

I/O CLOCK

A3

A4

A5

A6

A7

4

5

6

7

8

ADDRESS

DATA OUT

CS

17

16

15

14

REF+

9 10 11 12 13

In addition to a high-speed A/D converter and

versatile control capability, these devices have an

on-chip 14-channel multiplexer that can select

any one of 11 analog inputs or any one of three

internal self-test voltages. The sample-and-hold

function is automatic. At the end of A/D conversion, the end-of-conversion (EOC) output goes high to indicate

that conversion is complete. The converter incorporated in the devices features differential high-impedance

reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and

supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air

temperature range.

The TLV1543C is characterized for operation from 0°C to 70°C. The TLV1543I is characterized for industrial

temperature range of −40°C to 85°C. The TLV1543M is characterized for operation over the full military

temperature range of −55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(DB)

SMALL

OUTLINE

(DW)

PLASTIC CHIP

CARRIER

(FN)

T

A

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

PLASTIC DIP

(N)

0°C to 70°C

−40°C to 85°C

−55°C to 125°C

TLV1543CDB

TLV1543IDB

—

TLV1543CDW

—

TLV1543CN

TLV1543CFN

—

TLV1543MFK

TLV1543MJ

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2000 − 2004, Texas Instruments Incorporated

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

functional block diagram

REF+

14

REF−

13

10-Bit

Analog-to-Digital

Converter

1

A0

A1

Sample and

Hold

2

3

4

5

6

7

8

9

(switched capacitors)

A2

A3

A4

A5

A6

A7

A8

A9

10

14-Channel

Analog

Multiplexer

10

Output

Data

Register

10-to-1 Data

Selector and

Driver

16

DATA

OUT

11

12

4

Input Address

Register

A10

4

3

System Clock,

Control Logic,

and I/O

Self-Test

Reference

19

EOC

Counters

17

ADDRESS

18

15

I/O CLOCK

CS

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

A0−A10

C = 60 pF MAX

i

(equivalent input

capacitance)

5 MΩ TYP

2

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

ADDRESS

17

I

Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted

next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O

CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the

remainder of the current conversion period.

A0−A10

CS

1−9, 11,

12

I

Analog signal. The 11 analog inputs are applied to A0−A10 and are internally multiplexed. The driving source

impedance should be less than or equal to 1 kΩ.

15

Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT,

ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges

of the internal system clock.

DATA OUT

16

O

The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS

is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance

state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The

next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next most significant

bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O

CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial

interface data transfers of more than ten clocks produce zeroes as the unused LSBs.

EOC

19

10

18

O

I

End of conversion. EOC goes from a high- to a low- logic level on the trailing edge of the tenth I/O CLOCK

and remains low until the conversion is complete and data are ready for transfer.

GND

The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are

with respect to GND.

I/O CLOCK

I

Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four functions:

1) It clocks the four input address bits into the address register on the first four rising edges of I/O

CLOCK with the multiplex address available after the fourth rising edge.

2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins

charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.

3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

REF+

REF−

14

I

The upper reference voltage value (nominally V ) is applied to REF+. The maximum input voltage range

CC

is determined by the difference between the voltage applied to REF+ and the voltage applied to the REF−

terminal.

13

20

I

The lower reference voltage value (nominally ground) is applied to REF−.

Positive supply voltage

V

CC

detailed description

With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT

is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins

with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.

The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK.

During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O

CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks

load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next

six clocks providing the control timing for sampling the analog input.

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

detailed description (continued)

There are six basic serial interface timing modes that can be used with the device. These modes are determined

by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with

a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer

and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between

conversion cycles, (4) a fast mode with a 16-bit transfer and CS active (low) continuously, (5) a slow mode with

an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode with a

16-clock transfer and CS active (low) continuously.

The MSB of the previous conversion appears on DATA OUT on the falling edge of CS in mode 1, mode 3, and

mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6.

The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are

transmitted to the host through DATA OUT. The number of serial clock pulses used also depends on the mode

of operation, but a minimum of ten clock pulses is required for conversion to begin. On the 10th clock falling

edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result

can be read by the host. On the 10th clock falling edge, the internal logic takes DATA OUT low to ensure that

the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that

can be used, and the timing edge on which the MSB of the previous conversion appears at the output.

Table 1. Mode Operation

NO. OF

I/O CLOCKS

TIMING

DIAGRAM

†

MODES

MSB AT DATA OUT

CS

Mode 1 High between conversion cycles

Mode 2 Low continuously

10

CS falling edge

EOC rising edge

CS falling edge

EOC rising edge

CS falling edge

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Fast Modes

‡

Mode 3 High between conversion cycles

Mode 4 Low continuously

11 to 16

‡

16

11 to 16

Mode 5 High between conversion cycles

Mode 6 Low continuously

Slow Modes

‡

16

16th clock falling edge

†

‡

These edges also initiate serial-interface communication.

No more than 16 clocks should be used.

fast modes

The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is

completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not

begin until the falling edge of the 10th I/O CLOCK.

mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The

falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge

of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling

edges of the internal system clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After

the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then

begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous

conversion to appear immediately on this output.

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of

EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the

previous conversion to appear immediately on this output.

slow modes

In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow

mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must

occur before the conversion period is complete; otherwise, the device loses synchronization with the host serial

interface, and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must

occur within 9.5 µs after the tenth I/O clock falling edge.

mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of

the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the

MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next

16-clock transfer initiated by the serial interface.

address bits

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal

(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address

selects one of 14 inputs (11 analog inputs or 3 internal test inputs).

analog inputs and test modes

The 11 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the

input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce

input-to-input noise injection resulting from channel switching.

Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six

I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are

applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

Table 2. Analog-Channel-Select Address

VALUE SHIFTED INTO

ANALOG INPUT

ADDRESS INPUT

SELECTED

BINARY

0000

0001

0010

0011

0100

0101

0110

0111

HEX

0

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

1

2

3

4

5

6

7

1000

1001

1010

8

9

A

Table 3. Test-Mode-Select Address

VALUE SHIFTED INTO

ADDRESS INPUT

INTERNAL SELF-TEST

VOLTAGE SELECTED

‡

OUTPUT RESULT (HEX)

†

BINARY

HEX

V

– V

ref)

ref–

1011

B

200

2

V

1100

1101

C

D

000

3FF

ref−

V

ref+

†

‡

V

is the voltage applied to the REF+ input, and V

is the voltage applied to the REF−

ref+

input.

ref−

The output results shown are the ideal values and vary with the reference stability and with

internal offsets.

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the S switch and all S switches simultaneously.

C

T

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all S and S switches are opened and the threshold detector

T

C

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF−)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks

at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF−. If the voltage at the summing

node is greater than the trip point of the threshold detector (approximately one-half the V

voltage), a bit 0 is

CC

placed in the output register and the 512-weight capacitor is switched to REF−. If the voltage at the summing

node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight

capacitor remains connected to REF+ through the remainder of the successive-approximation process. The

process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all

bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

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ꢓ

ꢃꢃ

ꢏ

ꢐ

ꢏ

ꢁ

ꢑ

ꢒ

ꢉ

ꢐ

ꢙ

ꢚ

ꢀ

ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

converter and analog input (continued)

S

C

Threshold

Detector

To Output

Latches

512

Node 512

256

128

16

8

4

2

1

REF+

REF−

T

REF−

T

S

T

V

I

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode.

A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device

returns to the initial state (the contents of the output data register remain at the previous conversion result).

Exercise care to prevent CS from being taken low close to completion of conversion because the output data

can be corrupted.

reference voltage inputs

There are two reference inputs used with these devices: REF+ and REF−. These voltage values establish the

upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. The values

of REF+, REF−, and the analog input should not exceed the positive supply or be lower than GND consistent

with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal

to or higher than REF+ and at zero when the input signal is equal to or lower than REF−.

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1): TLV1543C/TLV1543I . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

TLV1543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V

CC

Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

+ 0.3 V

+ 0.1 V

I

CC

Output voltage range, V

Positive reference voltage, V

Negative reference voltage, V

Peak input current (any input), I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

O

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

ref+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.1 V

ref−

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

(p-p)

Peak total input current (all inputs), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

p

Operating free-air temperature range, T : TLV1543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

TLV1543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

TLV1543M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF− and GND wired together (unless otherwise noted).

7

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ꢗꢉ ꢀ ꢘ ꢖꢔ ꢕꢉ ꢏ ꢁ ꢇꢑ ꢐꢀ ꢕꢑ ꢁ ꢏꢐ ꢓ ꢃ ꢃ ꢏꢐ ꢏꢁ ꢑ ꢒ ꢉꢐ ꢙꢚꢀ ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

recommended operating conditions

MIN NOM

MAX

5.5

UNIT

V

TLV1543C/TLV1543I

TLV1543M

3

3.3

Supply voltage, V

CC

3.6

V

Positive reference voltage, V

ref+

(see Note 2)

− V (see Note 2)

V

CC

0

Negative reference voltage, V

ref−

V

Differential reference voltage, V

ref+

2.5

0

V +0.2

CC

V

ref−

CC

Analog input voltage (see Note 2)

V

CC

V

TLV1543C/TLV1543I

TLV1543M

V

= 3 V to 5.5 V

= 3 V to 3.6 V

= 3 V to 5.5 V

= 3 V to 3.6 V

2

V

CC

High-level control input voltage, V

IH

V

2

V

TLV1543C/TLV1543I

TLV1543M

0.6

0.8

V

Low-level control input voltage, V

IL

V

Setup time, address bits at data input before I/O CLOCK↑, t

su(A)

(see Figure 4)

100

0

ns

µs

Hold time, address bits after I/O CLOCK↑, t

(see Figure 4)

h(A)

Hold time, CS low after last I/O CLOCK↓, t

0

h(CS)

Setup time, CS low before clocking in first address bit, t

su(CS)

(see Note 3)

1.425

0

TLV1543C/TLV1543I

TLV1543M

1.1

2.1

Clock frequency at I/O CLOCK (see Note 4)

MHz

0

Pulse duration, I/O CLOCK high, t

190

ns

µs

w(H_I/O)

Pulse duration, I/O CLOCK low, t

w(L_I/O)

Transition time, I/O CLOCK, t

t(I/O)

Transition time, ADDRESS and CS, t

(see Note 5)

t(CS)

1

10

70

TLV1543C/TLV1543I

TLV1543M

0

Operating free-air temperature, T

°C

A

−55

125

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF− convert as all zeros (0000000000).

3. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

setup time has elapsed.

4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O clock rising edge (≥ 2 V) must occur within

9.5 µs.

5. This is the time required for the clock input signal to fall from V min to V max or to rise from V max to V min. In the vicinity of

IH

IL

IH

normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

8

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ꢆ ꢋꢆ ꢌꢂ ꢃ ꢍ ꢌꢎꢉ ꢀ ꢏꢐꢏ ꢁꢑ ꢒ ꢌꢀꢑ ꢌꢓꢉꢒ ꢉ ꢀꢏꢁ ꢇꢑ ꢐ ꢂꢔ ꢕꢀ ꢔꢕ ꢖ

ꢗ ꢉꢀ ꢘ ꢖꢔ ꢕꢉꢏ ꢁ ꢇꢑ ꢐꢀ ꢕꢑ ꢁ ꢏꢐꢓ ꢃꢃ ꢏꢐꢏ ꢁꢑ ꢒ ꢉ ꢐꢙ ꢚ ꢀꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

electrical characteristics over recommended operating free-air temperature range,

V

= V

= 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I

= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M (unless otherwise

CC

ref+

noted)

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= 3 V,

I

= −1.6 mA

= 20 µA

2.4

CC

OH

OL

TLV1543C/TLV1543I

TLV1543M

= 3 V to 5.5 V,

= 3 V,

V

−0.1

V

CC

2.4

−0.1

V

OH

High-level output voltage

Low-level output voltage

= −1.6 mA

= 20 µA

V

= 3 V to 3.6 V,

= 3 V,

V

CC

= 1.6 mA

= 20 µA

0.4

0.1

V

TLV1543C/TLV1543I

TLV1543M

= 3 V to 5.5 V,

= 3 V,

V

OL

= 1.6 mA

= 20 µA

0.4

V

= 3 V to 3.6 V,

0.1

V

= V

CC

,

CS at V

10

O

CC

I

Off-state (high-impedance-state) output current

µA

OZ

= 0,

CS at V

−10

2.5

I

High-level input current

Low-level input current

Operating supply current

V = V

CC

0.005

−0.005

0.8

µA

IH

I

V = 0

I

−2.5

2.5

IL

CS at 0 V

mA

CC

Selected channel at V

Unselected channel at 0 V

,

CC

1

Selected channel leakage current

µA

Selected channel at 0 V,

Unselected channel at V

CC

−1

Maximum static analog reference current into REF+

V

ref+

= V

CC

,

V

ref−

= GND

10

60

µA

TLV1543C/TLV1543I

TLV1543M

7

5

Input capacitance, Analog

inputs

pF

C

i

TLV1543C/TLV1543I

TLV1543M

Input capacitance, Control

inputs

pF

†

All typical values are at V

CC

= 5 V, T = 25°C.

A

9

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ꢆꢋ ꢆꢌꢂ ꢃ ꢍꢌ ꢎꢉ ꢀ ꢏ ꢐ ꢏꢁ ꢑꢒ ꢌꢀꢑ ꢌꢓꢉ ꢒ ꢉꢀꢏꢁ ꢇꢑ ꢐꢂꢔ ꢕꢀ ꢔꢕꢖ

ꢗꢉ ꢀ ꢘ ꢖꢔ ꢕꢉ ꢏ ꢁ ꢇꢑ ꢐꢀ ꢕꢑ ꢁ ꢏꢐ ꢓ ꢃ ꢃ ꢏꢐ ꢏꢁ ꢑ ꢒ ꢉꢐ ꢙꢚꢀ ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

operating characteristics over recommended operating free-air temperature range,

V

= V

= 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I

= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M

CC

ref+

†

PARAMETER

Linearity error (see Note 6)

Zero error (see Note 7)

TEST CONDITIONS

MIN TYP

MAX

UNIT

LSB

1

Full-scale error (see Note 7)

Total unadjusted error (see Note 8)

ADDRESS = 1011

ADDRESS = 1100

ADDRESS = 1101

See Figures 9−14

512

0

Self-test output code (see Table 3 and Note 9)

Conversion time

1023

t

21

µs

c(1)

21

See Figures 9−14

and Note 10

+10 I/O

CLOCK

periods

Total cycle time (access, sample, and conversion)

c(2)

I/O

CLOCK

periods

See Figures 9−14

and Note 10

t

Channel acquisition time (sample)

6

(acq)

t

Valid time, DATA OUT remains valid after I/O CLOCK↓

Delay time, I/O CLOCK↓ to DATA OUT valid

Delay time, tenth I/O CLOCK↓ to EOC↓

Delay time, EOC↑ to DATA OUT (MSB)

Enable time, CS↓ to DATA OUT (MSB driven)

Disable time, CS↑ to DATA OUT (high impedance)

Rise time, EOC

See Figure 6

See Figure 7

See Figure 8

See Figure 3

See Figure 8

See Figure 7

See Figure 6

10

ns

µs

ns

v

240

100

1.3

d(I/O-DATA)

d(I/O-EOC)

70

d(EOC-DATA)

, t

PZH PZL

, t

150

300

PHZ PLZ

r(EOC)

f(EOC)

r(bus)

f(bus)

Fall time, EOC

Rise time, data bus

Fall time, data bus

Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion

(see Note 11)

t

9

µs

d(I/O-CS)

†

All typical values are at T = 25°C.

A

NOTES: 6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the

difference between 1111111111 and the converted output for full-scale input voltage.

8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

9. Both the input address and the output codes are expressed in positive logic.

10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).

11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock

(1.425 µs) after the transition.

10

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ꢆ ꢋꢆ ꢌꢂ ꢃ ꢍ ꢌꢎꢉ ꢀ ꢏꢐꢏ ꢁꢑ ꢒ ꢌꢀꢑ ꢌꢓꢉꢒ ꢉ ꢀꢏꢁ ꢇꢑ ꢐ ꢂꢔ ꢕꢀ ꢔꢕ ꢖ

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

Test Point

V

CC

Test Point

V

CC

R

= 2.18 kΩ

R

= 2.18 kΩ

L

EOC

DATA OUT

12 kΩ

C

= 50 pF

C = 100 pF

L

Figure 2. Load Circuits

Address

Valid

2 V

CS

ADDRESS

V

IL

V

IL

t

, t

PZH PZL

t

, t

h(A)

PHZ PLZ

t

su(A)

2.4 V

0.4 V

90%

10%

I/O CLOCK

DATA

OUT

V

IL

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

Figure 4. ADDRESS Setup Voltage Waveforms

2 V

CS

V

IL

t

su(CS)

t

h(CS)

I/O CLOCK

First

Clock

Last

Clock

V

IL

V

IL

Figure 5. CS and I/O CLOCK Voltage Waveforms

11

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ꢆꢋ ꢆꢌꢂ ꢃ ꢍꢌ ꢎꢉ ꢀ ꢏ ꢐ ꢏꢁ ꢑꢒ ꢌꢀꢑ ꢌꢓꢉ ꢒ ꢉꢀꢏꢁ ꢇꢑ ꢐꢂꢔ ꢕꢀ ꢔꢕꢖ

ꢗꢉ ꢀ ꢘ ꢖꢔ ꢕꢉ ꢏ ꢁ ꢇꢑ ꢐꢀ ꢕꢑ ꢁ ꢏꢐ ꢓ ꢃ ꢃ ꢏꢐ ꢏꢁ ꢑ ꢒ ꢉꢐ ꢙꢚꢀ ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

t

t(I/O)

t

t(I/O)

2 V

I/O CLOCK

V

IL

V

IL

V

IL

I/O CLOCK Period

t

d(I/O-DATA)

t

v

2.4 V

0.4 V

2.4 V

0.4 V

DATA OUT

t

, t

r(bus) f(bus)

Figure 6. DATA OUT and I/O CLOCK Voltage Waveforms

I/O CLOCK

10th

V

IL

Clock

t

d(I/O-EOC)

2.4 V

EOC

0.4 V

t

f(EOC)

Figure 7. I/O CLOCK and EOC Voltage Waveforms

t

r(EOC)

EOC

2.4 V

0.4 V

t

d(EOC-DATA)

2.4 V

0.4 V

DATA OUT

Valid MSB

Figure 8. EOC and DATA OUT Voltage Waveforms

12

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇꢈ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢉꢈ ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢊ

ꢆ ꢋꢆ ꢌꢂ ꢃ ꢍ ꢌꢎꢉ ꢀ ꢏꢐꢏ ꢁꢑ ꢒ ꢌꢀꢑ ꢌꢓꢉꢒ ꢉ ꢀꢏꢁ ꢇꢑ ꢐ ꢂꢔ ꢕꢀ ꢔꢕ ꢖ

ꢗ

ꢉ

ꢀ

ꢘ

ꢖ

ꢔ

ꢕ

ꢉ

ꢏ

ꢁ

ꢇ

ꢑ

ꢐ

ꢀ

ꢕ

ꢑ

ꢁ

ꢏ

ꢐ

ꢓ

ꢃꢃ

ꢏ

ꢐ

ꢏ

ꢁ

ꢑ

ꢒ

ꢉ

ꢐ

ꢙ

ꢚ

ꢀ

ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

CS

(see Note A)

I/O

CLOCK

1

2

3

4

5

6

7

8

9

10

1

Access Cycle B

Sample Cycle B

Hi-Z State

DATA

OUT

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

B9

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

B3

MSB

B2

B1

B0

LSB

C3

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

time has elapsed.

Figure 9. Timing for 10-Clock Transfer Using CS

Must be High on Power Up

CS

(see Note A)

I/O

CLOCK

1

2

3

4

5

6

7

8

9

10

1

Access Cycle B

Sample Cycle B

DATA

OUT

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

B9

Low Level

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

B3

MSB

B2

B1

B0

LSB

C3

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

time has elapsed.

Figure 10. Timing for 10-Clock Transfer Not Using CS

13

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ꢆꢋ ꢆꢌꢂ ꢃ ꢍꢌ ꢎꢉ ꢀ ꢏ ꢐ ꢏꢁ ꢑꢒ ꢌꢀꢑ ꢌꢓꢉ ꢒ ꢉꢀꢏꢁ ꢇꢑ ꢐꢂꢔ ꢕꢀ ꢔꢕꢖ

ꢗ

ꢉ

ꢀ

ꢘ

ꢖ

ꢔ

ꢕꢉ

ꢏ

ꢁ

ꢇ

ꢑ

ꢐ

ꢀ

ꢕ

ꢑ

ꢁ

ꢏ

ꢐ

ꢓ

ꢃ ꢃ

ꢏ

ꢐ

ꢏ

ꢁ

ꢑ

ꢒ

ꢉ

ꢐ

ꢙ

ꢚ

ꢀ

ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

See Note B

CS

(see Note A)

I/O

CLOCK

1

2

3

4

5

6

7

8

9

10

11

16

1

Access Cycle B

Sample Cycle B

Low

Level

Hi-Z

DATA

OUT

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

B9

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

B3

MSB

B2

B1

B0

LSB

C3

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

setup time has elapsed.

B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock.

Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)

Must be High on Power Up

CS

(see Note A)

I/O

CLOCK

1

2

3

4

5

6

7

8

9

10

14

15

16

1

Access Cycle B

Sample Cycle B

See Note B

DATA

OUT

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

B9

Low Level

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

B3

MSB

B2

B1

B0

LSB

C3

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.

Initialize

B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock.

Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)

14

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ꢆ ꢋꢆ ꢌꢂ ꢃ ꢍ ꢌꢎꢉ ꢀ ꢏꢐꢏ ꢁꢑ ꢒ ꢌꢀꢑ ꢌꢓꢉꢒ ꢉ ꢀꢏꢁ ꢇꢑ ꢐ ꢂꢔ ꢕꢀ ꢔꢕ ꢖ

ꢗ

ꢉ

ꢀ

ꢘ

ꢖ

ꢔ

ꢕ

ꢉ

ꢏ

ꢁ

ꢇ

ꢑ

ꢐ

ꢀ

ꢕ

ꢑ

ꢁ

ꢏ

ꢐ

ꢓ

ꢃꢃ

ꢏ

ꢐ

ꢏ

ꢁ

ꢑ

ꢒ

ꢉ

ꢐ

ꢙ

ꢚ

ꢀ

ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

CS

(see Note A)

I/O

CLOCK

1

2

3

4

5

6

7

8

9

10

11

16

1

Access Cycle B

Sample Cycle B

See Note B

Hi-Z State

DATA

OUT

Low

Level

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

B9

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

B3

MSB

B2

B1

B0

LSB

C3

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum

chip CS setup time has elapsed.

B. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial

interface synchronization.

Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)

Must be High on Power Up

CS

(see Note A)

I/O

CLOCK

1

2

3

4

5

6

7

8

9

10

14

15

16

1

Access Cycle B

Sample Cycle B

See Note A

Low Level

See Note B

DATA

OUT

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

B9

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

B3

MSB

B2

B1

B0

LSB

C3

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

NOTES: A. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial

interface synchronization.

B. The I/O CLOCK sequence is exactly 16 clock pulses long.

Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)

15

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂꢃ ꢄꢅ ꢆ ꢉ ꢈ ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢊ

ꢆꢋ ꢆꢌꢂ ꢃ ꢍꢌ ꢎꢉ ꢀ ꢏ ꢐ ꢏꢁ ꢑꢒ ꢌꢀꢑ ꢌꢓꢉ ꢒ ꢉꢀꢏꢁ ꢇꢑ ꢐꢂꢔ ꢕꢀ ꢔꢕꢖ

ꢗꢉ ꢀ ꢘ ꢖꢔ ꢕꢉ ꢏ ꢁ ꢇꢑ ꢐꢀ ꢕꢑ ꢁ ꢏꢐ ꢓ ꢃ ꢃ ꢏꢐ ꢏꢁ ꢑ ꢒ ꢉꢐ ꢙꢚꢀ ꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

APPLICATION INFORMATION

1023

1022

1021

1111111111

1111111110

1111111101

See Notes A and B

V

FS

V

FT

= V − 1/2 LSB

FS

513

512

1000000001

1000000000

V

ZT

= V + 1/2 LSB

ZS

511

0111111111

V

ZS

2

1

0

0000000010

0000000001

0000000000

0

0.0048 0.0096

2.4528 2.4576 2.4624

V − Analog Input Voltage − V

4.9056

4.9104 4.9152

I

NOTES: A. This curve is based on the assumption that V

and V

have been adjusted so that the voltage at the transition from digital

0 to 1 (V ) is 0.0024 V and the transition to full scale (V ) is 4.908 V. 1 LSB = 4.8 mV.

ref+

ref−

FT

ZT

B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V

)

ZS

FS

is the step whose nominal midstep value equals zero.

Figure 15. Ideal Conversion Characteristics

TLV1543

15

18

17

1

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

CS

2

I/O CLOCK

ADDRESS

3

Control

Circuit

4

Processor

5

16

19

DATA OUT

EOC

6

Analog

Inputs

7

8

9

14

13

3-V DC Regulated

REF+

REF−

11

12

GND

10

To Source

Ground

Figure 16. Serial Interface

16

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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇꢈ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢉꢈ ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢊ

ꢆ ꢋꢆ ꢌꢂ ꢃ ꢍ ꢌꢎꢉ ꢀ ꢏꢐꢏ ꢁꢑ ꢒ ꢌꢀꢑ ꢌꢓꢉꢒ ꢉ ꢀꢏꢁ ꢇꢑ ꢐ ꢂꢔ ꢕꢀ ꢔꢕ ꢖ

ꢗ ꢉꢀ ꢘ ꢖꢔ ꢕꢉꢏ ꢁ ꢇꢑ ꢐꢀ ꢕꢑ ꢁ ꢏꢐꢓ ꢃꢃ ꢏꢐꢏ ꢁꢑ ꢒ ꢉ ꢐꢙ ꢚ ꢀꢖ

SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to V

within 1/2 LSB can be derived as follows:

S

The capacitance charging voltage is given by

−t /R C

c

t i

(1)

V = V 1−e

(

)

C

S

Where:

R = R + r

i

t

s

The final voltage to 1/2 LSB is given by

V (1/2 LSB) = V − (V /2048)

(2)

C

S

Equating equation 1 to equation 2 and solving for time t gives

c

−t /R C

c

t i

V −(V /2048) = V 1−e

(3)

(4)

(

)

S

and

t (1/2 LSB) = R × C × ln(2048)

c

t

i

Therefore, with the values given the time for the analog input signal to settle is

t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(2048)

(5)

c

s

This time must be less than the converter sample time shown in the timing diagrams.

†

Driving Source

TLV1543

R

r

i

s

V

I

V

S

V

C

1 kΩ MAX

C

i

60 pF MAX

V

= Input Voltage at A0−A10

= External Driving Source Voltage

I

S

s

R = Source Resistance

r

= Input Resistance

i

C = Input Capacitance

i

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the

resolution of the converter.

• R must be real at the input frequency.

s

Figure 17. Equivalent Input Circuit Including the Driving Source

17

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PACKAGE OPTION ADDENDUM

www.ti.com

11-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

Drawing

5962-9689401Q2A

5962-9689401QRA

TLV1543CDB

OBSOLETE

ACTIVE

FK

20

None

Call TI

J

SSOP

SOIC

DB

70

CU NIPDAU Level-1-220C-UNLIM

Call TI Call TI

TLV1543CDBLE

TLV1543CDBR

TLV1543CDW

OBSOLETE

ACTIVE

DB

2000

25

CU NIPDAU Level-1-220C-UNLIM

ACTIVE

DW

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1YEAR/

Level-1-220C-UNLIM

TLV1543CDWR

ACTIVE

SOIC

DW

20

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1YEAR/

Level-1-220C-UNLIM

TLV1543CFN

TLV1543CFNR

TLV1543CN

ACTIVE

PLCC

PDIP

FN

N

20

46

1000

20

None

Call TI

Pb-Free

(RoHS)

CU NIPDAU Level-NA-NA-NA

TLV1543CNE4

TLV1543IDB

ACTIVE

PDIP

N

20

70

None

Call TI Call TI

SSOP

DB

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

TLV1543IDBLE

TLV1543IDBR

OBSOLETE

ACTIVE

SSOP

DB

20

None

Call TI

2000

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1YEAR/

Level-1-220C-UNLIM

TLV1543MFKB

TLV1543MJ

OBSOLETE

LCCC

CDIP

FK

J

20

None

Call TI

TLV1543MJB

J

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Mar-2005

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for

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Digital Control

Military

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www.ti.com/digitalcontrol

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Logic

interface.ti.com

logic.ti.com

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power.ti.com

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Security

www.ti.com/opticalnetwork

www.ti.com/security

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www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265


型号：	TLV1543IDB
厂家：	TEXAS INSTRUMENTS
描述：	3.3V 10 BIT ANALOG TO DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS 3.3V 10位模拟带串行控制和11个模拟输入数字转换器转换器模数转换器光电二极管输入元件
文件：	总26页 (文件大小：607K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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