TLV1544C_08 [TI]
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS; 低电压10位模拟数字转换器与串行控制和4/8模拟输入
| 型号： | TLV1544C_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS |
| 文件： | 总41页 (文件大小：774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
D OR PW PACKAGE
(TOP VIEW)
Conversion Time ≤ 10 µs
10-Bit-Resolution ADC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Programmable Power-Down
Mode . . . 1 µA
DATA OUT
DATA IN
I/O CLK
EOC
CS
REF+
REF–
FS
INV CLK
GND
CSTART
A3
Wide Range Single-Supply Operation of
2.7 V dc to 5.5 V dc
V
CC
A0
Analog Input Range of 0 V to V
CC
Built-in Analog Multiplexer with 8 Analog
Input Channels
A1
A2
TMS320 DSP and Microprocessor SPI and
QSPI Compatible Serial Interfaces
DB OR J PACKAGE
(TOP VIEW)
End-of-Conversion (EOC) Flag
Inherent Sample-and-Hold Function
Built-In Self-Test Modes
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
EOC
I/O CLK
DATA IN
DATA OUT
CS
REF+
REF–
FS
INV CLK
Programmable Power and Conversion Rate
Asynchronous Start of Conversion for
Extended Sampling
Hardware I/O Clock Phase Adjust Input
CSTART
GND
description
The TLV1544 and TLV1548 are CMOS 10-bit
switched-capacitor successive-approximation (SAR)
analog-to-digital (A/D) converters. Each device
has a chip select (CS), input-output clock (I/O
CLK), data input (DATA IN) and serial data output
(DATA OUT) that provide a direct 4-wire
synchronous serial peripheral interface (SPI ,
QSPI ) port of a host microprocessor. When
interfacing with a TMS320 DSP, an additional
frame sync signal (FS) indicates the start of a
serial data frame. The devices allow high-speed
data transfers from the host. The INV CLK input
provides further timing flexibility for the serial
interface.
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
A3
I/O CLK
18
4
5
6
7
8
A4
A5
A6
A7
DATA IN
DATA OUT
CS
17
16
15
14
REF+
9
10 11 12 13
In addition to a high-speed converter andversatile
control capability, the device has an on-chip
11-channel multiplexer that can select any one of
eight analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic
except for the extended sampling cycle, where the sampling cycle is started by the falling edge of asynchronous
CSTART. At the end of the A/D conversion, the end-of-conversion (EOC) output goes high to indicate that the
conversion is complete. The TLV1544 and TLV1548 are designed to operate with a wide range of supply
voltages with very low power consumption. The power saving feature is further enhanced with a
software-programmed power-down mode and conversion rate. The converter incorporated in the device
features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error
conversion over the full operating temperature range.
SPI and QSPI are registered trademarks of Motorola, Inc.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
description (continued)
The TLV1544 has four analog input channels while the TLV1548 has eight analog input channels. The
TLV1544C and TLV1548C are characterized for operation from 0°C to 70°C. The TLV1544I and TLV1548I are
characterized for operation over the full industrial temperature range of –40°C to 85°C. The TLV1548M is
characterized for operation over the full military temperature range of –55°C to 125°C.
functional block diagram
Sample
and
Hold Function
10-Bit ADC
(Switch Capacitors)
CLOCK
1–8
A0–A7
Output Data Register
14
REF+
Analog
MUX
10-to-1
Data Selector
16
DATA OUT
Self-Test
Reference
13
17
REF–
Input
Data
Register
19
12
15
9
EOC
FS
DATA IN
Control
Logic
and
I/O
Counters
CS
CSTART
INV CLK
I/O CLK
11
18
Terminals shown are for the DB package.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
(DB)
(D)
(J)
(FK)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
TLV1548CDB
TLV1548IDB
TLV1544CD
TLV1544ID
TLV1544CPW
TLV1544IPW
TLV1548MJ
TLV1548MFK
DISSIPATION RATING TABLE
†
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
DB
D
PW
J
785 mW
799 mW
604 mW
1894 mW
1375 mW
8.7 mW/°C
8.9 mW/°C
6.7 mW/°C
15.1 mW/°C
11.0 mW/°C
393 mW
399 mW
302 mW
1212 mW
880 mW
261 mW
266 mW
201 mW
985 mW
715 mW
—
—
—
379 mW
275 mW
FK
†
This is the inverse of the traditional junction-to-ambient thermal resistance (RΘ ). RΘ values are derived from Texas Instruments
characterization data. Thermal resistance is not production tested and values are given for informational purposes only.
JA
JA
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
Terminal Functions
TERMINAL
I/O
DESCRIPTION
†
‡
NO.
NAME
NO.
A0–A3
6–9
–
1–4
5–8
I
Analog inputs. The analog inputs are internally multiplexed. (For a source impedance greater than
1 kΩ, the asynchronous start should be used to increase the sampling time.)
A4–A7
CS
16
15
I
I
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA IN,
DATA OUT, and I/O CLK within the maximum setup time. A low-to-high transition disables DATA IN, DATA
OUT, and I/O CLK within the setup time.
CSTART
DATA IN
10
9
Sampling/conversion start control. CSTART controls the start of the sampling of an analog input from a
selected multiplex channel. A high-to-low transition starts the sampling of the analog input signal. A
low-to-high transition puts the sample-and-hold function in hold mode and starts the conversion. CSTART
is independent from I/O CLK and works when CS is high. The low CSTART duration controls the duration
of the sampling cycle for the switched capacitor array. CSTART is tied to V
CC
if not used.
2
17
I
Serialdata input. The 4-bit serial data selects the desired analog input and test voltage to be converted next
in a normal cycle. These bits can also set the conversion rate and enable the power-down mode.
When operating in the microprocessor mode, the input data is presented MSB first and is shifted in on the
first four rising (INV CLK = V ) or falling (INV CLK = GND) edges of I/O CLK (after CS↓).
CC
When operating in the DSP mode, the input data is presented MSB first and is shifted in on the first four
falling (INV CLK = V ) or rising (INV CLK = GND) edges of I/O CLK (after FS↓).
CC
Afterthefourinputdatabitshavebeenreadintotheinputdataregister,DATAINisignoredfortheremainder
of the current conversion period.
DATA OUT
EOC
1
4
16
19
O
Three-state serial output of the A/D conversion result. DATA OUT is in the high-impedance state when CS
ishighandactivewhenCSisloworafterFS↓ (inDSPmode). WithavalidCSsignal, DATAOUTisremoved
from the high-impedance state and is driven to the logic level corresponding to the MSB or LSB value of
the previous conversion result. DATA OUT changes on the falling (microprocessor mode) or rising (DSP
mode) edge of I/O CLK.
O
I
End of conversion. EOC goes from a high to a low logic level on the tenth rising (microprocessor mode)
or tenth falling (DSP mode) edge of I/O CLK and remains low until the conversion is complete and data is
ready for transfer. EOC can also indicate that the converter is busy.
FS
13
11
12
12
10
11
DSP frame synchronization input. FS indicates the start of a serial data frame into or out of the device. FS
is tied to V
when interfacing the device with a microprocessor.
CC
GND
Ground return for internal circuitry. All voltage measurements are with respect to GND, unless otherwise
noted.
INV CLK
I
Inverted clock input. INV CLK is tied to GND when an inverted I/O CLK is used as the source of the input
clock. This affects both microprocessor and DSP interfaces. INV CLK is tied to V
inverted. INV CLK can also invoke a built-in test mode.
if I/O CLK is not
CC
†
‡
Terminal numbers are for the D package.
Terminal numbers are for the DB, J, and FK packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
†
‡
NAME
NO.
NO.
I/O CLK
3
18
I
Input/output clock. I/O CLK receives the serial I/O clock input in the two modes and performs the following
four functions in each mode:
Microprocessor mode
•
When INVCLK = V , I/O CLK clocks the four input data bits into the input data register on the first four
CC
rising edges of I/O CLK after CS↓ with the multiplexer address available after the fourth rising edge.
When INV CLK = GND, input data bits are clocked in on the first four falling edges instead.
•
On the fourth falling edge of I/O CLK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth rising edge of I/O CLK except in the
extended sampling cycle where the duration of CSTART determines when to end the sampling cycle.
•
•
Output data bits change on the first ten falling I/O clock edges regardless of the condition of INV CLK.
I/O CLK transfers control of the conversion to the internal state machine on the tenth rising edge of I/O
CLK regardless of the condition of INV CLK.
Digital signal processor (DSP) mode
•
When INV CLK = V , I/O CLK clocks the four input data bits into the input data register on the first four
CC
falling edges of I/O CLK after FS↓ with the multiplexer address available after the fourth falling edges.
When INV CLK = GND, input data bits are clocked in on the first four rising edges instead.
•
On the fourth rising edge of I/O CLK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLK except in the
extended sampling cycle where the duration of CSTART determines when to end the sampling cycle.
•
•
Output data MSB shows after FS↓ and the rest of the output data bits change on the first ten rising I/O
CLK edges regarless of the condition of INV CLK.
I/O CLK transfers control of the conversion to the internal state machine on the tenth falling edge of I/O
CLK regardless of the condition of INV CLK.
REF+
REF–
15
14
I
Upper reference voltage (nominally V
). The maximum input voltage range is determined by the difference
CC
between the voltages applied to REF+ and REF–.
Lower reference voltage (nominally ground)
Positive supply voltage
14
5
13
20
I
I
V
CC
†
‡
Terminal numbers are for the D package.
Terminal numbers are for the DB, J, and FK packages.
detailed description
Initially, with CS high (inactive), DATA IN and I/O CLK are disabled and DATA OUT is in the high-impedance
state. When the serial interface takes CS low (active), the conversion sequence begins with the enabling of I/O
CLK and DATA IN and the removal of DATA OUT from the high-impedance state. The host then provides the
4-bit channel address to DATA IN and the I/O clock sequence to I/O CLK. During this transfer, the host serial
interfacealsoreceivesthepreviousconversionresultfromDATAOUT. I/OCLKreceivesaninputsequencefrom
the host that is from 10 to 16 clocks long. The first four valid I/O CLK cycles load the input data register with the
4-bit input data on DATA IN that selects the desired analog channel. The next six clock cycles provide the control
timing for sampling the analog input. Sampling of the analog input is held after the first valid I/O CLK sequence
of ten clocks. The tenth clock edge also takes EOC low and begins the conversion. The exact locations of the
I/O clock edges depend on the mode of operation.
serial interface
The TLV1548 is compatible with generic microprocessor serial interfaces such as SPI and QSPI, and a TMS320
DSP serial interface. The internal latched flag If_mode is generated by sampling the state of FS at the falling
edge of CS. If_mode is set to one (for microprocessor) when FS is high at the falling edge of CS, and If_mode
is cleared to zero (for DSP) when FS is low at the falling edge of CS. This flag controls the multiplexing of I/O
CLK and the state machine reset function. FS is pulled high when interfacing with a microprocessor.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
I/O CLK
The I/O CLK can go up to 10 MHz for most of the voltage range when fast I/O is possible. The maximum I/O
CLK is limited to 2.8 MHz for a supply voltage range from 2.7 V. Table 1 lists the maximum I/O CLK frequencies
for all different supply voltage ranges. This also depends on input source impedance. For example, I/O CLK
speed faster than 2.39 MHz is achievable if the input source impedance is less than 1 kΩ.
Table 1. Maximum I/O CLK Frequency
MAXIMUM INPUT
RESISTANCE (Max)
V
CC
SOURCE IMPEDANCE
I/O CLK
1 kΩ
100 Ω
1 kΩ
2.39 MHz
2.81 MHz
7.18 MHz
10 MHz
2.7 V
4.5 V
5 K
1 K
100 Ω
microprocessor serial interface
Input data bits from DATA IN are clocked in on the first four rising edges of the I/O CLK sequence if INV CLK
is held high when the device is in microprocessor interface mode. Input data bits are clocked in on the first four
falling edges of the I/O CLK sequence if INV CLK is held low. The MSB of the previous conversion appears on
DATA OUT on the falling edge of CS. The remaining nine bits are shifted out on the next nine edges (depending
on the state of INV CLK) of I/O CLK. Ten bits of data are transmitted to the host through DATA OUT.
A minimum of 9.5 clock pulses is required for the conversion to begin. On the tenth clock rising edge, the EOC
output goes low and returns to the high logic level when the conversion is complete; then the result can be read
by the host. On the tenth clock falling edge, the internal logic takes DATA OUT low to ensure that the remaining
bit values are zero if the I/O CLK transfer is more than ten clocks long.
CSisinactive(high)betweenserialI/OCLKtransfers. EachtransfertakesatleasttenI/OCLKcycles. Thefalling
edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge of
CSendsthesequencebyreturningDATAOUTtothehigh-impedancestatewithinthespecifieddelaytime. Also,
the rising edge of CS disables I/O CLK and DATA IN within a setup time. A conversion does not begin until the
tenth I/O CLK rising edge.
A high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the output data register holds the previous conversion result). CS should not be taken
low close to completion of conversion because the output data can be corrupted.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
DSP interface
The TLV1544/1548 can also interface with a DSP, from the TMS320 family for example, through a serial port.
The analog-to-digital converter (ADC) serves as a slave device where the DSP supplies FS and the serial I/O
CLK. Transmit and receive operations are concurrent. The falling edge of FS must occur no later than seven
I/O CLK periods after the falling edge of CS.
DSP I/O cycles differ from microprocessor I/O cycles in the following ways:
WheninterfacedwithaDSP, theoutputdataMSBisavailableafterFS↓. Theremainingoutputdatachanges
on the rising edge of I/O CLK. The input data is sampled on the first four falling edges of I/O CLK after FS↓
and when INV CLK is high, or the first four rising edges of I/O CLK after FS↓ and when INV CLK is low. This
operation is inverted when interfaced with a microprocessor.
A new DSP I/O cycle is started on the rising edge of I/O CLK after the rising edge of FS. The internal state
machineisresetoneachfallingedgeofI/OCLKwhenFSishigh. Thisoperationisoppositewheninterfaced
with a microprocessor.
The TLV1544/1548 supports a 16-clock cycle when interfaced with a DSP. The output data is padded with
six trailing zeros when it is operated in DSP mode.
Table 2. TLV1544/TLV1548 Serial Interface Modes
INTERFACE MODE
I/O
MICROPROCESSOR ACTION
Initializes counter
Resets state machine and disable I/O
DSP ACTION
CS↓
CS↑
Samples state of FS
Disables I/O
Connects to DSP FSX output
Initializes the state machine at each CLK↓ after FS↑
Starts a new cycle at each CLK↑ following the initialization
(initializes the counter)
FS
Connects to V
CC
Starts sampling of the analog input started at fourth I/O CLK↑
Conversion started at tenth I/O CLK↑
Starts sampling of the analog input at fourth I/O CLK↓
Starts sampling of the analog input at tenth I/O CLK↓
I/O CLK
DATA IN
Samples input data on I/O CLK↑ (INV CLK high)
Samples input data on I/O CLK↓ (INV CLK low)
Samples input data at I/O CLK↓ (INV CLK high)
Samples input data at I/O CLK↑ (INV CLK low)
Makes MSB available FS↓
Changes remaining data at each following I/O CLK↑ after
FS↓
Makes MSB available on CS↓
Changes remaining data on I/O CLK↓
DATA OUT
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
input data bits
DATA IN is internally connected to a 4-bit serial input data register. The input data selects a different mode or
selects different analog input channels. The host provides the data word with the MSB first. Each data bit clocks
in on the edge (rising or falling depending on the status of INV CLK and FS) of the I/O CLK sequence. The input
clock can be inverted by grounding INV CLK (see Table 3 for the list of software programmed operations set
by the input data).
Table 3. TLV1544/1548 Software-Programmed Operation Modes
INPUT DATA BYTE
FUNCTION SELECT
A3 – A0
BINARY
COMMENT
HEX
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Analog channel A0 for TLV1548 selected
Analog channel A1 for TLV1548 selected
Analog channel A2 for TLV1548 selected
Analog channel A3 for TLV1548 selected
Analog channel A4 for TLV1548 selected
Analog channel A5 for TLV1548 selected
Analog channel A6 for TLV1548 selected
Analog channel A7 for TLV1548 selected
Software power down set
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Channel 0 for TLV1544
Channel 1 for TLV1544
Channel 2 for TLV1544
Channel 3 for TLV1544
No conversion result (cleared by any access)
No conversion result (cleared by setting to fast)
No conversion result (cleared by setting to slow)
Output result = 200h
Fast conversion rate (10 µs) set
Slow conversion rate (40 µs) set
Self-test voltage (V
ref
– V )/2 selected
ref–
Self-test voltage V
Self-test voltage V
Reserved
selected
selected
Output result = 000h
ref
Output result = 3FFh
ref
No conversion result
Reserved
No conversion result
analog inputs and internal test voltages
The eight analog inputs and the three internal test inputs are selected by the 11-channel multiplexer according
to the input data bit as shown in Table 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.
The device can be operated in two distinct sampling modes: normal sampling mode (fixed sampling time) and
extended sampling mode (flexible sampling time). When CSTART is held high, the device is operated in normal
sampling mode. When operated in normal sampling mode, sampling of the analog input starts on the rising edge
of the fourth I/O CLK pulse in the microprocessor interface mode (and on the fourth falling edge of I/O CLK in
the DSP interface mode). Sampling continues for 6 I/O CLK periods. The sample is held on the falling edge of
the tenth I/O CLK pulse in the microprocessor interface mode. The sample is held on the falling edge of the tenth
I/O CLK pulse in the DSP interface mode.The three test inputs are applied to the multiplexer, then sampled and
converted in the same manner as the external analog inputs.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
converter
The CMOS threshold detector in the successive-approximation conversion system determines the value of
each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase
of the conversion process, the analog input is sampled by closing the S switch and all S switches
C
T
simultaneously. This action charges all of the capacitors to the input voltage.
In the next phase of the conversion process, all S and S switches are opened and the threshold detector
T
C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF –)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF –. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half V ), a bit 0 is placed in the
CC
output register and the 512-weight capacitor is switched to REF –. If the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight capacitor remains
connected to REF + through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
S
C
Threshold
Detector
To Output
Latches
512
Node 512
256
128
8
4
2
1
1
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
S
S
S
S
S
S
S
S
T
T
T
T
T
T
T
T
V
I
Figure 1. Simplified Model of the Successive-Approximation System
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
extended sampling, asynchronous start of sampling: CSTART operation
The extended sampling mode of operation programs the acquisition time (t
) of the sample-and-hold circuit.
ACQ
This allows the analog inputs of the device to be directly interfaced to a wide range of input source impedances.
The extended sampling mode consumes higher power depending on the duration of the sampling period
chosen.
CSTART controls the sampling period and starts the conversion. The falling edge of CSTART initiates the
sampling period of a preset channel. The low time of CSTART controls the acquisition time of the input
sample-and-hold circuit. The sample is held on the rising edge of CSTART. Asserting CSTART causes the
converter to perform a new sample of the signal on the preset valid MUX channel (one of the eight) and discard
the current conversion result ready for output. Sampling continues as long as CSTART is active (negative). The
rising edge of CSTART ends the sampling cycle. The conversion cycle starts two internal system clocks after
the rising edge of CSTART.
Once the conversion is complete, the processor can initiate a normal I/O cycle to read the conversion result and
set the MUX address for the next conversion. Since the internal flag AsyncFlag is set high, this flag setting
indicatesthe cycle is an output cycle, so no conversion is performed during the cycle. The internal state machine
tests the AsyncFlag on the falling edge of CS. AsyncFlag is set high at the rising edge of CSTART, and it is reset
low at the rising edge of each CS. A conversion cycle follows a sampling cycle only if AsyncFlag is tested as
low at the falling edge of CS. As shown in Figure 2, an asynchronous I/O cycle can be removed by two
consecutive normal I/O cycles.
Table 4. TLV1544/1548 Hardware Configuration for Different Operating Modes
OPERATING MODES
Normal sampling
CS
Low
Low
CSTART AsyncFlag at CS↓
ACTION
High
High
Low
Fixed 6 I/O CLK sampling, synchronous conversion follows
No sampling, no conversion
Normal I/O (read out only)
High
Flexible sampling period controlled by CSTART,
asynchronous conversion follows
Extended sampling
High
Low
N/A
9
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
Complete Extended
Extended
Sample
Cycle
Sample Cycle
Read Out
Cycle
Extended
Sample
Cycle
Normal
Cycle
Read Out
Cycle
Read Out
Cycle
Normal
Cycle
CS
FS
(DSP Mode)
t
t
ACQ
ACQ
CSTART
DATA IN
Aa
Ab
Ab
Ac
Ad
EOC
Hi–Z
Hi–Z
Hi–Z
Hi–Z
Hi–Z
Hi–Z
DATA OUT
X
Da
Db
Db
Dc
Async Flag
NOTES: A. Aa = Address for input channel a.
B. Da = Conversion result from channel a.
Figure 2. Extended Sampling Operation
reference voltage inputs
There are two reference inputs used with the TLV1544/TLV1548, REF+ and REF–. These voltage values
establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading
respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or be lower
than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REF+ and is at zero when the input signal is equal to or lower than REF–.
programmable conversion rate
The TLV1544/TLV1548 offers two conversion rates to maximize battery life when high-speed operation is not
necessary. The conversion rate is programmable. Once the conversion rate has been selected, it takes effect
immediately in the same cycle and stays at the same rate until the other rate is chosen. The conversion rate
should be set at power up. Activation and deactivation of the power-down state (digital logic active) has no effect
on the preset conversion rate.
10
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
Table 5. Conversion Rate and Power Consumption Selection
TYPICAL SUPPLY CURRENT, I
CC
CONVERSION TIME,
AVAILABLE V
RANGE
CC
CONVERSION RATE
INPUT DATA
POWER
DOWN
t
conv
OPERATING
Fast conversion speed
Slow conversion speed
7 µs typ
5.5 V to 3.3 V
5.5 V to 2.7 V
9h
Ah
0.6 mA typ
0.4 mA typ
1.5 mA max
1 mA max
1 µA typ
1 µA typ
15 µs typ
programmable power-down state
The device is put into the power-down state by writing 8h to DATA IN. The power-up state is restored during
the next active access by pulling CS low. The conversion rate selected before the device is put into the
power-down state is not affected by the power-down mode. Power-down can be used to achieve even lower
power consumption. This is because the sustaining power (when not converting) is only 1.3 mA maximum and
standby power is only 1 µA maximum. (By averaging out the power consumption can be much lower than the
1 mA peak when the conversion throughput is lower.)
Power Down
CS
Hi-Z
Hi-Z
DATA IN
EOC
1 0 0 0
Supply Current
1 mA
(Typical Peak Supply)
0.3 mA
I
(Typical Sustaining)
CC
0.0007 mA
(Typical Power Down
Supply)
0
Figure 3. Typical Supply Current During Conversion/Power Down
power up and initialization
After power up, if operating in DSP mode, CS and FS must be taken from high to low to begin an I/O cycle. EOC
is initially high, and the input data register is set to all zeroes. The content of the output data register is random,
and the first conversion result should be ignored. For initialization during operation, CS is taken high and
returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down
state can be invalid and should be disregarded.
When power is first applied to the device, the conversion rate must be programmed, and the internal Async Flag
must be taken low once. The rising edge of CS of the same cycle then takes Async Flag low.
11
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
First Cycle After Powerup
MUX Address for Channel 0
CS
FS
(For DSP Mode)
Async Flag
(Internal)
DATA IN
9h
0h
Ab
Signal Channel 0 Converted
EOC
Hi–Z
Hi–Z
Hi–Z
Hi–Z
DATA OUT
X
D0
X
Conversion Result From Channel 0
Conversion Rate Set to Fast
AsyncFlag Reset Low
Figure 4. Power Up Initialization
input clock inversion – INV CLK
The input data register uses I/O CLK as the source of the sampling clock. This clock can be inverted to provide
more setup time. INV CLK can invert the clock. When INV CLK is grounded, the input clock for the input data
register is inverted. This allows an additional one-half I/O CLK period for the input data setup time. This is useful
for some serial interfaces. When the input sampling clock is inverted, the output data changes at the same time
that the input data is sampled.
Table 6. Function of INV CLK
CONDITION
I/O CLK ACTIVE EDGE
CLOCK
OUTPUT DATA
CHANGES ON SAMPLED ON
INPUT DATA
INV CLK
FS at CS↓
†
High
High
Low
Low
High (MP mode)
↓
↑
↓
↑
↑
↓
↓
↑
‡
Low (DSP mode)
†
High (MP mode)
‡
Low (DSP mode)
†
‡
MP = microprocessor mode
DSP = digital signal processor mode
12
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
Threshold
Detect
REF+
REF–
EOC
Sample-
and-
Hold
Function
A0–A7
†
SAR Latch
11-to-1
Analog
10-to-1 Select
DATA OUT
INV CLK
TEST 0–2
MUX
Conversion
Clock
REF+
REF–
Output Shift Clock
V
ref
Invert
CS
FS
If_mode
If_mode
OSC
Input
Data
I/O CLK
DATA IN
Register
Control
State
Machine
SMCLK
If_mode
Input Shift Clock
2-to-1
Invert
2-to-1
§
DSP
‡
Microprocessor
†
Successive approximation register
‡
§
If_mode = 1, microprocessor interface mode
If_mode = 0, DSP interface mode
Figure 5. Clock Scheme
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
+ 0.3 V
+ 0.1 V
I
CC
CC
CC
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Positive reference voltage, V
Negative reference voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
ref+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V
ref–
Peak input current, I (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Operating free-air temperature range, T : TLV1544C, TLV1548C . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV1544I, TLV1548I . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLV1548M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND with REF– and GND wired together (unless otherwise noted).
13
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
2.7
5.5
CC
Positive reference voltage, V
(see Note 2)
(see Note 2)
– V (see Note 2)
V
V
V
ref+
Negative reference voltage, V
CC
0
V
ref–
Differential reference voltage, V
2.5
0
V +0.2
CC
V
ref+
ref–
CC
Analog input voltage, V
(see Note 2)
V
CC
V
I (analog)
High-level control input voltage, V
2.1
V
IH
Low-level control input voltage, V
0.6
V
IL
Setup time, input data bits valid before I/O CLK↑↓, t
(see Figure 9)
100
5
ns
ns
ns
ns
su(A)
(see Figure 9)
Hold time, input data bits valid after I/O CLK↑↓, t
30
30
h(A)
Setup time, CS↓ to I/O CLK↑, t
See Figure 10
See Figure 10
5
su(CS)
Hold time, I/O CLK↓ to CS↑, t
65
h(CS)
I/O CLK
periods
Pulse duration, FS high, t
See Figure 12
1
wH(FS)
Source impedance ≤ 1 kΩ,
See Figure 14
V
= 5.5 V,
CC
Pulse duration, CSTART, t
0.84
µs
w(CSTART)
Setup time, CS↑ to CSTART↓, t
See Figure 14
10
0.1
0.1
50
ns
su(CSTART)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V
= 2.7 V
= 5.5 V
= 2.7 V
= 5.5 V
= 2.7 V
6
2
10
Clock frequency at I/O CLK, f
MHz
ns
CLK
2.81
Pulse duration, I/O CLK high, t
wH(I/O)
wL(I/O)
100
50
Pulse duration, I/O CLK low, t
ns
100
Transition time, I/O CLK, t
(see Figure 11 and Note 4)
1
10
µs
µs
µs
µs
µs
t(I/O)
Transition time, DATA IN, t
(see Figure 9)
t(DATA IN)
Transition time, CS, t
(see Figure 10)
(see Figure 13)
10
t(CS)
Transition time, FS, t
10
t(FS)
Transition time, CSTART, t
(see Figure 14)
10
t(CSTART)
TLV1544C, TLV1548C
TLV1544I, TLV1548I
TLV1548M
0
–40
–55
70
Operating free-air temperature, T
85
°C
°C
A
125
115
115
150
TLV1544C, TLV1548C
TLV1544I, TLV1548I
TLV1548M
Junction temperature, T
J
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000). The device is functional with reference (V
V; however, the electrical specifications are no longer applicable.
– V ) down to 1
ref–
ref+
3. To minimize errors caused by noise at CS↓, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in an input dat until the minimum CS setup time has elapsed.
4. This is the time required for the I/O CLK signal to fall from V max to V min or to rise from V max to V min. Inthevicinityofnormal
IH
IL
IL
IH
room temperature, the devices function with an input clock transition time as slow as 1 µs for remote data-acquisition applications
where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
14
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
V
= V
= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHz (unless otherwise noted)
CC
ref+
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
V
V
= 5.5 V,
= 2.7 V,
= 5.5 V,
= 2.7 V,
I
I
I
I
= –0.2 mA
= –20 µA
= 0.8 mA
= 20 µA
2.4
CC
CC
CC
CC
OH
OH
OL
OL
V
High-level output voltage
Low-level output voltage
High-impedance output current
V
OH
V
CC–0.1
0.4
0.1
V
OL
V
= V
,
CS = V
CS = V
1
2.5
O
O
CC
= 0,
CC
CC
I
µA
OZ
–1
0.005
–2.5
2.5
I
I
High-level input current
Low-level input current
V = V
I CC
µA
µA
IH
V = 0
I
–0.005
2.5
IL
Conversion speed = fast,
For all digital inputs,
V
CC
= 3.3 V to 5.5 V
0.6
1.5
0 ≤ V ≤ 0.3 V or
I
V ≥ V
– 0.3 V
CC
I
I
Operating supply current
mA
CC
Conversion speed = slow,
For all digital inputs,
V
V
= 3.3 V to 5.5 V
= 2.7 V to 3.3 V
0.4
1
CC
0 ≤ V ≤ 0.3 V or
I
0.35
0.75
CC
V ≥ V
– 0.3 V
CC
I
V
= 3.3 V to 5.5 V
= 2.7 V to 3.3 V
1.5
1
mA
mA
Extended sampling mode
operating current
CC
CC
I
I
CC(ES)
V
Conversion speed = slow,
For all digital inputs,
0 ≤ V ≤ 0.3 V or
Sustaining supply current
V
CC
= 2.7 V to 3.3 V
0.3
1
mA
CC(ST)
I
V ≥ V
– 0.3 V
I
CC
For all digital inputs,
0 ≤ V ≤ 0.3 V or V ≥ V – 0.3 V
CC
I
I
Power-down supply current
25
µA
CC(PD)
I
I
Selected channel at V , unselected channel at 0 V
CC
Selected channel at 0 V, unselected channel at V
1
µA
µA
Selected channel leakage current
lkg
–1
CC
Maximum static analog
reference current into REF+
V
ref+
= V
= 5.5 V,
V = GND
ref–
1
µA
CC
Input capacitance, analog inputs
Input capacitance, control inputs
20
20
55
15
1
C ‡
pF
i
V
V
= 4.5 V
= 2.7 V
CC
Z ‡
i
Input multiplexer on resistance
kΩ
5
CC
†
‡
All typical values are at V
Not production tested.
= 5 V, T = 25°C.
A
CC
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
operating characteristics over recommended operating free-air temperature range,
V
= V
= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHz (unless otherwise noted)
CC
ref+
TEST
CONDITIONS
†
PARAMETER
MIN TYP
MAX
UNIT
E
Linearity error (see Note 6)
Differential linearity error
Offset error (see Note 7)
Gain error (see Note 7)
±0.5
±0.5
±1
±1
LSB
LSB
LSB
LSB
LSB
L
E
See Note 2
See Note 2
See Note 2
D
O
G
T
E
E
E
±1.5
±1
Total unadjusted error (see Note 8)
±1.75
DATA IN = 1011
DATA IN - 1100
DATA IN = 1101
512
0
Self-test output code (see Table 3 and Note 9)
1023
7
Fast conversion speed
10
25
µs
µs
See Figures 15
through 17
t
t
Conversion time
conv
Slow conversion speed
15
See Figures 15
through 18 and
Notes 10, 11, 12
10.1 +
10 I/O CLK
Fast conversion speed
Total cycle time (access,
sample, conversion and EOC↑
to CS↓ delay)
µs
c
See Figures 15
Slow conversion speed through 18 and
Notes 10 and 12
40.1 +
10 I/O CLK
See Figures 15
through 18 and
Note 10
I/O CLK
periods
t
Channel acquisition time (sample)
6
acq
t
t
t
Valid time, DATA OUT remains valid after I/O CLK↓
Delay time, I/O CLK high to FS high
See Figure 11
See Figure 13
See Figure 13
50
5
ns
ns
ns
v
30
30
50
60
d1(FS)
d2(FS)
Delay time, I/O CLK high to FS low
10
See Figure 14
and Note 5
t
t
t
Delay time, EOC↑ to CS low
Delay time, CS↓ to FS↑
100
1
ns
d(EOC↑ – CS↓)
d(CS↓ – FS↑)
d(I/O -CS)
See Figures 17
and 18
I/O CLK
periods
7
Delay time, 10th I/O CLK low to CS low to abort
conversion (see Note 13)
See Figure 10
1.1
µs
†
All typical values are at T = 25°C.
A
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
appliedtoREF–convertasallzeros(000000000000).Thedeviceisfunctionalwithreferencedownto1V(V +–V –1);however,
ref ref
the electrical specifications are no longer applicable.
5. For all operating modes.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage. Full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input data and the output codes are expressed in positive logic.
10. I/O CLK period = 1/(I/O CLK frequency) (see Figure 8).
11. For 3.3 V to 5.5 V only
12. For microprocessor mode
13. Any transitions of CS are recognized as valid only when the level is maintained for a setup time after the transition.
16
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
operating characteristics over recommended operating free-air temperature range,
V
= V
= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHz (unless otherwise noted) (continued)
CC
ref+
†
PARAMETER
TEST CONDITIONS
See Figure 11
See Figure 12
See Figure 8
MIN TYP
MAX
50
UNIT
ns
t
t
t
t
t
t
t
Delay time, I/O CLK low to DATA OUT valid
Delay time, 10th I/O CLK↓ to EOC low
d(I/O-DATA)
70
0.7
70
15
50
50
240
1.3
ns
d(I/O-EOC)
, t
PZH PZL
Enable time, CS low to DATA OUT valid (MSB driven)
Disable time, CS high to DATA OUT invalid (high impedance)
Fall time, EOC
µs
, t
See Figure 8
150
50
ns
PHZ PLZ
See Figure 12
See Figure 11
See Figure 11
ns
f(EOC)
r(bus)
f(bus)
Rise time, output data bus at 2.2 MHz I/O CLK
Fall time, output data bus at 2.2 MHz I/O CLK
250
250
ns
ns
†
All typical values are at T = 25°C.
A
PARAMETER MEASUREMENT INFORMATION
15 V
C1
10 µF
C2
0.1 µF
EOC
TLV1544/48
Ax
_
U1
+
V
I
D0
–15 V
C1
10 µF
C2
0.1 µF
LOCATION
DESCRIPTION
PART NUMBER
U1
C1
C2
OP27
—
—
10-µF 35-V tantalum capacitor
0.1-µF ceramic NPO SMD capacitor
AVX 12105C104KA105 or equivalent
Figure 6. Analog Input Buffer to Analog Inputs
V
CC
V
CC
Test Point
Test Point
R
= 2.18 kΩ
R
= 2.18 kΩ
L
L
EOC
DATA OUT
12 kΩ
12 kΩ
C
= 50 pF
C = 100 pF
L
L
Figure 7. Load Circuits
17
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Address
Valid
V
V
IH
90%
10%
90%
10%
DATA IN
t
V
V
10%
10%
t
IH
90%
IL
CS
t
10%
t
t (DATA IN)
t (DATA IN)
t
IL
, t
PZH PZL
h(A)
t
, t
su(A)
PHZ PLZ
V
V
V
IH
OH
90%
10%
90%
10%
I/O CLK
DATA
OUT
10%
IL
V
OL
t
t(I/O)
Figure 8. DATA OUT to Hi-Z Voltage Waveforms
Figure 9. DATA IN Setup Voltage Waveforms
t
t
t(CS)
t(CS)
V
V
IH
90%
90%
CS
10%
10%
IL
t
h(CS)
d(I/O-CS)
10%
t
su(CS)
t
I/O CLK
First
Clock
Last
Clock
10%
V
IL
Figure 10. CS and I/O CLK Voltage Waveforms
t
t(I/O)
t
t(I/O)
V
V
IH
90%
10%
I/O Clock Period
90%
10%
I/O CLK
10%
IL
t
d(I/O-DATA)
t
v
V
V
OH
90%
10%
90%
10%
DATA OUT
VALID
OL
t
, t
r(bus) f(bus)
Figure 11. DATA OUT and I/O CLK Voltage Waveforms
t
d(ES–FS
CS
FS
Figure 12. CS Low to FS Low
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
10th
Clock
I/O CLK
10%
10%
V
IL
t
d(I/O-EOC)
V
V
OH
EOC
(µp Mode)
10%
OL
t
d(I/O-EOC)
V
V
OH
EOC
(DSP Mode)
90%
10%
OL
t
f(EOC)
Figure 13. I/O CLK and EOC Voltage Waveforms
V
V
IH
90%
90%
I/O CLK
t
IL
t
d2(FS)
d1(FS)
t
t(FS)
t
t(FS)
V
V
IH
90%
10%
90%
10%
FS
IL
t
wH(FS)
Figure 14. FS and I/O CLK Voltage Waveforms
CS
10%
10%
V
IL
t
su(CSTART)
t
t(CSTART)
t
t(CSTART)
t
w(CSTART)
90%
90%
CSTART
10%
t
d(EOC↑-CS↓)
t
d(I/O-EOC)
EOC
10%
V
OL
Figure 15. CSTART and CS Waveforms
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Address Sampled
Conversion Starts on 10th I/O CLK↑
Rise After 10th I/O CLK↓
Conversion
t
d(EOC↑-CS↓)
Access
Sample
(6 I/O CLKs)
CS
(see Note A)
1
2
3
4
5
6
7
8
9
10
I/O CLK
DI
A3
A2
D8
A1
D7
A0
D6
A
D
3
MSB
Hi-Z
Hi-Z
D9
D5
D4
D3
D2
D1
D0
DO
9
0s
MSB
LSB
EOC
Initialize State Machine
and Counter
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
Figure 16. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High)
Address Sampled
Conversion Starts on 10th I/O CLK↑
Rise After 10th I/O CLK↓
Conversion
t
d(EOC↑-CS↓)
Access
Sample
(5.5 I/O CLKs)
CS
(see Note A)
1
2
3
4
5
6
7
8
9
10
I/O CLK
DI
A3
A2
A1
A0
A
D
3
9
MSB
Hi-Z
Hi-Z
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DO
0s
MSB
LSB
EOC
Initialize State Machine
and Counter
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time has elapsed.
Figure 17. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low)
20
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WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Initialize Counter
Address Sampled
Conversion Starts on 10th I/O CLK↓
CS Rise After 16th I/O CLK↓
Initialize State Machine
t
d(EOC↑-CS↓)
7 I/O CLKs
Maximum
Access
Sample
Hold/Conversion
(6 I/O CLKs)
CS
(see
Note A)
2
3
4
5
6
7
8
9
10
1
11
12 13
14
15
16
I/O CLK
FS
DI
A3
A2 A1
A0
D6
MSB
Hi-Z
DO
Hi-Z
D9 D8
MSB
D7
D5 D4
D3
D2 D1
D0
LSB
0s
EOC
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
Figure 18. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = High)
21
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Initialize Counter
Address Sampled
Conversion Starts on 10th I/O CLK↓
CS Rise After 16th I/O CLK↓
Initialize State Machine
t
d(EOC↑-CS↓)
7 I/O CLKs
Maximum
Access
Sample
Hold/Conversion
(6 I/O CLKs)
CS
(see
Note A)
2
3
4
5
6
7
8
9
10
1
11
12 13
14
15
16
I/O CLK
FS
DI
A3
A2 A1
A0
D6
MSB
Hi-Z
DO
Hi-Z
D9 D8
MSB
D7
D5 D4
D3
D2 D1
D0
LSB
0s
EOC
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS setup time elapses.
Figure 19. DSP Interface Timing (16-Clock Transfer, Normal Sample Mode, INV CLK = Low)
22
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
INTEGRAL NONLINEARITY ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.4
0.3
0.5
0.4
Maximum
Maximum
0.3
0.2
0.1
0.2
0.1
V
CC
= 2.7 V
V
CC
= 5.5 V
0
–0.1
–0.2
–0.3
–0.4
0
–0.1
–0.2
–0.3
–0.4
–0.5
Minimum
Minimum
75
–75
–25
T
25
75
125
–75
–25
25
125
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
A
Figure 20
Figure 21
DIFFERENTIAL NONLINEARITY ERROR
DIFFERENTIAL NONLINEARITY ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.4
0.3
0.6
0.4
0.2
Maximum
Maximum
0.2
0.1
0
V
CC
= 5.5 V
V
CC
= 2.7 V
0
–0.1
–0.2
–0.3
–0.4
–0.2
Minimum
75
Minimum
25
–0.4
–0.5
–0.6
–75
–25
25
125
–75
–25
75
125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 22
Figure 23
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.35
0.3
0.7
0.6
0.5
V
CC
= 2.7 V
0.25
V
CC
= 5.5 V
0.2
0.4
0.3
V
CC
= 2.7 V
0.15
0.1
0.2
0.1
V
CC
= 5.5 V
0.05
0
0
–75
–25
25
75
125
–75
–25
25
75
125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 24
Figure 25
TOTAL UNADJUSTED ERROR
vs
FREE-AIR TEMPERATURE
TOTAL UNADJUSTED ERROR
vs
FREE-AIR TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.2
1
Maximum
0.8
Maximum
0.6
0.4
0.2
0
V
CC
= 2.7 V
V
CC
= 5.5 V
Minimum
Minimum
25
–0.2
–0.4
–0.1
–0.2
–75
–25
T
A
25
75
125
–75
–25
T
A
75
125
– Free-Air Temperature – °C
– Free-Air Temperature – °C
Figure 26
Figure 27
24
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.56
0.54
0.52
0.5
0.48
0.46
0.44
V
= 5.5 V
CC
Clock Mode =
0.42
0.4
Fast Conversion
–75
–25
25
75
125
T
A
– Free-Air Temperature – °C
Figure 28
INTEGRAL NONLINEARITY ERROR
DIFFERENTIAL NONLINEARITY ERROR
vs
vs
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
2
1.6
2
1
V
T
= 2.7 V
V
T
= 2.7 V
= 25°C
CC
= 25°C
CC
A
A
Clock Mode = Fast
Clock Mode = Fast
1.2
0.8
0.4
0
0
–0.4
–0.8
–1.2
–1
–1.6
–2
–2
0
512
1023
0
512
1023
Digital Output Code
Digital Output Code
Figure 29
Figure 30
25
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
DIFFERENTIAL NONLINEARITY ERROR
vs
vs
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
V
T
= 5 V
CC
= –40°C
V
= 5 V
CC
= –40°C
A
T
A
Clock Mode = Fast
Clock Mode = Fast
0
–0.2
–0.4
–0.6
0
–0.2
–0.4
–0.6
–0.8
–1
–0.8
–1
0
512
1023
0
512
1023
Digital Output Code
Digital Output Code
Figure 31
Figure 32
INTEGRAL NONLINEARITY ERROR
DIFFERENTIAL NONLINEARITY ERROR
vs
vs
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
V
T
= 5 V
CC
= 25°C
V
= 5 V
CC
T = 25°C
A
A
Clock Mode = Fast
Clock Mode = Fast
0
–0.2
–0.4
–0.6
0
–0.2
–0.4
–0.6
–0.8
–1
–0.8
–1
0
512
1023
0
512
1023
Digital Output Code
Digital Output Code
Figure 33
Figure 34
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
0.2
V
T
= 5 V
CC
= 85°C
A
Clock Mode = Fast
0
–0.2
–0.4
–0.6
–0.8
–1
0
512
1023
Digital Output Code
Figure 35
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
V
T
= 5 V
CC
= 85°C
0.8
0.6
0.4
0.2
A
Clock Mode = Fast
0
–0.2
–0.4
–0.6
–0.8
–1
0
512
1023
Digital Output Code
Figure 36
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
APPLICATION INFORMATION
1023
1022
1021
1111111111
V
FS
See Notes A and B
1111111110
1111111101
V
FSnom
V
FT
= V
– 1/2 LSB
FS
513
512
1000000001
1000000000
V
ZT
= V
+ 1/2 LSB
ZS
511
0111111111
V
ZS
2
1
0
0000000010
0000000001
0000000000
0
0.0048 0.0096
2.4528 2.4576 2.4624
V – Analog Input Voltage – V
4.9128
4.9140 4.9152
I
NOTES: A. This curve is based on the assumption that V
ref+
and V have been adjusted so that the voltage at the transition from digital 0
ref–
to 1 (V ) is 0.0024 V, and the transition to full scale (V ) is 4.908 V. 1 LSB = 4.8 mV.
ZT FT
B. The full-scale value (V ) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V ) is
FS
ZS
the step whose nominal midstep value equals zero.
Figure 37. Ideal Conversion Characteristics
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SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
APPLICATION INFORMATION
V
CC
†
TLV1548
Microprocessor
20
12
V
CC
FS
15
18
I/O 2
11
CS
INV CLK
CLKX
CLKR
DX
I/O CLK
17
16
DATA IN
1–8
DATA OUT
DR
A0–A7
Analog Inputs
14
13
3 V dc
Regulated
REF+
REF–
GND
10
To Source Ground
†
DB package is shown for TLV1548
Figure 38. Typical Interface to a Microprocessor
V
CC
‡
TLV1548
20
V
15
18
CC
IO2
CS
11
INV CLK
CLKX
CLKR
DX
I/O CLK
TMS320 DSP
17
16
DATA IN
1–8
DATA OUT
DR
A0–A7
Analog Inputs
12
14
13
FS
REF+
REF–
FSX
FSR
3 V dc
Regulated
GND
10
To Source GND
‡
DB package is shown for TLV1548
Figure 39. Typical Interface to a TMS320 DSP
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WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
APPLICATIONS INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 33, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:
S
The capacitance charging voltage is given by:
–t R C
c
t
i
V
V
1–e
C
S
where
(1)
R = R + r
i
t
s
t = Cycle time
c
The input impedance Z is 1 kΩ at 5 V, and is higher (~ 5 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given by:
i
(2)
V (1/2 LSB) = V – (V /2048)
C
S
S
Equating equation 1 to equation 2 and solving for cycle time t gives:
c
–t R C
c
t
i
V
V
2048
V
1–e
S
S
S
(3)
and time to change to 1/2 LSB (minimum sampling time) is:
(1/2 LSB) = R × C × ln(2048)
t
ch
t
i
where
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
(1/2 LSB) = (R + 1 kΩ) × 55 pF × ln(2048)
(4)
t
ch
s
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x I/O CLK.
(5)
t
(1/2 LSB) ≤ 6x 1/f
I/O
ch
Therefore the maximum I/O CLK frequency is:
max(f ) = 6/t (1/2 LSB) = 6/(ln(2048) × R × C )
(6)
I/O
ch
t
i
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
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SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
APPLICATIONS INFORMATION
†
Driving Source
TLV1544/48
V
V
= Input Voltage at AIN
= External Driving Source Voltage
I
S
s
R
r
i
s
V
I
R = Source Resistance
V
S
V
r
= Input Resistance (MUX on Resistance)
C
i
1 kΩ
C = Input Capacitance
i
C
V
= Capacitance Charging Voltage
C
i
55 pF MAX
†
Driving source requirements:
•
•
Noise and distortion for the source must be equivalent to the resolution of the converter.
R must be real at the input frequency.
s
Figure 40. Equivalent Input Circuit Including the Driving Source
maximum conversion throughput
For a supply voltage at 5 V, if the source impedance is less than 1 kΩ, this equates to a minimum sampling
time t (0.5 LSB) of 0.84 µs. Since the sampling time requires six I/O clocks, the fastest I/O clockfrequency is
ch
6/t = 7.18 MHz. The minimal total cycle time is given as:
ch
t = t
+ t
+ t
+ t
c
address
sample
conv d(EOC↑ – CS↓)
= 0.56 µs + 0.84 µs + 10 µs + 0.1 µs
= 11.5 µs
A maximum throughput of 87 KSPS. The throughput can be even higher with a smaller source impedance.
When source impedance is 100Ω, the minimum sampling time is 0.46 µs. The maximum I/O clock frequency
possible is almost 13 MHz. Then 10 MHz clock (maximum I/O CLK for TLV1544/1548) can be used. The minimal
total cycle time is:
t = t
+ t
+ t
+ t
c
address
sample
conv d(EOC↑ – CS↓)
= 4 × 1/f + 0.46 µs + 10 µs + 0.1 µs
= 0.4 µs + 0.46 µs + 10 µs + 0.1 µs
= 10.96 µs
The maximum throughput is 1/10.96 µs = 91 KSPS for this case.
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,65
28
M
0,15
0,22
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
14
PINS **
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /D 02/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
MECHANICAL DATA
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
18 17 16 15 14 13 12
TERMINALS
MIN
MAX
MIN
MAX
**
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
21
22
23
24
25
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
B SQ
A SQ
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
MECHANICAL DATA
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
0.785
0.910
0.975
(19,94) (19,94) (23,10) (24,77)
C
0.755
(19,18) (19,18)
0.755
0.930
(23,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,65
M
0,10
0,19
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
0,75
A
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/E 08/96
NOTES: F. All linear dimensions are in millimeters.
G. This drawing is subject to change without notice.
H. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
I. Falls within JEDEC MO-153
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
SOIC
Drawing
5962-9853801Q2A
5962-9853801QRA
TLV1544CD
ACTIVE
ACTIVE
ACTIVE
FK
J
20
20
16
1
1
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1544CDG4
TLV1544CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
20
20
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1544CDRG4
TLV1544CPW
TLV1544CPWG4
TLV1544CPWR
TLV1544CPWRG4
TLV1544ID
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1544IDG4
TLV1544IDR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1544IDRG4
TLV1544IPW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
SSOP
SSOP
PW
PW
PW
PW
DB
DB
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1544IPWG4
TLV1544IPWR
TLV1544IPWRG4
TLV1548CDB
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1548CDBG4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1548CDBLE
TLV1548CDBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
20
20
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1548CDBRG4
TLV1548IDB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1548IDBG4
TLV1548IDBR
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV1548IDBRG4
ACTIVE
SSOP
DB
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV1548MFKB
TLV1548MJ
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CDIP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
TLV1548MJB
J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV1548, TLV1548M :
Automotive: TLV1548-Q1
Enhanced Product: TLV1548-EP
•
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLV1544CDR
TLV1544CPWR
TLV1544IDR
SOIC
TSSOP
SOIC
D
16
16
16
16
20
20
2500
2000
2500
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
16.4
16.4
6.5
6.67
6.5
10.3
5.4
2.1
1.6
2.1
1.6
2.5
2.5
8.0
8.0
16.0
12.0
16.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
PW
D
10.3
5.4
8.0
TLV1544IPWR
TLV1548CDBR
TLV1548IDBR
TSSOP
SSOP
SSOP
PW
DB
DB
6.67
8.2
8.0
7.5
12.0
12.0
8.2
7.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV1544CDR
TLV1544CPWR
TLV1544IDR
SOIC
TSSOP
SOIC
D
16
16
16
16
20
20
2500
2000
2500
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
29.0
33.0
29.0
33.0
33.0
PW
D
TLV1544IPWR
TLV1548CDBR
TLV1548IDBR
TSSOP
SSOP
SSOP
PW
DB
DB
Pack Materials-Page 2
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