TLV1571CPW [TI]

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS; 2.7 V至5.5 V ， 1 / 8通道， 10位，并行模拟 - 数字转换器


型号：	TLV1571CPW
厂家：	TEXAS INSTRUMENTS
描述：	2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS 2.7 V至5.5 V ， 1 / 8通道， 10位，并行模拟 - 数字转换器转换器
文件：	总29页 (文件大小：434K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

features

TLV1578

DA PACKAGE

(TOP VIEW)

Fast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

CH0

CH1

CH2

CH3

CLK

DGND

CH7

CH6

CH5

CH4

Wide Analog Input: 0 V to AV

Differential Nonlinearity Error: < ± 1 LSB

Integral Nonlinearity Error: < ± 1 LSB

8-to-1 Analog MUX – TLV1578

Internal OSC

AIN

AGND

REFM

REFP

CSTART

D9/A1

D8/A0

Single 2.7-V to 5.5-V Supply Operation

Low Power: 12 mW at 3 V and 35 mW at 5 V

Auto Power Down of 1 mA Max

Software Power Down: 10 µA Max

Hardware Configurable

INT/EOC

DSP and Microcontroller Compatible

Parallel Interface

TLV1571

DW OR PW PACKAGE

(TOP VIEW)

Binary/Twos Complement Output

Hardware Controlled Extended Sampling

AIN

Channel Sweep Mode Operation and

Channel Select

CLK

DGND

AGND

REFM

REFP

CSTART

D9/A1

D8/A0

Hardware or Software Start of Conversion

applications

INT/EOC

Mass Storage and HDD

Automotive

Digital Servos

Process Control

General-Purpose DSP

Image Sensor Processing

NC – No internal connection

description

The TLV1571/1578 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a

high-speed 10-bit ADC, and a parallel interface. The device contains two on-chip control registers allowing

control of channel selection, software conversion start, and power down via the bidirectional parallel port. The

control registers can be set to a default mode by applying a dummy RD signal when WR is tied low. This allows

the TLV1571/1578 to be configured by hardware. The MUX is independently accessible. This allows the user to

insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and

the ADC. Therefore, one signal conditioning circuit can be used for all eight channels. The TLV1571 is a single

channel analog input device with all the same functions as the TLV1578.

The TLV1571/TLV1578 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range

from0VtoAV anddigitizestheinputatamaximum1.25MSPSthroughputrateat5V. Thepowerdissipations

are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode

that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the

ADC is further powered down to only 10 µA.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

description (continued)

Very high throughput rate, simple parallel interface, and low power consumption make the TLV1571/TLV1578

an ideal choice for high-speed digital signal processing requiring multiple analog inputs.

AVAILABLE OPTIONS

PACKAGE

32 TSSOP

(DA)

24 SOP

(DW)

24 TSSOP

(PW)

0°C to 70°C

TLV1578CDA

TLV1578IDA

TLV1571CDW

TLV1571IDW

TLV1571CPW

TLV1571IPW

–40°C to 85°C

functional block diagram – TLV1571/78

REFP

REFM

MO AV

AIN

CH0 – CH7

MUX

D0 – D7

Three

State

Latch

10-BIT

SAR ADC

TLV1578 Only

D8/A0

D9/A1

Internal

Clock

MUX

CLK

Input Registers

and Control Logic

INT/EOC

CSTART

AGND

DGND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

Terminal Functions

TERMINAL

NO.

TLV1571 TLV1578

I/O

DESCRIPTION

NAME

AGND

AIN

–

Analog ground

ADC analog input (used as single analog input channel for TLV1571)

Analog supply voltage, 2.7 V to 5.5 V

CH0 – CH7

1–4,

Analog input channels

29–32

CLK

External clock input

Chip select. A logic low on CS enables the TLV1571/TLV1578.

CSTART

Hardware sample and conversion start input. The falling edge of CSTART starts sampling and

the rising edge of CSTART starts conversion.

DGND

Digital ground

Digital supply voltage, 2.7 V to 5.5 V

D0 – D7

8–12,

13–15

12–16,

17–19

I/O Bidirectional 3-state data bus

D8/A0

I/O Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0

and CR1 for initialization.

D9/A1

I/O Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0

and CR1 for initialization.

End-of-conversion/interrupt

INT/EOC

On-chip mux analog output

Not connected

Read data. A falling edge on RD enables a read operation on the data bus when CS is low.

REFM

Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be

grounded.

REFP

Upper reference voltage (nominally AV ). The maximum input voltage range is determined by

the difference between the voltage applied to REFP and REFM.

Write data. A rising edge on the WR latches in configuration data when CS is low. When using

software conversion start, a rising edge on WR also initiates an internal sampling start pulse.

When WR is tied to ground, the ADC in nonprogrammable (hardware configuration mode).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

detailed description

Ain

Charge

Redistribution

DAC

SAR

ADC Code

REFM

Control

Logic

Figure 1. Analog-to-Digital SAR Converter

The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a

simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, theSARcontrollogicandchargeredistributionDACareusedtoaddandsubtractfixedamountsofcharge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

sampling frequency, f

The TLV1571/TLV1578 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling

frequency achievable with a given CLK frequency is:

= (1/16) f

CLK

s(max)

The TLV1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which

CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A

description of the control registers is shown in Figure 2.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

detailed description (continued)

control registers

Control Register Zero (CR0)

D7 D6

STARTSEL PROGEOC CLKSEL

A(1:0)=00

†

SWPWDN MODESEL

CHSEL(2–0)

Single

Input

D(2–0)

Channels Swept

HARDWARE INT

START

(CSTART)

NORMAL

Single

Channel

Internal

Clock

0,1

EOC

Powerdown Sweep

Mode

0,1,2,3

SOFTWARE

START

External

Clock

0,1,2,3,4,5,

0,1,2,3,4,5,6,7

N/A

Control Register One (CR1)

‡

READREG

STEST1

STEST0

A(1:0)=01

RESERVED OSCSPD 0 Reserved 0 Reserved OUTCODE

IF READREG = 0

ACTION

Output =

CR1.(1–0)

INT. OSC.

SLOW

INT. OSC.

FAST

Reserved Binary

Enable Self

Test

Enable

Read back

Reserved

Bit

Always

Write 0

Reserved

Bit

Always

Write 0

Bit,

Always

Write 0

CONVERSION result

Output =

SELF TEST 1 result

Output =

SELF TEST 2 result

Output =

SELF TEST 3 result

Complement

IF READREG = 1

Output Contents of

CR0

Output Contents of

CR1

RESERVED

†

‡

Don’t care for TLV1571

When in read back mode, the values read from the control register reserved bits are don’t care.

Figure 2. Input Data Format

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

detailed description (continued)

hardware configuration option

The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a

dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control

registers. TheADCisconfiguredideallyfor3-Voperation, whichmeanstheinternalOSCissetat10MHz, single

channel input mode, and hardware start of conversion using CSTART.

ADC conversion modes

The TLV1571/TLV1578 provides two conversion modes and two start of conversion modes. In single channel

input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the

TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these

modes in more detail.

Table 1. Conversion Modes

START OF

CONVER-

SION

COMMENT–SET BITS

CR0.D(2–0) FOR INPUT

MODES

OPERATION

Single

Hardware • Repeated conversions from a selected channel

Start • CSTART falling edge to start sampling

(CSTART) • CSTART rising edge to start conversion

CR0.D3 = 0 CR0.D7 = 0 • If in INT mode, one INT pulse generated after each conversion

CSTART rising edge must

be applied a minimum of

5 ns before or after CLK

rising edge.

Channel

†

Input

CR1.D7 = 0

• If in EOC mode, EOC will go high to low at start of conversion, and return high

at end of conversion.

Software

Start

CR0.D7 = 1

• Repeated conversions from a selected channel

• WRrisingedgetostartsamplinginitially.Thereafter, samplingoccursattherising and RD rising edge must be

edge of RD. a minimum 5 ns before or

With external clock, WR

• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT after CLK rising edge.

mode, one INT pulse is generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion and return high at

end of conversion.

Channel

Sweep

Hardware • One conversion per channel from a predetermined sequence of channels

Start • CSTART falling edge to start sampling

CSTART rising edge must

be applied a minimum of

5 ns before or after CLK

rising edge.

CR0.D3 = 1 (CSTART) • CSTART rising edge to start conversion

CR1.D7 = 0 CR0.D7 = 0 • If in INT mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion, and return high

at end of conversion.

Software

Start

• One conversion per channel from a sequence of channels

• WR rising edge to start sampling

With external clock, WR

and RD rising edge must be

CR0.D7 = 1 • ADC proceeds to sample next channel at rising edge of RD. Conversion begins a minimum 5 ns before or

after 6 clocks and lasts 10 clocks

after CLK rising edge.

• If in INT mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion and return high at

end of conversion.

†

Single channel input mode repeatedly samples and converts from the channel until WR is applied.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

detailed description (continued)

configure the device

The device can be configured by writing to control registers CR0 and CR1.

Table 2. TLV1571/TLV1578 Programming Examples

INDEX

COMMENT

EXAMPLE1

CR0

Single channel

Single Input

CR1

EXAMPLE2

CR0

Sweep mode

CR1

2’s complement output

Control data written to the TLV1571/78 can be read back from the control registers CR0 and CR1. See Figure 2.

NOTE:

Data read out of CR1 reserved bits is don’t care.

power down

The TLV1571/TLV1578 offers two power-down modes, auto power down and software power down. This device

will automatically proceed to auto power-down mode if RD is not present one clock after conversion. Software

power down is controlled directly by the userby pulling CS to DV

Table 3. Power Down Modes

SOFTWARE POWER DOWN

(CS = DV

PARAMETERS/MODES

AUTO POWER DOWN

)

10 µA

Maximum power down dissipation current

Comparator

1 mA

Power down

Active

Power down

Saved

Clock buffer

Reference

Control registers

Saved

Minimum power down time

Minimum resume time

1 CLK

2 CLK

1 CLK

2 CLK

self-test modes

The TLV1571/TLV1578 provides three self test modes. These modes can be used to check whether the ADC

itself is working properly without having to supply an external signal. There are three tests that are controlled

by writing to CR1(D1,D0) (see Table 4).

Table 4. Self Tests

CR1(D1,D0)

SELF TEST VOLTAGE APPLIED

Normal, no self test applied

DIGITAL OUTPUT

N/A

VREFM applied to ADC input internally

(VREFP–VREFM)/2 applied to ADC input internally

VIN = VREFP applied to ADC input internally

000h

200h

3FFh

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

detailed description (continued)

reference voltage input

The TLV1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins

establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading

respectively. The values of REFP, REFM, and the analog input should not exceed the positive supply or be less

than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the

input signal is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.

sampling/conversion

All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or

CSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and

CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay

close to the rising edge of the external clock (if they are used as CLK). The minimum setup and hold time with

respect to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this

is not an issue since these two edges will start the internal clock automatically. Therefore, the setup time is

always met. Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal

oscillator if enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from

0.6 µs to 0.3 µs. The internal oscillator frequency is 9 MHz minimum (oscillator frequency is between 9 MHz

to22MHz), translatingintoasamplingtimefrom0.6 µsto0.3 µs. Conversionbeginsimmediatelyaftersampling

and lasts 10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal

oscillator (9 MHz minimum) if enabled. Hardware controlled sampling, via CSTART, begins on falling CSTART

lasts the length of the active CSTART signal. This allows more control over the sampling time, which is useful

when sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in

hardwarecontrolledmodealsolasts10clockcycles. Thisisdoneusingtheexternalclockinput(1MHz–20MHz)

or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.

ExtClk

≥5 ns

h(WRL_EXTCLKH)

≥5 ns

su(WRH_EXTCLKH)

≥5 ns

h(RDL_EXTCLKH)

≥5 ns

su(RDH_EXTCLKH)

≥5 ns

h(CSTARTL_EXTCLKH)

su(CSTARTH_EXTCLKH)

≥5 ns

d(EXTCLK_CSTARTL)

≥5 ns

CSTART

NOTE: t = setup time, t = hold time

Figure 3. Trigger Timing – Software Start Mode Using External Clock

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

start of conversion mechanism

There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins

sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start

mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion

process lasts only 16 clocks in this case. If RD is not detected during the next clock cycle, the ADC automatically

proceeds to a power down state. Data is valid on the rising edge of INT in both conversion modes.

hardware CSTART conversion

external clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and

conversion begins at the rising edge of CSTART. At the end of conversion, EOC goes from low to high, telling

the host that conversion is ready to be read out. The external clock is active and is used as the reference at all

times. With this mode, it is required that CSTART is not applied at the rising edge of the clock (see Figure 4).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

start of conversion mechanism (continued)

CLK

su(CSL_WRL)

su(CSL_RDL)

h(WRH_CSH)

su(CSL_RDL)

h(RDH_CSH)

d(CSH_CSTARTL)

(sample)

(I/O CLKs)

(Channel 0)

(see Note A)

(Channel 0)

(see Note A)

CSTART

su(DAV_WRH)

dis(RDH_DAV)

h(WRH_DAV)

Config

Data

D[0:9]

INT

ADC

en(RDL_DAV)

EOC

Auto Powerdown

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 4. Multichannel Input Mode Conversion – Hardware CSTART, External Clock

internal clock

In single channel input mode, with CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART, and

conversion begins at the rising edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after

each conversion.

su(CSL_WRL)

h(WRH_CSH)

su(CSL_RDL)

d(CSH_CSTARTL)

(STARTOSC)

(sample)

(Channel 0)

(see Note A)

h(RDH_CSH)

CSTART

INTCLK

(Channel 1)

(see Note A)

(STARTOSC)

su(DAV_WRH)

h(WRH_DAV)

dis(RDH_DAV)

Config

Data

D[0:9]

INT

ADC

Data

ADC

Data

en(RDL_DAV)

EOC

Auto Powerdown

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 5. Multichannel Input Mode Conversion – Hardware CSTART, Internal Clock

software START conversion

external clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks

after sampling begins. At the end of conversion, INT goes low telling the host that conversion is ready to be read out. EOC is low during the

conversion and makes a high-to-low transition at the end of the conversion. The external clock is active and used as the reference at all times.

With this mode, WR and RD should not be applied at the rising edge of the clock (see Figure 3).

CLK

su(CSL_RDL)

su(CSL_WRL)

h(RDH_CSH)

su(CSL_RDL)

h(WRH_CSH)

(sample)

(Channel 0)

(see Note A)

(Channel 1)

(see Note A)

su(DAV_WRH)

dis(RDH_DAV)

h(WRH_DAV)

Config

Data

D[0:9]

INT

ADC Data

en(RDL_DAV)

EOC

Auto Powerdown

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 6. Multichannel Input Mode Conversion – Software Start, External Clock

software START conversion (continued)

internal clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling

begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins

at the rising edge of RD.

su(CSL_RDL)

h(RDH_CSH)

su(CSL_WRL)

h(WRH_CSH)

(STARTOSC)

INTCLK

(sample)

(Channel 0)

(see Note A)

(Channel 1)

(see Note A)

su(DAV_WRH)

dis(RDH_DAV)

h(WRH_DAV)

Config

Data

ADC

Data

D[0:9]

INT

ADC

en(RDL_DAV)

EOC

Auto Powerdown

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 7. Multichannel Input Mode Conversion – Software Start, Internal Clock

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

software START conversion (continued)

system clock source

The TLV1571/TLV1578 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used

for most conversion subtasks. The source of SYSCLK is programmable via control register zero bit 5. The

source of SYSCLK is changed at the rising edge of WR of the cycle when CR0.D5 is programmed.

internal clock (CR0.D5 = 0, SYSCLK = internal OSC)

The TLV1571/TLV1578 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of

SYSCLK, the internal clock starts with a delay (one half of the OSC period max) after the falling edge of the

conversion trigger (either WR, RD, or CSTART). The OSC speed can be set to 10 ± 1 MHz or 20 ± 2 MHz by

setting register bit CR1.6.

external clock (CR0.D5 = 1, SYSCLK = external clock)

The TLV1571/TLV1578 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from

1 MHz to 20 MHz.

host processor interface

The TLV1571/TLV1578 provides a generic high-speed parallel interface that is compatible with

high-performance DSPs and general-purpose microprocessors. The interface includes D(0–9), INT/EOC, RD,

and WR.

output format

The data output format is unipolar (code 0 to 1023) when the device is operated in single-ended input mode.

The output code format can be either binary or twos complement by setting register bit CR1.D3.

power up and initialization

After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV1571/TLV1578 requires

two write cycles to configure the two control registers. The first conversion after the device has returned from

the power down state may be invalid and should be disregarded.

definitions of specifications and terminology

integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points.

differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition

should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual

difference between first and last code transitions and the ideal difference between first and last code transitions.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

software START conversion (continued)

signal-to-noise ratio + distortion (SINAD)

Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all

other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective

number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its

measured SINAD.

total harmonic distortion (THD)

Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the

measured input signal and is expressed as a percentage or in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak

spurious signal.

DSP interface

The TLV1571/TLV1578 is a 10-bit 1-/8-analog input channel analog-to-digital converter with throughput up to

1.25 MSPS at 5 V and up to 625 KSPS at 3 V. To achieve 1.25 MSPS throughout, the ADC must be clocked

at 20 MHz. Likewise to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The

TLV1571/TLV1578 can be easily interfaced to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin

connections to interface the TLV1571/TLV1578 to the TMS320C6x DSP.

TMS320C6X

A0–A15

TLV1571/78

Address

Decoder

†

CH(1–8)

REF

REFP

REFM

EOC

D0–D9

INTx

D0–D15

The TLV1571 has only one analog input (AIN).

†

Figure 8. TMS320C6x DSP Interface

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

grounding and decoupling considerations

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back

into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.

In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency

range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be

placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be

shorted immediately outside the package. This can be accomplished by running a low impedance line between

DGND and AGND under the package.

TLV1571/78

AGND

REFP

REFM

100 nF

REFP

100 nF

REFM

DGND

100 nF

Figure 9. Placement for Decoupling Capacitors

power supply ground layout

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.

Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected

together at the low-impedance power-supply source. The best ground connection may be achieved by

connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground

currents are well managed.

†

Driving Source

TLV1571/78

= Input Voltage at AIN

= External Driving Source Voltage

i(MUX)

AIN

R = Source Resistance

i(ADC)

= Input Resistance of ADC

= Input Resistance (MUX on resistance)

i(ADC)

i(MUX)

C = Input Capacitance

= Capacitance Charging Voltage

15 pF

†

Driving source requirements:

•

Noise and distortion for the source must be equivalent to the resolution of the converter.

R must be real at the input frequency.

Figure 10. Equivalent Input Circuit Including the Driving Source

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

simplified analog input analysis

Using the equivalent circuit in Figure 9, the time required to charge the analog input capacitance from 0 to V

within 1/2 LSB, t (1/2 LSB), can be derived as follows.

The capacitance charging voltage is given by:

–t

R C

1–e

C(t)

Where:

(1)

R = R + R

R = R

+ R

i(MUX)

i(ADC)

= Charge time

The input impedance R is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given

by:

(2)

V (1/2 LSB) = V – (V /2048)

Equating equation 1 to equation 2 and solving for cycle time t gives:

–t

R C

1–e

2048

(3)

and time to change to 1/2 LSB (minimum sampling time) is:

(1/2 LSB) = R × C × ln(2048)

Where:

ln(2048) = 7.625

Therefore, with the values given, the time for the analog input signal to settle is:

(1/2LSB)=(R + 718 Ω)× 15 pF × ln(2048)

(4)

(5)

(6)

This time must be less than the converter sample time shown in the timing diagrams, which is 6x SCLK.

(1/2 LSB) ≤ 6x 1/f

(SCLK)

Therefore the maximum SCLK frequency is:

Max(f ) = 6/t (1/2 LSB) = 6/(ln(2048) × R × C )

(SCLK)

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, GND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV

Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV

+ 0.3 V

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C

Operating free-air temperature range, T : TLV1571C, TLV1578C . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

TLV1571I, TLV1578I . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN

2.7

MAX

5.5

UNIT

Analog supply voltage, AV

Digital supply voltage, DV

2.7

5.5

NOTE 1: Abs (AV

– DV ) < 0.5 V

analog inputs

MIN

MAX

UNIT

Analog input voltage, AIN

AGND VREFP

digital inputs

MIN NOM

MAX

UNIT

High-level input voltage, V

= 2.7 V to 5.5 V

= 4.5 V to 5.5 V

= 2.7 V to 3.3 V

= 4.5 V to 5.5 V, f

= 2.7 V to 3.3 V, f

= 4.5 V to 5.5 V, f

= 2.7 V to 3.3 V, f

2.1

2.4

Low level input voltage, V

0.8

MHz

Input CLK frequency

= 20 MHz

= 10 MHz

= 20 MHz

= 10 MHz

CLK

Pulse duration, CLK high, t

w(CLKH)

Pulse duration, CLK low, t

w(CLKL)

Rise time, I/O and control, CLK, CS

Fall time, I/O and control, CLK, CS

50 pF output load

reference specifications

MIN

NOM

MAX

UNIT

= 3 V

VREFP

= 5 V

2.5

External reference voltage

= 3 V

= 5 V

AGND

VREFM

VREFP – VREFM

AV –AGND

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted)

digital specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic inputs

High-level input current

Low-level input current

Input capacitance

= 5 V, DV

= 3 V, Input = DV

= 3 V, Input = 0 V

–1

µA

= 5 V, DV

–1

Logic outputs

High-level output voltage

= 50 µA to 0.5 mA

DV –0.4

Low-level output voltage

0.4

High-impedance-state output current

Low-impedance-state output current

Output capacitance

= 5 V, DV

= 3 V, Input = DV

= 3 V, Input = 0 V

µA

–1

3 V, AV

5 V, AV

= DV

Internal clock

MHz

dc specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

Accuracy

Integral nonlinearity, INL

Best fit

±0.5

±1

LSB

Differential nonlinearity, DNL

Missing codes

Offset error

±0.1% ±0.15%

FSR

Gain error

±0.1%

±0.2%

Analog input

AIN, AV

= 3 V, AV

= 5 V

µA

= 3 V, AV

Input capacitance

MUX input, AV

= 5 V

Input leakage current

Input MUX ON resistance

AIN

= 0 to AV

±1

680

340

lkg

= DV

= 3 V

= 5 V

240

215

Ω

Voltage reference input

Input resistance

kΩ

Input capacitance

300

Power supply

= DV

= 3 V, f

= 5 V, f

= 10 MHz

= 20 MHz

5.5

8.5

CLK

Operating supply current, I

+ I

DD REF

AV +DV

= 3 V

= 5 V

Power dissipation

AV +DV

= 3 V

= 5 V

= 3 V

= 5 V

µA

Software

+ I

DD REF

Supply current in power-down mode

0.5

Auto

I + I

DD REF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range, supply

voltages, and reference voltages (unless otherwise noted) (continued)

ac specifications, AV

= DV

= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 1.25 MSPS, AV

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

= 5 V

= 3 V

f = 100 kHz,

Signal-to-noise ratio, SNR

80% of FS

f = 625 KSPS, AV

f = 1.25 MSPS, AV

f = 100 kHz,

80% of FS

Signal-to-noise ratio + distortion, SINAD

Total harmonic distortion, THD

f = 625 KSPS, AV

f = 1.25 MSPS, AV

–60

9.3

–63

–56

f = 100 kHz,

80% of FS

f = 625 KSPS, AV

f = 1.25 MSPS, AV

Bits

f = 100 kHz,

80% of FS

Effective number of bits, ENOB

f = 625 KSPS, AV

f = 1.25 MSPS, AV

–56

f = 100 kHz,

80% of FS

Spurious free dynamic range, SFDR

f = 625 KSPS, AV

Analog input

Channel-to-channel cross talk

–75

–1 dB

Full-scale 0 dB input sine wave

–20 dB input sine wave

MHz

Full-power bandwidth

Small-signal bandwidth

–3 dB

–1 dB

–3 dB

–20 dB input sine wave

= 4.5 V to 5.5 V

= 2.7 V to 3.3 V

0.0625

1.25 MSPS

0.625 MSPS

Sampling rate, f

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

timing requirements, AV

= DV

= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

= 4.5 V to 5.5 V

Cycle time, CLK

c(CLK)

= 2.7 V to 3.3 V

100

SYSCLK

Cycles

Reset and sampling time

Total conversion time

(sample)

SYSCLK

Cycles

SYSCLK

Cycles

Pulse width, end of conversion, EOC

Pulse width, interrupt

wL(EOC)

wL(INT)

SYSCLK

Cycles

Start-up time, internal oscillator

100

(STARTOSC)

Delay time, CS high to CSTART low

d(CSH_CSTARTL)

= 5 V at 50 pF

= 3 V at 50 pF

= 5 V at 50 pF

= 3 V at 50 pF

Enable time, data out

Disable time, data out

en(RDL_DAV)

dis(RDH_DAV)

Setup time, CS to WR

Hold time, CS to WR

su(CSL_WRL)

h(WRH_CSH)

Clock

Pulse width, write

Pulse width, read

w(WR)

Period

Clock

Period

w(RD)

Setup time, data valid to WR

Hold time, data valid to WR

Setup time, CS to RD

su(DAV_WRH)

h(WRH_DAV)

su(CSL_RDL)

Hold time, CS to RD

h(RDH_CSH)

Hold time WR to clock high

Hold time RD to clock high

h(WRL_EXTXLKH)

h(RDL_EXTCLKH)

h(CSTARTL_EXTCLKH)

su(WRH_EXTCLKH)

su(RDH_EXTCLKH)

su(CSTARTH_EXTCLKH)

d(EXTCLK_CSTARTL)

Hold time CSTART to clock high

Setup time WR high to clock high

Setup time RD high to clock high

Setup time CSTART high to clock high

Delay time clock low to CSTART low

NOTE: Specifications subject to change without notice.

Data valid is denoted as DAV.

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

ANALOG MUX INPUT RESISTANCE

SUPPLY CURRENT

FREE AIR TEMPERATURE

INPUT CHANNEL NUMBER

700

600

500

400

300

200

100

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

= DV

= 5 V

= DV

= 3 V

= DV

= 2.7 V

= DV

= 5 V

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

Input Channel Number

– Free Air Temperature – °C

Figure 11

Figure 12

ANALOG INPUT BANDWIDTH

SUPPLY CURRENT

FREQUENCY

CLOCK FREQUENCY

= DV

= 5 V

–1

–2

–3

= DV

= 5 V,

= DV

= 3 V

–4

AIN = 90% of FS,

REF = 5 V,

–5

–6

= 25°C

0.1

100

10 12 14 16 18 20

f – Frequency – MHz

– Clock Frequency – MHz

clock

Figure 13

Figure 14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODE

1.0

0.5

0.0

External Ref = 3 V,

= DV

= 3 V,

–0.5

–1.0

CLK = 10 MHz,

= 25°C

1023

256

512

768

Digital Output Code

Figure 15

INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODE

1.0

0.5

External Ref = 3 V,

= DV

= 3 V,

CLK = 10 MHz,

= 25°C

0.0

–0.5

–1.0

1023

256

512

768

Digital Output Code

Figure 16

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TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

DIGITAL OUTPUT CODE

1.0

0.5

0.0

External Ref = 5 V,

= DV

= 5 V,

–0.5

–1.0

CLK = 20 MHz,

= 25°C

1023

256

512

768

Digital Output Code

Figure 17

INTEGRAL NONLINEARITY

DIGITAL OUTPUT CODE

1.0

0.5

0.0

External Ref = 5 V,

= DV

= 5 V,

–0.5

–1.0

CLK = 20 MHz,

= 25°C

1023

256

512

768

Digital Output Code

Figure 18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

FREQUENCY

= DV

= 3 V,

External Ref = 3 V

100

150

200

250

f – Frequency – kHz

Figure 19

EFFECTIVE NUMBER OF BITS

FREQUENCY

= DV

= 5 V,

External Ref = 5 V

50 100 150 200 250 300 350 400 450 500

f – Frequency – kHz

Figure 20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM

FREQUENCY

–20

AIN = 200 KHz

CLK = 10 MHz

= DV

= 3 V

External Ref = 3 V

–40

–60

–80

–100

–120

100

125

150

175

200

225

250

275

f – Frequency – kHz

Figure 21

FAST FOURIER TRANSFORM

FREQUENCY

–20

AIN = 200 KHz

CLK = 20 MHz

External Ref = 5 V

= DV

= 5 V

–40

–60

–80

–100

–120

100

150

200

250

300

350

400

450

500

550

f – Frequency – kHz

Figure 22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

MECHANICAL DATA

DA (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

0,30

0,19

0,13

0,65

6,20

8,40

NOM 7,80

0,15 NOM

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

DIM

9,80

9,60

11,10

10,90

11,10

12,60

12,40

A MAX

A MIN

10,90

4040066/D 11/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.419 (10,65)

0.400 (10,15)

0.010 (0,25) NOM

0.299 (7,59)

0.293 (7,45)

Gage Plane

0.010 (0,25)

0°–8°

0.050 (1,27)

0.016 (0,40)

Seating Plane

0.004 (0,10)

0.012 (0,30)

0.004 (0,10)

0.104 (2,65) MAX

PINS **

0.710

DIM

0.410

0.510

0.610

A MAX

A MIN

(10,41) (12,95) (15,49) (18,03)

0.400

0.500

0.600

0.700

(10,16) (12,70) (15,24) (17,78)

4040000/C 07/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

TLV1571CPW [TI]

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