TLV1812 [TI]
双路微功耗高电压比较器;
| 型号： | TLV1812 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路微功耗高电压比较器 比较器 |
| 文件： | 总39页 (文件大小：1916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV1811, TLV1811L, TLV1821, TLV1821L, TLV1812, TLV1822
ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
TLV181x 和TLV182x 系列40V 轨至轨输入比较器，具有推挽或开漏输出选项
输入做出响应，从而防止系统上电和断电期间出现错误
输出。
1 特性
• 2.4V 至40V 宽电源电压范围
TLV181x 比较器具有推挽式输出级，能够灌/拉毫安级
• 轨至轨输入
电流，同时可对 LED 进行控制或驱动容性负载（例如
• 已知启动的上电复位(POR)
MOSFET 栅极）。
• 低输入失调电压500µV
TLV182x 比较器具有开漏输出级，可在独立于比较器
电源电压的情况下上拉至40V。
• 420ns 典型传播延迟
• 每通道的低静态电流为5μA
• 低输入偏置电流150fA
• 开漏输出选项(TLV182x)
• 推挽输出选项(TLV181x)
• -40°C 到+125°C 的完整温度范围
• 2kV ESD 保护
器件信息
封装(1)
封装尺寸（标称值）
1.25mm x 2.00mm
1.60mm x 2.90mm
器件型号
TLV1811、
TLV1821
（单通道）
SC-70 (6)
SOT-23 (5)
SC-70 (5)
• 功能安全型
1.25mm x 2.00mm
1.60mm x 2.90mm
TLV1811L、
TLV1821L
– 有助于进行功能安全系统设计的文档
（单通道- 交替引脚
排列）
SOT-23 (5)
2 应用
SOIC (8)
3.91mm × 4.90mm
3.00mm × 4.40mm
3.00mm × 3.00mm
2.00mm × 2.00mm
1.60mm × 2.90mm
3.91mm × 8.65mm
4.40mm × 5.00mm
4.20mm x 2.00mm
• 电器
TSSOP (8)（预览）
VSSOP (8)（预发布）
WSON (8)（预发布）
SOT-23 (8)（预发布）
SOIC (14)（预览）
TSSOP (14)（预览）
• 工厂自动化和控制
• 电机驱动器
• 信息娱乐系统与仪表组
TLV1812，
TLV1822
（双通道）
3 说明
TLV181x 和TLV182x 是一个40V 单通道、双通道和四
通道比较器系列，具有多个输出选项。该系列提供具有
推挽或开漏输出选项的轨至轨输入。该系列具有出色的
速度功率组合，传播延迟为420ns，整个电源电压范围
为 2.4V 至 40V，每个通道的静态电源电流仅为
5μA。
TLV1814、
TLV1824
（四通道）
SOT-23 (14)（预发
布）
3.00mm × 3.00mm
WQFN (16)（预发布）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
所有器件都包含上电复位 (POR) 功能。这可确保输出
处于已知状态，直到达到最小电源电压，然后输出才对
V+
V+
V+
V+
*
*
IN+
IN-
+
-
Output
Control
OUT
V+
ESD
CLAMPS
Power
Clamp
V-
V-
V-
V-
Power-On
Reset
Bias
* Push-Pull
Version Only
V-
TLV18xx 方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDC8
TLV1811, TLV1811L, TLV1821, TLV1821L, TLV1812, TLV1822
ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
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Table of Contents
8.1 Overview...................................................................13
8.2 Functional Block Diagrams....................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................16
9.1 Application Information............................................. 16
9.2 Typical Applications.................................................. 19
9.3 Power Supply Recommendations.............................26
9.4 Layout....................................................................... 26
10 Device and Documentation Support..........................28
10.1 Documentation Support.......................................... 28
10.2 接收文档更新通知................................................... 28
10.3 支持资源..................................................................28
10.4 Trademarks.............................................................28
10.5 Electrostatic Discharge Caution..............................28
10.6 术语表..................................................................... 28
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions: TLV18x1 and TLV18x1L............................3
Pin Functions: TLV1812 and TLV1822..............................4
Pin Functions: TLV1814 and TLV1824..............................5
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information - Single.......................................7
6.5 Thermal Information - Dual......................................... 7
6.6 Thermal Information - Quad........................................7
6.7 Electrical Characteristics.............................................8
6.8 Switching Characteristics............................................9
7 Typical Characteristics................................................. 10
8 Detailed Description......................................................13
Information.................................................................... 28
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (November 2022) to Revision B (December 2022)
Page
• 商用TLV1811/21 单版本.....................................................................................................................................1
Changes from Revision * (September 2022) to Revision A (November 2022)
Page
• 商用TLV1812/22 双版本.....................................................................................................................................1
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ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
5 Pin Configuration and Functions
Pin Functions: TLV18x1 and TLV18x1L
OUT
V-
1
2
3
5
4
V+
IN-
IN+
TLV1811 and TLV1821
Standard "North West" pinout
DBV, DCK Packages,
SOT-23-5, SC-70-5
Top View
OUT
V+
1
2
3
5
4
V-
IN+
IN-
TLV1811L and TLV1821L DBV Package,
"LMC72x1/TLV72x1 type" pinout with reversed supplies
SOT-23-5,
Top View
OUT
V+
1
2
3
6
5
4
N/C
V-
IN+
IN-
TLV1811L and TLV1821L DCK Package,
"TLV72x1 6-pin type" pinout with reversed supplies and shifted V-
SC-70-6,
Top View
表5-1. Pin Functions: TLV1811, TLV1821, TLV1811L and TLV1821L
TLV1811, TLV1821
TLV1811L, TLV1821L
PINS
PINS
NAME
I/O
DESCRIPTION
SOT-23
SC-70
SOT-23
SC-70
1
1
5
3
4
2
6
OUT
1
2
3
4
1
5
3
O
-
Output
V-
2
3
4
Negative Supply Voltage
Non-Inverting (+) Input
IN+
IN-
I
4
2
-
I
-
-
Inverting (-) Input
Positive Supply Voltage
No Connection
V+
5
-
5
-
N/C
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ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
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Pin Functions: TLV1812 and TLV1822
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
8
V+
OUT1
1
2
Exposed
Thermal
Die Pad
on
OUT2
IN2œ
IN2+
IN1œ
7
6
OUT2
IN2œ
IN1+
3
4
Underside
5
IN2+
Vœ
D, DGK, PW, DDF Packages
8-Pin SOIC, VSSOP, TSSOP, SOT-23-8
Top View
NOTE: Connect exposed thermal pad directly to V- pin.
DSG Package,
8-Pad WSON With Exposed Thermal Pad,
Top View
表5-2. Pin Functions: TLV1812 and TLV1822
PIN
I/O
DESCRIPTION
NAME
OUT1
NO.
1
O
I
Output pin of the comparator 1
2
Inverting input pin of comparator 1
Noninverting input pin of comparator 1
Negative (low) supply
IN1–
IN1+
3
I
V-
4
—
IN2+
5
I
Noninverting input pin of comparator 2
Inverting input pin of comparator 2
Output pin of the comparator 2
Positive supply
6
I
IN2–
OUT2
V+
7
O
—
—
8
Thermal Pad
Connect directly to V- pin
—
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ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
Pin Functions: TLV1814 and TLV1824
OUT2
OUT1
V+
1
2
3
4
5
6
7
14 OUT3
OUT4
Vœ
13
12
11
10
9
V+
IN1œ
NC
1
2
3
4
12
11
10
9
Vœ
IN4+
NC
IN1œ
IN1+
IN4+
IN4œ
Thermal
Pad
IN1+
IN4œ
IN2œ
IN3+
IN2+
IN3œ
8
Not to scale
D, PW, DYY Package, 14-Pin SOIC, TSSOP, SOT-23,
Top View
NOTE: Connect exposed thermal pad directly to V- pin.
RTE Package, 16-Pad WQFN With Exposed
Thermal Pad, Top View
表5-3. Pin Functions: TLV1814 and TLV1824
PIN
SOIC
I/O
DESCRIPTION
NAME
OUT2(1)
WQFN
1
2
3
15
16
1
O
O
Output pin of the comparator 2
OUT1(1)
V+
Output pin of the comparator1
Positive supply
—
I
4
5
2
4
Negative input pin of the comparator 1
Positive input pin of the comparator 1
Negative input pin of the comparator 2
Positive input pin of the comparator 2
Negative input pin of the comparator 3
Positive input pin of the comparator 3
Negative input pin of the comparator 4
Positive input pin of the comparator 4
Negative supply
IN1–
IN1+
I
6
5
I
IN2–
IN2+
7
6
I
8
7
I
IN3–
IN3+
9
8
I
10
11
12
13
14
—
—
—
9
I
IN4–
IN4+
11
12
13
14
3
I
V-
—
O
O
OUT4
OUT3
NC
Output pin of the comparator 4
Output pin of the comparator 3
No Internal Connection - Leave floating or GND
No Internal Connection - Leave floating or GND
Connect directly to V- pin.
—
—
—
NC
10
PAD
Thermal Pad
(1) Some manufacturers transpose the names of channels 1 and 2. Electrically the pinouts are identical, just a difference in channel
naming convention.
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ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–10
–0.3
–0.3
-10
MAX
42
UNIT
V
Supply voltage: VS = (V+) –(V–)
Input pins (IN+, IN–) from (V–), Rail-to-Rail Input(2)
Current into Input pins (IN+, IN–)
Output (OUT) voltage (Open-Drain) from (V–)(3)
Output (OUT) voltage (Push-Pull) from (V–)
Output (OUT) current (4) (5) (6)
(V+) + 0.3
10
V
mA
V
42
(V+) + 0.3
10
V
mA
°C
°C
Junction temperature, TJ
150
Storage temperature, Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input terminals are diode-clamped to (V–). Inputs (IN+, IN–) can be greater than (V+) and OUT as long as it is within the –0.3 V to
42 V range
(3) Output (OUT) for open drain can be greater than (V+) and inputs (IN+, IN–) as long as it is within the –0.3 V to 42 V range
(4) The output is diode-clamped to (V-) for both output options, and diode clamped to (V+) for the push-pull output option. The open drain
version does not have a clamp to V+. Please see the Outputs and ESD Protection section of the Application Information Section for
more information.
(5) Output sinking and sourcing current is internally limited to <35mA when operating within the Absolute Maximum output voltage limits.
The Absoulute Maximum Output Current limit specified here is the maximum current through the clamp structure when exceeding the
supply votlage below (V-) for both output options, or above (V+) for the push-pull option.
(6) Short-circuit from output to (V–) or (V+). Continuous output short circuits at elevated supply voltages can result in excessive heating
and exceeding the maximum allowed junction temperature, leading to eventual device destruction.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.4
MAX
UNIT
40
(V+) + 0.2
40
V
V
Supply voltage: VS = (V+) –(V–)
Input voltage range from (V–)
–0.2
–0.2
–0.2
–40
Open Drain
Push Pull
V
Output voltage range from (V–)
(V+) + 0.2
125
V
Ambient temperature, TA
°C
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6.4 Thermal Information - Single
TLV18x1 and TLV18x1L
DCK
(SC-70)
DCK
DBV
THERMAL METRIC(1)
UNIT
(SC-70) (SOT-23)
5 PINS
6 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
226.6
185.6
203.4
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
129.5
78.6
51.5
78.3
–
137.6
76.5
59.8
76.2
–
105.4
106.6
54.0
106
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
°C/W
°C/W
ψJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
–
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.
6.5 Thermal Information - Dual
TLV18x2
D
PW
DDF
DSG
(WSON)
DGK
(VSSOP)
THERMAL METRIC(1)
UNIT
(SOIC) (TSSOP) (SOT-23)
8 PINS
136.1
76.8
8 PINS
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
79.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
26.8
ψJT
78.9
ψJB
RθJC(bot)
–
–
–
–
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.
6.6 Thermal Information - Quad
TLV18x4
D
PW
DDF
DSG
(WQFN)
DGK
(VSSOP)
THERMAL METRIC(1)
UNIT
(SOIC)
(TSSOP) (SOT-23)
14 PINS
14 PINS
14 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
104.2
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
60.3
60.2
20.7
59.8
–
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
°C/W
°C/W
ψJB
RθJC(bot)
–
–
–
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.
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6.7 Electrical Characteristics
For VS (Total Supply Votlage) = (V+) –(V–) = 12 V, VCM = VS / 2 at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.5
3
4
mV
mV
–3
–4
VOS
Input offset voltage
TA = –40°C to +125°C
Input offset voltage
drift
dVIO/dT
PSRR
±1.2
100
µV/°C
dB
TA = –40°C to +125°C
Power supply rejection
ratio
VS = 2.4 V to 40 V, VCM = (V–)
POWER SUPPLY
Output Low, TA = 25°C
TLV1811 Only
6
8
7.5
8.5
10
Output Low, TA = –40°C to +125°C
TLV1811 Only
Quiescent current, No
Load
IQ
µA
Output High, TA = 25°C
TLV1811 Only
Output High, TA = –40°C to +125°C
TLV1811 Only
11
Output Low, TA = 25°C
5
7
6.5
7.5
9
Output Low, TA = –40°C to +125°C
Output High, TA = 25°C
Quiescent current per
comparator, No Load
IQ
µA
V
10
Output High, TA = –40°C to +125°C
Power On Reset
Voltage
VPOR
1.7
INPUT BIAS CURRENT
150
10
fA
nA
fA
IB
Input bias current (1)
Input offset current (1)
1.2
TA = –40°C to +125°C
–1.2
IOS
INPUT CAPACITANCE
Input Capacitance,
Differential
CID
CIC
2
8
pF
pF
Input Capacitance,
Common Mode
INPUT COMMON MODE RANGE
VS = 2.4 V to 40 V
TA = –40°C to +125°C, Rail to Rail
Common-mode
VCM-Range
(V+) + 0.2
V
(V–) –0.2
voltage range
OUTPUT
Voltage swing from
(V–)
ISINK = 4 mA
TA = –40°C to +125°C
VOL
250
250
mV
mV
nA
Voltage swing from
(V+) (for Push-
Pull only)
ISOURCE = 4 mA
TA = –40°C to +125°C
VOH
VID = +0.1 V, VPULLUP = (V+)
TA = –40°C to +125°C
Open-drain output
leakage current
ILKG
0.1
IOL
IOH
Short-circuit current
Short-circuit current
Sinking
15
15
30
30
mA
mA
Sourcing (for Push-Pull only)
(1) This parameter is ensured by design and/or characterization and is not tested in production .
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6.8 Switching Characteristics
For VS (Total Supply Voltage) = (V+) –(V–) = 12 V, VCM = VS / 2 at TA = 25°C (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Propagation delay time, high-
to-low
ns
ns
TPD-HL
VOD = 10 mV, CL = 50 pF
900
450
900
420
15
Propagation delay time, high-
to-low
TPD-HL
TPD-LH
TPD-LH
TRISE
VOD = 100 mV, CL = 50 pF
VOD = 10 mV, CL = 50 pF
VOD = 100 mV, CL = 50 pF
CL = 50 pF
Propagation delay time, low-to-
high, push-pull output
ns
ns
Propagation delay time, low-to-
high, push-pull output
Output Rise Time, 20% to
80%, push-pull output
ns
TFALL
Output Fall Time, 80% to 20% CL = 50 pF
Toggle Frequency VID = 100 mV, CL = 50 pF
15
ns
FTOGGLE
500
kHz
POWER ON TIME
PON
Power on-time
200
µs
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7 Typical Characteristics
TA = 25°C, VS = 12 V, RPULLUP = 2.5k, CL = 20pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise
noted.
8.0
125°C
25°C
-40°C
Output High
No Load
7.5
7.0
6.5
6.0
0
4
8
12
16
20
24
28
32
36
40
Supply Voltage (V)
图7-1. Supply Current per Channel vs. Supply Votlage, Output
图7-2. Supply Current per Channel vs. Supply Votlage, Output
Low
High
10
VS = 2.4 V
P-P Output Only
1
100m
10m
125°C
25°C
-40°C
1m
10
100
1m
10m
100m
Output Sourcing Current (A)
图7-3. Output Voltage vs. Output Sinking Current, 2.4 V
图7-4. Output Voltage vs. Output Sourcing Current, 2.4 V
10
10
VS = 5 V
VS = 5 V
P-P Output Only
1
100m
10m
1
100m
10m
125°C
125°C
25°C
25°C
-40°C
-40°C
1m
10
1m
10
100
1m
10m
100m
100
1m
10m
100m
Output Sinking Current (A)
Output Sourcing Current (A)
图7-5. Output Voltage vs. Output Sinking Current, 5 V
图7-6. Output Voltage vs. Output Sourcing Current, 5 V
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7 Typical Characteristics (continued)
TA = 25°C, VS = 12 V, RPULLUP = 2.5k, CL = 20pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise
noted.
10
1
VS = 12 V
P-P Output Only
100m
10m
1m
125°C
25°C
-40°C
10
100
1m
10m
100m
Output Sourcing Current (A)
图7-7. Output Voltage vs. Output Sinking Current, 12 V
图7-8. Output Voltage vs. Output Sourcing Current, 12 V
VS = 40 V
10
VS = 40 V
P-P Output Only
10
1
1
100m
100m
10m
1m
10m
125°C
25°C
-40°C
125°C
25°C
-40°C
1m
10
100
1m
10m
100m
10
100
1m
10m
100m
Output Sinking Current (A)
Output Sourcing Current (A)
图7-9. Output Voltage vs. Output Sinking Current, 40 V
图7-10. Output Voltage vs. Output Sourcing Current, 40 V
1000
1000
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
VS = 2.4V
VCM = VS/2
CL = 20pF
VS = 2.4V
VCM = VS/2
CL = 20pF
900
800
700
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
10
20 30 40 50 70 100
200 300 500 700 1000
10
20 30 40 50 70 100
200 300 500 700 1000
Input Overdrive (mV)
Input Overdrive (mV)
图7-11. Propagation Delay, High to Low, 2.4V
图7-12. Propagation Delay, Low to High, 2.4V
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7 Typical Characteristics (continued)
TA = 25°C, VS = 12 V, RPULLUP = 2.5k, CL = 20pF, VCM = 0 V, VUNDERDRIVE = 100 mV, VOVERDRIVE = 100 mV unless otherwise
noted.
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
VS = 5V
VCM = VS/2
CL = 20pF
VS = 5V
VCM = VS/2
CL = 20pF
10
20 30 40 50 70 100
200 300 500 700 1000
10
20 30 40 50 70 100
200 300 500 700 1000
Input Overdrive (mV)
Input Overdrive (mV)
图7-13. Propagation Delay, High to Low, 5V
图7-14. Propagation Delay, Low to High, 5V
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
125°C
85°C
25°C
-40°C
125°C
85°C
25°C
-40°C
VS = 12V
VCM = VS/2
CL = 20pF
VS = 12V
VCM = VS/2
CL = 20pF
10
20 30 40 50 70 100
200 300 500 700 1000
10
20 30 40 50 70 100
200 300 500 700 1000
Input Overdrive (mV)
Input Overdrive (mV)
图7-15. Propagation Delay, High to Low, 12V
图7-16. Propagation Delay, Low to High, 12V
1000
900
800
700
600
500
400
300
200
100
0
125°C
VS = 40V
VCM = VS/2
CL = 20pF
85°C
25°C
-40°C
10
20 30 40 50 70 100
200 300 500 700 1000
Input Overdrive (mV)
图7-17. Propagation Delay, High to Low, 40V
图7-18. Propagation Delay, Low to High, 40V
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8 Detailed Description
8.1 Overview
The TLV181x and TLV182x devices are micro-power comparators with push-pull and open-drain output options.
Operating down to 2.4 V while only consuming only 5 µA per channel, the TLV181x and TLV182x are well suited
for portable, automotive and industrial applications. An internal power-on reset circuit ensures that the output
remains in a known state during power-up and power-down.
8.2 Functional Block Diagrams
V+
V+
V+
V+
*
*
IN+
IN-
+
-
Output
Control
OUT
V+
ESD
CLAMPS
Power
Clamp
V-
V-
V-
V-
Power-On
Reset
Bias
* Push-Pull
Version Only
V-
图8-1. TLV18xx Block Diagram
8.3 Feature Description
TLV18xx Family Options
The TLV18xxy family consists of several output and pinout options, all featuring 40 V operation, micro-power 5
µA supply currents, 420 ns propagation delay, and a Power-On Reset (POR) function.
The TLV18xx family has two output options:
The TLV181x has a push-pull (sink-source) output.
The TLV182x has a open-drain (sink only) output, capable of being pulled-up to any voltage up to 40 V,
independent of comparator supply voltage.
The TLV1811L and TLV1821L are alternate pinouts of the TLV1811 and TLV1821 that allow upgrading older
devices such as the TLV7211, TLV7221, LMC7211 and LMC7221 family.
8.4 Device Functional Modes
8.4.1 Inputs
8.4.1.1 TLV18xx Rail-to-Rail Input
The TLV18xx input voltage range extends from 200 mV below V- to 200 mV above V+. The differential input
voltage (VID) may be any voltage within these limits. No phase-inversion of the comparator output will occur
when the input voltages stay within the specified range.
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The Rail-to-Rail input does have an ESD clamp to the V+supply line and therefore the input voltage must not
exceed the supply voltages by more than 200mV. It is not recommended to apply signals to the rail to rail inputs
with no supply voltage.
8.4.1.2 ESD Protection
The TLV181x open-drain output ESD protection consists of a snapback ESD clamp between the output and V- to
allow the output to be pulled above V+ to a maximum of 40 V. There is no "upper" ESD clamp diode between the
output and V+ on the open-drain output. There is a "lower" clamp between V- and the output.
The TLV182x push-pull output ESD protection contains a conventional diode-type "upper" ESD clamp between
the output and V+, and a "lower" ESD clamp between the output and V-. The output must not exceed the supply
rails by more than 200mV.
If the inputs are to be connected to a low impedance source, such as a power supply or buffered reference line,
TI recommends adding a current-limiting resistor in series with the input to limit any currents when the clamps
conduct. The current must be limited 10 mA or less, though TI recommends limitng the current to 1mA or less.
This series resistance may be part of any resistive input dividers or networks.
8.4.1.3 Unused Inputs
If a channel is not to be used, DO NOT tie the inputs together. Due to the high equivalent bandwidth and low
offset voltage, tying the inputs directly together may cause high frequency chatter as the device triggers on it's
own internal wideband noise. Instead, the inputs must be tied to any available voltage that resides within the
specified input voltage range and provides a minimum of 50 mV differential voltage. For example, one input can
be grounded and the other input connected to a reference voltage, or even V+ (as long as the input is directly
connected to the V+ pin to avoid transients).
8.4.2 Outputs
8.4.2.1 TLV181x Push-Pull Output
The TLV181x features a push-pull output stage capable of both sinking and sourcing current. This allows driving
loads such as LED's and MOSFET gates, as well as eliminating the need for a power-wasting external pull-up
resistor. The push-pull output must never be connected to another output.
Directly shorting the output to the opposite supply rail (V+ when output "low" or V- when output "High") can result
in thermal runaway and eventual device destruction at high (>12 V) supply voltages. If output shorts are
possible, a series current limiting resistor is recommended to limit the power dissipation.
Unused push-pull outputs mustbe left floating, and never tied to a supply, ground, or another output.
8.4.2.2 TLV182x Open-Drain Output
The TLV182x features an open-drain (also commonly called open collector) sinking-only output stage enabling
the output logic levels to be pulled up to an external voltage from 0 V up to 40 V, independent of the comparator
supply voltage (V+). The open-drain output allows logical OR'ing of multiple open drain outputs and logic level
translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower value pull-up
resistor values will help increase the rising edge rise-time, but at the expense of increasing VOL and higher
power dissipation. The rise-time is dependent on the time constant of the total pull-up resistance and total load
capacitance. Large value pull-up resistors (>1 MΩ) will create an exponential rising edge due to the output RC
time constant and increase the rise-time.
Directly shorting the output to V+ can result in thermal runaway and eventual device destruction at high (>12 V)
pull-up voltages. If output shorts are possible, a series current limiting resistor is recommended to limit the power
dissipation.
Unused open drain outputs may be left floating, or may be tied to the V- pin if floating pins are not desired.
8.4.3 Power-On Reset (POR)
The TLV18xx family has an internal Power-on-Reset (POR) circuit for known start-up or power-down conditions.
While the power supply (V+) is ramping up or ramping down, the POR circuitry will be activated for up to 200µs
after the minimum supply voltage threshold of 2.4 V is crossed, or immediately when the supply voltage drops
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below 2.4 V. When the supply voltage is equal to or greater than the minimum supply voltage, and after the delay
period, the comparator output reflects the state of the differential input (VID).
For the TLV181x push-pull output devices, the output is held low during the POR period (ton).
For the TLV182x open drain output option the POR circuit will keep the output high impedance (Hi-Z) during the
POR period (ton).
tON
V-
(V-) + 2.4V
V+
VOH/2
V-
OUT
图8-2. Power-On Reset Timing Diagram
Note that it the nature of an open collector output that the output will rise with the pull-up voltage during the POR
period.
8.4.4 Hysteresis
The TLV18xx family does not have internal hysteresis. Due to the wide effective bandwidth and low input offset
voltage, it is possible for the output to "chatter" when the absolute differential voltage is near zero as the
comparator triggers on it's own internal wideband noise. This is normal comparator behavior and is expected. TI
recommends that the user add external hysteresis if slow moving signals are expected. See 节 9.1.2 in the
following section.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 Basic Comparator Definitions
9.1.1.1 Operation
The basic comparator compares the input voltage (VIN) on one input to a reference voltage (VREF) on the other
input. In the 图 9-1 example below, if VIN is less than VREF, the output voltage (VO) is logic low (VOL). If VIN is
greater than VREF, the output voltage (VO) is at logic high (VOH). 表 9-1 summarizes the output conditions. The
output logic can be inverted by simply swapping the input pins.
表9-1. Output Conditions
Inputs Condition
IN+ > IN-
Output
HIGH (VOH
)
IN+ = IN-
Indeterminate (chatters - see Hysteresis)
LOW (VOL
IN+ < IN-
)
9.1.1.2 Propagation Delay
There is a delay between from when the input crosses the reference voltage and the output responds. This is
called the Propagation Delay. Propagation delay can be different between high-to low and low-to-high input
transitions. This is shown as tpLH and tpHL in 图 9-1 and is measured from the mid-point of the input to the
midpoint of the output.
图9-1. Comparator Timing Diagram
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9.1.1.3 Overdrive Voltage
The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input
peak-to-peak voltage). The overdrive voltage is 100 mV as shown in the 图 9-1 example. The overdrive voltage
can influence the propagation delay (tp). The smaller the overdrive voltage, the longer the propagation delay,
particularly when <100mV. If the fastest speeds are desired, it is recommended to apply the highest amount of
overdrive possible.
The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.
9.1.2 Hysteresis
The basic comparator configuration may oscillate or produce a noisy "chatter" output if the applied differential
input voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very
slowly across the switching threshold of the comparator.
This problem can be prevented by the addition of hysteresis or positive feedback.
The hysteresis transfer curve is shown in 图 9-2. This curve is a function of three components: VTH, VOS, and
VHYST
:
• VTH is the actual set voltage or threshold trip voltage.
• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip
point at which the comparator must respond to change output states.
• VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.
V
+ V œ (V
/ 2)
V
TH
+ V
V
+ V + (V
OS
/ 2)
TH
OS
HYST
OS
TH
HYST
图9-2. Hysteresis Transfer Curve
For more information, please see Application Note SBOA219 "Comparator with and without hysteresis circuit".
9.1.2.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator
supply voltage (VCC), as shown in 图9-3.
+V
CC
+5 V
R
1
1 MΩ
5 V
0 V
V
IN
œ
V
O
V
O
V
A
+
V
A2
V
A1
1.67 V
3.33 V
V
IN
R
3
R
2
1 MΩ
1 MΩ
图9-3. TLV181xin an Inverting Configuration With Hysteresis
The equivalent resistor networks when the output is high and low are shown in 图9-3.
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V
High
V Low
O
O
+V
+V
CC
CC
R
R
R
1
1
3
V
A1
V
A2
R
3
R
R
2
2
图9-4. Inverting Configuration Resistor Equivalent Networks
When VIN is less than VA, the output voltage is high (for simplicity, assume VO switches as high as VCC). The
three network resistors can be represented as R1 || R3 in series with R2, as shown in 图9-4.
方程式1 below defines the high-to-low trip voltage (VA1).
R2
VA1 = VCC
´
(R1 || R3) + R2
(1)
When VIN is greater than VA, the output voltage is low. In this case, the three network resistors can be presented
as R2 || R3 in series with R1, as shown in 方程式2.
Use 方程式2 to define the low to high trip voltage (VA2).
R2 || R3
VA2 = VCC
´
R1 + (R2 || R3)
(2)
(3)
方程式3 defines the total hysteresis provided by the network.
DVA = VA1 - VA2
9.1.2.2 Non-Inverting Comparator With Hysteresis
A non-inverting comparator with hysteresis requires a two-resistor network and a voltage reference (VREF) at the
inverting input, as shown in 图9-5,
5 V
V
œ
REF 2.5 V
V
O
V
O
V
A
V
+
IN
V
V
IN2
IN1
R
0 V
1
1.675 V
3.325 V
330 kΩ
V
IN
R
2
1 MΩ
图9-5. TLV181x in a Non-Inverting Configuration With Hysteresis
The equivalent resistor networks when the output is high and low are shown in 图9-6.
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V
Low
IN1
V
High
O
O
+V
+V
CC
R
R
R
R
2
1
V
A
= V
V
= V
A REF
REF
1
2
V
IN2
图9-6. Non-Inverting Configuration Resistor Networks
When VIN is less than VREF,, the output is low. For the output to switch from low to high, VIN must rise above the
V
IN1 threshold. Use 方程式4 to calculate VIN1.
VREF
VIN1 = R1 ´
+ VREF
R2
(4)
When VIN is greater than VREF, the output is high. For the comparator to switch back to a low state, VIN must
drop below VIN2. Use 方程式5 to calculate VIN2
.
VREF (R1 + R2) - VCC ´ R1
VIN2
=
R2
(5)
(6)
The hysteresis of this circuit is the difference between VIN1 and VIN2, as shown in 方程式6.
R1
DVIN = VCC
´
R2
For more information, please see Application Notes SNOA997 "Inverting comparator with hysteresis circuit" and
SBOA313 "Non-Inverting Comparator With Hysteresis Circuit".
9.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
It is also possible to use an open drain output device, such as the TLV182x, but the output pull-up resistor must
also be taken into account in the calculations. The pull-up resistor is seen in series with the feedback resistor
when the output is high. Thus, the feedback resistor is actually seen as R2 + RPULLUP. TI recommends that the
pull-up resistor be at least 10 times less than the feedback resistor value.
9.2 Typical Applications
9.2.1 Window Comparator
Window comparators are commonly used to detect undervoltage and overvoltage conditions. 图 9-7 shows a
simple window comparator circuit. Window comparators require open drain outputs (TLV182x) if the outputs are
directly connected together.
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3.3 V
RPU
R
1
Low when V > V
IN
TH+
10 MΩ
UV_OV
+
V
TH+
Micro-
Controller
œ
Sensor
Open Drain Output Only!
V
IN
R
2
10 MΩ
Low when V < V
IN
TH-
+
Output high
when V is
IN
œ
V
TH-
within window
R
3
Open Drain Output Only!
10 MΩ
图9-7. Window Comparator
9.2.1.1 Design Requirements
For this design, follow these design requirements:
• Alert (logic low output) when an input signal is less than 1.1 V
• Alert (logic low output) when an input signal is greater than 2.2 V
• Alert signal is active low
• Operate from a 3.3-V power supply
9.2.1.2 Detailed Design Procedure
Configure the circuit as shown in 图 9-7. Connect VCC to a 3.3-V power supply and VEE to ground. Make R1, R2
and R3 each 10-MΩ resistors. These three resistors are used to create the positive and negative thresholds for
the window comparator (VTH+ and VTH–).
With each resistor being equal, VTH+ is 2.2 V and VTH- is 1.1 V. Large resistor values such as 10-MΩare used to
minimize power consumption. The resistor values may be recalculated to provide the desired trip point values.
The sensor output voltage is applied to the inverting and noninverting inputs of the two comparators. Using two
open-drain output comparators allows the two comparator outputs to be Wire-OR'ed together.
The respective comparator outputs will be low when the sensor is less than 1.1 V or greater than 2.2 V. The
respective comparator outputs will be high when the sensor is in the range of 1.1 V to 2.2 V (within the
"window"), as shown in 图9-8.
9.2.1.3 Application Curve
V
IN
V + = 2.2 V
TH
V
= 1.1 V
THœ
OUT
图9-8. Window Comparator Results
For more information, please see Application note SBOA221 "Window comparator circuit".
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9.2.2 Square-Wave Oscillator
Square-wave oscillator can be used as low cost timing reference or system supervisory clock source. A push-
pull output (TLV181x) is recommended for best symmetry.
R4
100 kΩ
t
C1
100 pF
1
+
V
V
C
œ
OUT
0
t
2
+
R1
100 kΩ
R3
100 kΩ
V
A
V
CC
R2
100 kΩ
图9-9. Square-Wave Oscillator
9.2.2.1 Design Requirements
The square-wave period is determined by the RC time constant of the capacitor C1 and resistor R4. The
maximum frequency is limited by propagation delay of the device and the capacitance load at the output. The
low input bias current allows a lower capacitor value and larger resistor value combination for a given oscillator
frequency, which may help to reduce BOM cost and board space. TI recommends that R4 be over several kilo-
ohms to minimize loading of the output.
9.2.2.2 Detailed Design Procedure
The oscillation frequency is determined by the resistor and capacitor values. The following calculation provides
details of the steps.
图9-10. Square-Wave Oscillator Timing Thresholds
First consider the output of Figure 图 9-9 as high, which indicates the inverted input VC is lower than the
noninverting input (VA). This causes the C1 to be charged through R4, and the voltage VC increases until it is
equal to the noninverting input. The value of VA at the point is calculated by 方程式7.
VCCìR2
R2 + R1IIR3
VA1
=
(7)
if R1 = R2= R3, then VA1 = 2 VCC/ 3
At this time the comparator output trips pulling down the output to the negative rail. The value of VAat this point is
calculated by 方程式8.
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VCC(R2IIR3 )
VA2
=
R1+R2IIR3
(8)
if R1 = R2 = R3, then VA2 = VCC/3
The C1 now discharges though the R4, and the voltage VCC decreases until it reaches VA2. At this point, the
output switches back to the starting state. The oscillation period equals to the time duration from for C1 from
2VCC/3 to VCC / 3 then back to 2VCC/3, which is given by R4C1 × ln 2 for each trip. Therefore, the total time
duration is calculated as 2 R4C1 × ln 2.
The oscillation frequency can be obtained by 方程式9:
f = 1/ 2 R4ìC1ìIn2
(9)
9.2.2.3 Application Curve
图9-11 shows the simulated results of an oscillator using the following component values:
• R1 = R2 = R3 = R4 = 100 kΩ
• C1 = 100 pF, CL = 20 pF
• V+ = 5 V, V–= GND
• Cstray (not shown) from VA TO GND = 10 pF
图9-11. Square-Wave Oscillator Output Waveform
9.2.3 Adjustable Pulse Width Generator
图9-12 is a variation on the square wave oscillator that allows adjusting the pulse widths.
R4 and R5 provide separate charge and discharge paths for the capacitor C depending on the output state.
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ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
R4
1 MΩ
D1
R5
100 kΩ
D2
t
C1
100 pF
1
+
V
V
V
C
œ
OUT
0
t
2
+
R1
100 kΩ
R3
100 kΩ
A
V
CC
R2
100 kΩ
图9-12. Adjustable Pulse Width Generator
The charge path is set through R5 and D2 when the output is high. Similarly, the discharge path for the capacitor
is set by R4 and D1 when the output is low.
The pulse width t1 is determined by the RC time constant of R5 and C. Thus, the time t2 between the pulses can
be changed by varying R4, and the pulse width can be altered by R5. The frequency of the output can be
changed by varying both R4 and R5. At low voltages, the effects of the diode forward drop (0.8 V, or 0.15 V for
Shottky) must be taken into account by altering output high and low voltages in the calculations.
9.2.4 Time Delay Generator
The circuit shown in 图 9-13 provides output signals at a prescribed time interval from a time reference and
automatically resets the output low when the input returns to 0 V. This is useful for sequencing a "power on"
signal to trigger a controlled start-up of power supplies.
+V
RPU not required if using
push-pull output devices
+V
LOGIC3
100 kΩ
10 MΩ
Open
Drain
Output
R
PU
R
100 kΩ
+
V
IN
V
10 kΩ
10 kΩ
10 kΩ
+
V
C
0
+
4
t
t4
0
œ
1
V
3
Input
Gating
Signal
œ
C
+V
LOGIC2
t
t
3
0
100 kΩ
51 kΩ
R
PU
10 MΩ
+
2
œ
V
2
V
V
3
+V
LOGIC1
t
t
2
0
2
51 kΩ
10 MΩ
R
PU
V
C
V
1
+
3
V
1
t
0
t
1
t
2
t
3
t
4
œ
t
t
1
0
51 kΩ
图9-13. Time Delay Generator
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Consider the case of VIN = 0. The output of comparator 4 is also at ground, "shorting" the capacitor and holding it
at 0V. This implies that the outputs of comparators 1, 2, and 3 are also at 0V. When an input signal is applied,
the output of open drain comparator 4 goes High-Z and C charges exponentially through R. This is indicated in
the graph. The output voltages of comparators 1, 2, and 3 switch to the high state in sequence when VC rises
above the reference voltages V1, V2 and V3. A small amount of hysteresis has been provided by the 10 kΩ and
10 MΩ resistors to insure fast switching when the RC time constant is chosen to give long delay times. A good
starting point is R = 100 kΩand C = 0.01 µF to 1 µF.
All outputs will immediately go low when VIN falls to 0V, due to the comparator output going low and immediately
discharging the capacitor.
Comparator 4 must be a open-drain type output (TLV182x), whereas comparators 1 though 3 may be either
open drain or push-pull output, depending on system requirements. RPU is not required for push-pull output
devices.
9.2.5 Logic Level Shifter
The output of the TLV182x is the uncommitted drain of the output transistor. Many open-drain outputs can be
tied together to provide an output OR'ing function if desired.
V
LOGIC
V
CC
Logic
In
V
CC
R
PULLUP
+
Logic
Out
0
œ
Open
Drain
Output
R1
V
CC
10 kΩ
V
R2
10 kΩ
LOGIC
0
图9-14. Universal Logic Level Shifter
The two 10 kΩ resistors bias the input to half of the input logic supply level to set the threshold in the mid-point
of the input logic levels. Only one shared output pull-up resistor is needed and may be connected to any pull-up
voltage between 0 V and 5.5 V. The pullup voltage should match the driven logic input "high" level.
9.2.6 One-Shot Multivibrator
+V
R1
C1
1 MΩ
100 pF
+V
IN
V
2
1
+V
0
œ
PW
R2
1 MΩ
+
D1
1N4148
t
0
C2
t
0
t
1
V
D2
1N4148
R4
图9-15. One-Shot Multivibrator
A monostable multivibrator has one stable state in which it can remain indefinitely. It can be triggered externally
to another quasi-stable state. A monostable multivibrator can thus be used to generate a pulse of desired width.
The desired pulse width is set by adjusting the values of C2 and R4. The resistor divider of R1 and R2 can be
used to determine the magnitude of the input trigger pulse. The output will change state when V1 < V2. Diode D2
provides a rapid discharge path for capacitor C2 to reset at the end of the pulse. The diode also prevents the
non-inverting input from being driven below ground.
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9.2.7 Bi-Stable Multivibrator
+V
R3
R4
100 kΩ
50 kΩ
R1
100 kΩ
+V
S
+
SET
œ
RESET
R
R2
100 kΩ
图9-16. Bi-Stable Multivibrator
A bi-stable multivibrator has two stable states. The reference voltage is set up by the voltage divider of R2 and
R3. A pulse applied to the SET terminal will switch the output of the comparator high. The resistor divider of R1
and R4 now sets the non-inverting input to a voltage greater than the reference voltage. A pulse applied to
RESET will now toggle the output low.
9.2.8 Zero Crossing Detector
+V
R3
100 kΩ
R4
100 kΩ
R1
5 kΩ
R2
5 kΩ
V
3
V
IN
œ
V
2
V
OUT
+
D1
BAT54
V
1
R4
20 MΩ
R5
10 kΩ
R1 = R2 = (R5 / 2)
图9-17. Zero Crossing Detector
A voltage divider of R4 and R5 establishes a reference voltage V1 at the non-inverting input. By making the
series resistance of R1 and R2 equal to R5, the comparator will switch when VIN = 0. Diode D1 insures that V3
clamps near ground. The voltage divider of R2 and R3 then prevents V2 from going below ground. A small
amount of hysteresis is setup to ensure rapid output voltage transitions.
9.2.9 Pulse Slicer
A Pulse Slicer is a variation of the Zero Crossing Detector and is used to detect the zero crossings on an input
signal with a varying baseline level. This circuit works best with symmetrical waveforms. The RC network of R1
and C1 establishes an mean reference voltage VREF, which tracks the mean amplitude of the VIN signal. The
non-inverting input is directly connected to VREF through R2. R2 and R3 are used to produce hysteresis to keep
transitions free of spurious toggles. The time constant is a tradeoff between long-term symmetry and response
time to changes in amplitude.
If the waveform is data, it is recommended that the data be encoded in NRZ (Non-Return to Zero) format to
maintain proper average baseline. Asymmetrical inputs may suffer from timing distortions caused by the
changing VREF average voltage.
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V
REF
470 kꢀ
R1
470 kꢀ
10M ꢀ
R3
+
R2
U1
Output
V
IN
œ
C1
0.01 ꢁF
图9-18. Pulse Slicer
For this design, follow these design requirements:
• The RC constant value (R2 and C1) must support the targeted data rate to maintain a valid tripping threshold.
• The hysteresis introduced with R2 and R43 helps to avoid spurious output toggles.
The TLV182x may also be used, but with the addition of a pull-up resistor on the output (not shown for clarity).
图9-19 shows the results of a 9600 baud data signal riding on a varying baseline.
1.8 V
VIN
1.2 V
4.0 V
VOUT
0.0 V
1.61 V
VREF
1.58 V
0.0
200.0 u
400.0 u
Time
600.0 u
800.0 u
图9-19. Pulse Slicer Waveforms
9.3 Power Supply Recommendations
Due to the fast output edges, it is critical to have bypass capacitors on the supply pin to prevent supply ringing
and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1 µF ceramic
bypass capacitor directly between VCC pin and ground pins. Narrow, peak currents will be drawn during the
output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed
supply lines and poor grounds to ring, possibly causing variation that can eat into the input voltage range and
create an inaccurate comparison or even oscillations.
The device may be powered from both "split" supplies (V+ and V-), or "single" supplies (V+ and GND), with GND
applied to the V- pin. Input signals must stay within the specified input range (between V+ and V-) for either type.
Note that with a "split" supply the ouptut will now swing "low" (VOL) to V- potential and not GND.
9.4 Layout
9.4.1 Layout Guidelines
For accurate comparator applications it is important maintain a stable power supply with minimized noise and
glitches. Output rise and fall times are in the tens of nanoseconds, and should be treated as high speed logic
devices. The bypass capacitor should be as close to the supply pin as possible and connected to a solid ground
plane, and preferably directly between the VCC and GND pins.
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ZHCSLV0B –SEPTEMBER 2022 –REVISED DECEMBER 2022
Minimize coupling between outputs and inputs to prevent output oscillations. Do not run output and input traces
in parallel unless there is a VCC or GND trace between output to reduce coupling. When series resistance is
added to inputs, place resistor close to the device. A low value (<100 ohms) resistor may also be added in series
with the output to dampen any ringing or reflections on long, non-impedance controlled traces. For best edge
shapes, controlled impedance traces with back-terminations should be used when routing long distances.
9.4.2 Layout Example
Ground
Better
0.1mF
VCC
1
2
3
4
8
7
6
5
1OUT
1IN-
VCC
2OUT
2IN-
Input Resistors
Close to device
OK
VCC or GND
1IN+
GND
Ground
2IN+
图9-20. Dual Layout Example
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
Analog Engineers Circuit Cookbook: Amplifiers (See Comparators section) - SLYY137
Precision Design, Comparator with Hysteresis Reference Design—TIDU020
Window comparator circuit - SBOA221
Reference Design, Window Comparator Reference Design—TIPD178
Comparator with and without hysteresis circuit - SBOA219
Inverting comparator with hysteresis circuit - SNOA997
Non-Inverting Comparator With Hysteresis Circuit - SBOA313
Zero crossing detection using comparator circuit - SNOA999
PWM generator circuit - SBOA212
How to Implement Comparators for Improving Performance of Rotary Encoder in Industrial Drive Applications -
SNOAA41
A Quad of Independently Func Comparators - SNOA654
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV1811DBVR
TLV1811LDBVR
TLV1812DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
5
5
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2XJT
2XNT
Samples
Samples
Samples
Samples
Samples
Samples
SN
NIPDAU
SN
TL1812
2XLT
TLV1821DBVR
TLV1821LDBVR
TLV1822DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
SN
2XMT
NIPDAU
TL1822
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV1812, TLV1822 :
Automotive : TLV1812-Q1, TLV1822-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV1811DBVR
TLV1811LDBVR
TLV1812DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
5
5
8
3000
3000
3000
3000
3000
3000
178.0
178.0
330.0
178.0
178.0
330.0
9.0
9.0
2.4
2.4
6.4
2.4
2.4
6.4
2.5
2.5
5.2
2.5
2.5
5.2
1.2
1.2
2.1
1.2
1.2
2.1
4.0
4.0
8.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q1
Q3
Q3
Q1
12.4
9.0
12.0
8.0
TLV1821DBVR
TLV1821LDBVR
TLV1822DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
9.0
8.0
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV1811DBVR
TLV1811LDBVR
TLV1812DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
5
5
8
3000
3000
3000
3000
3000
3000
180.0
180.0
356.0
180.0
180.0
356.0
180.0
180.0
356.0
180.0
180.0
356.0
18.0
18.0
35.0
18.0
18.0
35.0
TLV1821DBVR
TLV1821LDBVR
TLV1822DR
SOT-23
SOT-23
SOIC
DBV
DBV
D
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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