TLV2197-Q1 [TI]
汽车类、双通道、高电压、精密 RRIO 运算放大器;
| 型号： | TLV2197-Q1 |
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TEXAS INSTRUMENTS |
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TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B –APRIL 2020–REVISED JULY 2020
TLVx197-Q1 Automotive, High-Voltage, Precision, Rail-to-Rail In, Rail-to-Rail Out Op Amp
1 Features
3 Description
The TLV197-Q1, TLV2197-Q1 and TLV4197-Q1
(TLVx197-Q1) family of devices are part of a new
generation, of low-cost, 36-V, automotive-qualified,
operational amplifiers. The TLVx197-Q1 family uses a
method of package-level trim for offset and offset
temperature drift implemented during the final steps
of manufacturing after the plastic molding process.
This method minimizes the influence of inherent input
transistor mismatch, as well as errors induced during
package molding.
1
•
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to +125°C, TA
–
•
•
•
•
•
•
•
•
•
•
•
•
•
Low offset voltage: ±500 µV (maximum)
Low noise: 5.5 nV/√Hz at 1 kHz
High common-mode rejection: 140 dB
Low bias current: ±5 pA
Rail-to-rail input and output
Wide bandwidth: 10-MHz GBW
High slew rate: 20 V/µs
Good dc precision and ac performance including rail-
to-rail input/output, an optimized cost structure, and
AEC-Q100 grade 1 qualification, make this family an
excellent choice for low-side current-sensing and
signal-conditioning applications in the automotive
space.
Low quiescent current: 1 mA per amplifier
Wide supply: ±2.25 V to ±18 V, 4.5 V to 36 V
EMI/RFI filtered inputs
Differential input-voltage range to supply rail
High capacitive load drive capability: 1 nF
Industry-standard package:
More unique features, such as a differential input-
voltage range to the supply rail, a high output current
(±65 mA), a heavy capacitive load drive of up to 1 nF,
and a high slew rate (20 V/µs), make these devices a
robust, high-performance operational amplifier family
for high-voltage automotive applications.
–
–
–
Single channel in very small 8-pin VSSOP
Dual channel in 8-pin VSSOP
Quad channel in 14-pin TSSOP
The TLVx197-Q1 family of op amps is available in
standard packages and is specified from –40°C to
+125°C.
2 Applications
•
•
•
•
Inverter and motor control
DC/DC converter
Device Information
On-board (OBC) and wireless charger
Battery management system (BMS)
PART NUMBER
TLV197-Q1
PACKAGE
VSSOP (8)
TSSOP (14)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
5.00 mm x 4.40 mm
TLV2197-Q1
TLV4197-Q1
1. For all available packages, see the package option addendum
at the end of the data sheet.
TLVx197-Q1 Detect Voltages in Automotive Applications
VBUS
VREF
TLVx197-Q1
+
ADC
œ
GND
GND
`
VREF
TLVx197-Q1
+
ADC
œ
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B –APRIL 2020–REVISED JULY 2020
www.ti.com
Table of Contents
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 25
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
Power Supply Recommendations...................... 29
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information: TLV197-Q1 ............................. 7
6.5 Thermal Information: TLV2197-Q1 ........................... 7
6.6 Thermal Information: TLV4197-Q1 ........................... 7
8
9
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Examples................................................... 30
11 Device and Documentation Support ................. 31
11.1 Device Support...................................................... 31
11.2 Documentation Support ........................................ 31
11.3 Related Links ........................................................ 31
11.4 Receiving Notification of Documentation Updates 31
11.5 Support Resources ............................................... 31
11.6 Trademarks........................................................... 32
11.7 Electrostatic Discharge Caution............................ 32
11.8 Glossary................................................................ 32
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8
V to 36 V)................................................................... 8
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS
=
4.5 V to 8 V)............................................................. 10
6.9 Typical Characteristics............................................ 12
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2020) to Revision B
Page
•
Changed TLV197-Q1 and TLV2197-Q1 from advance information (preview) to production data (active) ............................ 1
Changes from Original (April 2020) to Revision A
Page
•
Changed to correct device names in titles for all Thermal Information tables ....................................................................... 7
2
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TLV197-Q1, TLV2197-Q1, TLV4197-Q1
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SBOS935B –APRIL 2020–REVISED JULY 2020
5 Pin Configuration and Functions
TLV197-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: TLV197-Q1
PIN
I/O
DESCRIPTION
NAME
+IN
–IN
NO.
3
I
Noninverting input
Inverting input
2
I
NC
1, 5, 8
—
O
—
—
No internal connection (can be left floating)
Output
OUT
V+
6
7
4
Positive (highest) power supply
Negative (lowest) power supply
V–
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TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B –APRIL 2020–REVISED JULY 2020
www.ti.com
TLV2197-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: TLV2197-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
5
2
I
6
I
1
O
O
—
—
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
4
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SBOS935B –APRIL 2020–REVISED JULY 2020
TLV4197-Q1 PW Package
14-Pin TSSOP
Top View
Pin Functions: TLV4197-Q1
PIN
I/O
DESCRIPTION
NAME
+IN A
–IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
5
10
12
2
I
I
I
6
I
9
I
13
1
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
11
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SBOS935B –APRIL 2020–REVISED JULY 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Single-supply, VS = (V+)
VS
Supply voltage
Voltage
Dual-supply, VS = (V+) – (V–)
Common-mode
±20
(V–) – 0.5
(V+) + 0.5
(V+) – (V–) +
0.2
+IN, –IN
Differential
Current
±10
Continuous
150
mA
Output short circuit(2)
Operating temperature
Junction temperature
Storage temperature
Continuous
–55
TA
TJ
150
°C
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
V
V(ESD)
Electrostatic discharge
Charge Device Model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±750
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single-supply, VS = (V+)
VS
TA
Supply voltage
Dual-supply, VS = (V+) – (V–)
±2.25
–40
±18
125
Operating temperature
°C
6
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SBOS935B –APRIL 2020–REVISED JULY 2020
6.4 Thermal Information: TLV197-Q1
TLV197-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
180.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
N/A
RθJC(top)
RθJB
67.9
102.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
10.4
ψJB
100.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductorand IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2197-Q1
TLV2197-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
158
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
N/A
RθJC(top)
RθJB
48.6
78.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
3.9
ψJB
77.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductorand IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4197-Q1
TLV4197-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
108.1
26.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
N/A
RθJC(top)
RθJB
54.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
1.4
ψJB
53.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductorand IC Package Thermal Metrics application
report.
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SBOS935B –APRIL 2020–REVISED JULY 2020
www.ti.com
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
±5
±1
±500
±5
µV
dVOS/dT
Input offset voltage drift TA = –40°C to +125°C
µV/°C
Power-supply rejection
TA = –40°C to +125°C
ratio
PSRR
±0.3
±1.0
µV/V
INPUT BIAS CURRENT
±5
±2
±20
±5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
±20
±2
IOS
Input offset current
Input voltage noise
NOISE
En
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 100 Hz
1.3
4
µVPP
10.5
5.5
32
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 1 kHz
Input voltage noise
density
en
nV/√Hz
f = 100 Hz
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 1 kHz
f = 1 kHz
12.5
Input current noise
density
in
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
(V+) + 0.1
V
120
114
100
86
140
126
120
100
(V–) – 0.1 V < VCM < (V+) – 3 V
(V–) < VCM < (V+) – 3 V
TA = –40°C to +125°C
TA = –40°C to +125°C
Common-mode
rejection ratio
CMRR
dB
(V+) – 1.5 V < VCM < (V+)
INPUT IMPEDANCE
ZID
Differential
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω ||
pF
ZIC
Common-mode
8
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SBOS935B –APRIL 2020–REVISED JULY 2020
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
120
114
126
134
126
140
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
AOL
Open-loop voltage gain
dB
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
120
134
FREQUENCY RESPONSE
GBW
SR
Unity gain bandwidth
10
20
MHz
V/µs
Slew rate
G = 1, 10-V step
To 0.01%
G = 1, 10-V step
G = 1, 5-V step
G = 1, 10-V step
G = 1, 5-V step
1.4
0.9
2.1
1.8
0.2
ts
Settling time
µs
To 0.001%
ts
Settling time
µs
µs
tOR
Overload recovery time VIN × G = VS
Total harmonic
THD+N
G = 1, f = 1 kHz, VO = 3.5 VRMS
0.00008%
distortion + noise
TLV4197-Q1 at dc
150
130
dB
dB
Crosstalk
TLV4197-Q1, f = 100 kHz
OUTPUT
No load
5
95
15
110
500
15
Positive rail
Negative rail
RL = 10 kΩ
RL = 2 kΩ
No load
430
5
Voltage output swing
from rail
VO
mV
RL = 10 kΩ
RL = 2 kΩ
95
110
500
430
±65
ISC
Short-circuit current
mA
mA
°C
POWER SUPPLY
1
1.2
1.5
Quiescent current per
IQ
IO = 0 A
amplifier
TEMPERATURE
Thermal protection
TA = –40°C to +125°C
140
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6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VCM = (V+) – 3 V
±5
±1
±500
±5
µV
dVOS/dT
Input offset voltage drift VCM = (V+) – 1.5 V
µV/°C
Power-supply rejection
TA = –40°C to +125°C
ratio
PSRR
±2
µV/V
INPUT BIAS CURRENT
±5
±2
±20
±5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
±20
±2
IOS
Input offset current
Input voltage noise
NOISE
En
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
f = 0.1 Hz to 10 Hz
f = 100 Hz
1.3
4
µVPP
10.5
5.5
32
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 1 kHz
Input voltage noise
density
en
nV/√Hz
f = 100 Hz
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 1 kHz
f = 1 kHz
12.5
Input current noise
density
in
1.5
fA/√Hz
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–) – 0.1
(V+) + 0.1
V
94
90
110
104
120
100
(V–) – 0.1 V < VCM < (V+) – 3 V
(V–) < VCM < (V+) – 3 V
TA = –40°C to +125°C
TA = –40°C to +125°C
Common-mode
rejection ratio
CMRR
dB
100
84
(V+) – 1.5 V < VCM < (V+)
INPUT IMPEDANCE
ZID
Differential
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω ||
pF
ZIC
Common-mode
10
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SBOS935B –APRIL 2020–REVISED JULY 2020
Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
110
100
110
120
114
126
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
TA = –40°C to +125°C
TA = –40°C to +125°C
AOL
Open-loop voltage gain
Open-loop voltage gain
dB
dB
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
AOL
110
120
FREQUENCY RESPONSE
GBW
SR
ts
Unity gain bandwidth
10
20
MHz
V/µs
µs
Slew rate
G = 1, 5-V step
To 0.01%
Settling time
VS = ±3V, G = 1, 5-V step
1
tOR
Overload recovery time VIN × G = VS
0.2
150
130
µs
dB
dB
TLV4197-Q1 at dc
Crosstalk
TLV4197-Q1, f = 100 kHz
OUTPUT
No load
5
95
15
110
500
15
Positive rail
RL = 10 kΩ
RL = 2 kΩ
No load
430
5
Voltage output swing
from rail
VO
mV
Negative rail
RL = 10 kΩ
RL = 2 kΩ
95
110
500
430
±65
ISC
Short-circuit current
mA
mA
°C
POWER SUPPLY
1
1.2
1.5
Quiescent current per
IQ
IO = 0 A
amplifier
TEMPERATURE
Thermal protection
TA = –40°C to +125°C
140
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6.9 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
50
25
0
100
75
VCM = +18.1 V
50
VCM = –18.1 V
P-Channel
25
0
–25
–50
–75
–100
VCM = –18.1 V
N-Channel
–25
–50
Transition
–20
–15
–10
–5
0
5
10
15
20
12.5
13.5
14.5
15.5
16.5
17.5
18.5
Common-Mode Voltage (V)
Common-Mode Voltage (V)
C001
Figure 1. Offset Voltage vs Common-Mode Voltage
Figure 2. Offset Voltage vs Common-Mode Voltage
200
150
100
50
50
40
10 Typical Units Shown
5 Typical Units Shown
30
20
10
0
0
–10
–20
–30
–40
–50
–50
–100
–150
–200
VCM = +2.35 V
N-Channel
VCM = –2.35 V
P-Channel
Transition
–2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
Power Supply Voltage (V)
Common-Mode Voltage (V)
VS = ±2.25 V
VS = ±2.25 V to ±18 V
Figure 3. Offset Voltage vs Common-Mode Voltage
Figure 4. Offset Voltage vs Power Supply
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
180
60.0
G = -100
G = +1
G = -1
Open-Loop Gain
135
40.0
20.0
0.0
G = -10
Phase
90
45
œ20.0
–20.0
0
10M 100M
1000
10k
100k
1M
10M
1
10
100
1k
10k 100k 1M
C003
Frequency (Hz)
Frequency (Hz)
CLOAD = 15 pF
Figure 5. Open-Loop Gain and Phase vs Frequency
Figure 6. Closed-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
6000
5000
4000
3000
2000
1000
0
20
IB+
IB -
15
Ios
10
IB–
5
0
IB+
–5
–10
–15
–20
Ios
œ1000
œ75 œ50 œ25
0
25
50
75 100 125 150 175
18.0
9.0
0.0
9.0
18.0
Temperature (°C)
Common-Mode Voltage (V)
C001
C001
Figure 7. Input Bias Current vs Common-Mode Voltage
Figure 8. Input Bias Current vs Temperature
(V–) + 5
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
(V–) + 4
(V–) + 3
(V–) + 2
(V–) + 1
(V–)
+125°C
– 40°C
+PSRR
CMRR
-PSRR
(V–) – 1
0
10
20
30
40
50
60
70
80
1
10
100
1k
10k
100k
1M
Output Current (mA)
C012
Frequency (Hz)
C001
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
Figure 10. CMRR and PSRR vs Frequency
10
1
0.8
8
6
0.6
0.4
4
VS
= 2.25 V, VCM = V+ - 3 V
0.2
2
0
0
–0.2
–0.4
–0.6
–0.8
–1
œ2
œ4
œ6
œ8
œ10
VS
= 18 V, VCM = 0 V
–75 –50 –25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C001
Figure 12. PSRR vs Temperature
Figure 11. CMRR vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
1000
VCM = V+ –100 mV
N-Channel Input
100
10
1
VCM = 0 V
P-Channel Input
µV
Peak-to-Peak Noise = VRMS × 6.6 = 1.30
Time (1 s/div)
pp
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
C002
C001
Figure 13. 0.1-Hz to 10-Hz Noise
Figure 14. Input Voltage Noise Spectral Density
vs Frequency
0.1
–60
0.1
0.01
–60
G = +1 V/V, RL = 10 kΩ
G = +1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
G = –1 V/V, RL = 2 kΩ
0.01
0.001
–80
–80
–100
–120
–140
0.001
–100
–120
–140
0.0001
0.0001
0.00001
G = +1 V/V, RL = 10 kΩ
G = +1 V/V, RL = 2 kΩ
G = –1 V/V, RL = 10 kΩ
G = –1 V/V, RL = 2 kΩ
0.00001
0.01
0.1
1
10
10
100
1k
10k
Output Amplitude (VRMS
)
Frequency (Hz)
f = 1 kHz, BW = 80 kHz
VOUT = 3.5 VRMS, BW = 80 kHz
Figure 15. THD+N Ratio vs Frequency
Figure 16. THD+N vs Output Amplitude
1.2
1.1
1.0
0.9
1.2
1.1
1
VS = 18 V
VS = 2.25 V
0.9
0.8
0
0.8
75
4
8
12
16
20
24
28
32
36
50
25
0
25
50
75
100 125 150
Supply Voltage (V)
Temperature (°C)
C001
Figure 17. Quiescent Current vs Supply Voltage
Figure 18. Quiescent Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
3.0
2.0
10k
VS = 4.5 V
VS = 36 V
1k
1.0
0.0
100
10
–1.0
–2.0
–3.0
0
1
10
100
1k
10k 100k 1M
10M
–75 –50 –25
0
25
50
75
100 125 150
Frequency (Hz)
Temperature(°C)
C016
RL = 10 kΩ
Figure 19. Open-Loop Gain vs Temperature
Figure 20. Open-Loop Output Impedance vs Frequency
50
45
40
35
30
25
20
15
10
5
50
+ 18 V
45
40
35
30
25
20
15
10
5
-
+ 18 V
RISO
TLV197-Q1
-
RISO
+
+
-
RL
CL
+
-
TLV197-Q1
VIN
-18 V
VIN
+
CL
-18 V
0
RISO = 0 Ω
RISO = 252Ω5
RISO = 50 Ω
RISO = 0 Ω
0
RISO = 25 Ω
25
RISO = 50 Ω
50
0
0
10p
100p
1n
10p
100p
1n
Capacitive Load (F)
Capacitive Load (F)
G = 1
RI = 1 kΩ, RF = 1 kΩ, G = –1
Figure 21. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 22. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
VOUT
+ 18
V
-
+
-
VOUT
TLV197-Q1
VIN
+
- 18
V
+ 18 V
-
TLV197-Q1
+
+
VIN
RL
CL
-18 V
-
VIN
Time (100 ns/div)
Time (200 ns/div)
CL = 10 pF, G = 1
RI = 1 kΩ, RF = 10 kΩ, G = –10
Figure 24. Small-Signal Step Response (100 mV)
Figure 23. Positive Overload Recovery
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
+ 18
V
-
+
-
TLV197-Q1
VIN
+
CL
- 18
V
+ 18 V
-
+
-
TLV197-Q1
VIN
+
CL
-18 V
Time (120 ns/div)
Time (300 ns/div)
RL = 1 kΩ, CL = 10 pF, G = –1
RL = 1 kΩ, CL = 10 pF, G = –1
Figure 25. Small-Signal Step Response (100 mV)
Figure 26. Large-Signal Step Response
4
3
4
3
2
2
1
1
0
0
0.01% Settling = 500 μV
–1
–2
–3
–4
–1
–2
–3
–4
0.01% Settling = 1 mV
Step Applied at t = 0
Step Applied at t = 0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
Time (μs)
Time (μs)
G = 1
G = 1
Figure 28. Settling Time (5-V Positive Step)
Figure 27. Settling Time (10-V Positive Step)
80
60
40
20
0
30
25
20
15
10
5
Maximum output voltage without
slew-rate induced distortion.
VS
= 15 V
ISC, Source
ISC, Sink
VS
= 5 V
VS
=
2.25 V
0
10k
100k
1M
Frequency (Hz)
10M
–75 –50 –25
0
25
50
75
100 125 150
Temperature (°C)
C033
C001
Figure 29. Short-Circuit Current vs Temperature
Figure 30. Maximum Output Voltage vs Frequency
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SBOS935B –APRIL 2020–REVISED JULY 2020
Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Overdrive = 100 mV
VOUT Voltage
tpLH = 1.1 ꢀs
tpLH = 0.97 ꢀs
VOUT Voltage
Overdrive = 100 mV
Time (200 ns/div)
Time (200 ns/div)
C025
C026
Figure 31. Propagation Delay Rising Edge
Figure 32. Propagation Delay Falling Edge
-80
-100
-120
-140
-160
-180
1k
10k
100k
1M
Frequency (Hz)
Figure 33. Crosstalk vs Frequency
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7 Detailed Description
7.1 Overview
The TLVx197-Q1 family of e-trim™ operational amplifiers uses a method of package-level trim for offset and
offset temperature drift implemented during the final steps of manufacturing after the plastic molding process.
This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during
package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim
points are set, further communication to the trim structure is permanently disabled. The Functional Block
Diagram shows the simplified diagram of the TLVx197-Q1 e-trim operational amplifier.
Unlike previous e-trim op amps, the TLVx197-Q1 uses a patented two-temperature trim architecture to achieve a
low offset voltage of 500 µV (maximum), and low voltage offset drift of 5 µV/°C (maximum) over the full specified
temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for
high-impedance industrial sensors, filters, and high-voltage data acquisition.
7.2 Functional Block Diagram
+
NCH Input
Stage
œ
IN+
+
High Capacitive
Load
Compensation
VOUT
36-V
Differential
Front End
Output
Stage
Slew
Boost
œ
INœ
+
PCH Input
Stage
œ
e-trim™
Package Level Trim
18
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SBOS935B –APRIL 2020–REVISED JULY 2020
7.3 Feature Description
7.3.1 Input Protection Circuitry
The TLVx197-Q1 use a unique input architecture to eliminate the need for input protection diodes, but still
provide robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 34 can be activated by fast transient step responses, and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 35. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, cause an increase in input current, and result in extended settling time.
TLV197-Q1 Provides Full 36-
V Differential Input Range
Conventional Input Protection
Limits Differential Input Range
V+
V+
+
VIN+
VIN+
+
VOUT
VOUT
TLVx197-Q1
~0.7 V
36 V
œ
VIN-
œ
VIN-
V-
V-
Figure 34. TLVx197-Q1 Input Protection Does Not Limit Differential Input Capability
1
Ron_mux
Vn = +10 V
RFILT
+10 V
Sn
D
1
2
~œ9.3 V
+10 V
CFILT
CS
CD
Vinœ
2
Ron_mux
Sn+1
Vn+1 = œ10 V RFILT
œ10 V
~0.7 V
Vout
CFILT
CS
Idiode_transient
Vin+
œ10 V
Input Low Pass Filter
Simplified Mux Model
Buffer Amplifier
Figure 35. Back-to-Back Diodes Create Settling Issues
The TLVx197-Q1 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications. This patented input protection architecture does not introduce additional signal
distortion or delayed settling time, and makes the device an excellent choice for multichannel, high-switched,
input applications. The TLVx197-Q1 tolerates a maximum differential swing (voltage between inverting and
noninverting pins of the op amp) of up to 36 V, thus making the device great for use as a comparator or in
applications with fast-ramping input signals such as multiplexed data-acquisition systems; see Figure 41.
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Feature Description (continued)
7.3.2 EMI Rejection
The TLVx197-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLVx197-Q1 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 36 shows the results of this testing on the TLVx197-Q1. Table 1 shows the EMIRR IN+ values for the
TLVx197-Q1 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 1 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in the EMI Rejection Ratio of Operational Amplifiers application report, available for download from
www.ti.com.
160.0
PRF = -10 dBm
VSUPPLY = 18 V
VCM = 0 V
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
Frequency (Hz)
1G
10G
C017
Figure 36. EMIRR Testing
Table 1. TLVx197-Q1 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications
44.1 dB
Global system for mobile communications (GSM) applications, radio communication, navigation, GPS
(to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
52.8 dB
61.0 dB
69.5 dB
88.7 dB
105.5 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
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7.3.3 Phase Reversal Protection
The TLVx197-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the respective linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The TLVx197-Q1 is a rail-to-rail input op amp; therefore, the common-
mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the
output limits into the appropriate rail.
7.3.4 Thermal Protection
CAUTION
The absolute maximum junction temperature of the TLVx197-Q1 is 150°C. Exceeding
this temperature causes damage to the device.
The internal power dissipation of any amplifier causes the internal (junction) temperature of the amplifier to rise.
This phenomenon is called self heating. The TLVx197-Q1 has a thermal protection feature that prevents damage
from self heating. The protection works by monitoring the temperature of the device and turning off the op amp
output drive for temperatures greater than 140°C. Figure 37 shows an application example for the TLVx197-Q1
that has significant self heating (159°C) because of the power dissipation (0.81 W). Thermal calculations indicate
that for an ambient temperature of 65°C, the device junction temperature must reach 187°C. The actual device,
however, turns off the output drive to maintain a safe junction temperature. Figure 37 shows how the circuit
behaves during thermal protection. During normal operation, the device acts as a buffer, so the output is 3 V.
When self heating causes the device junction temperature to exceed 140°C, the thermal protection forces the
output to a high-impedance state, and the output is pulled to ground through resistor RL.
Normal
Operation
3 V
TA = 65°C
PD = 0.81W
30 V
Output
High-Z
0 V
RꢀJA = 116°C/W
TJ = 116°C/W × 0.81W + 65°C
TJ = 159°C (expected)
œ
150°C
140°C
TLVx197-Q1
+
IOUT = 30 mA
+
3 V
œ
RL
100 Ω
+
VIN
3 V
œ
Figure 37. Thermal Protection
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7.3.5 Capacitive Load and Stability
The TLVx197-Q1 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads.
The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether an amplifier is stable in operation.
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10-
Ω to 20-Ω) resistor, RISO, in series with the output, as shown in Figure 38. This resistor significantly reduces
ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with
the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive load drive makes the TLVx197-Q1 a great choice for applications such as
reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 38 uses an isolation
resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased
phase margin, and the results using the TLVx197-Q1 are summarized in Table 2. For additional information on
techniques to optimize and design using this circuit, reference design TIPD128, Capacitive Load Drive Verified
Reference Design Using an Isolation Resistor, details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Cload
+
Vin
-Vs
œ
Figure 38. Extending Capacitive Load Drive With the TLVx197-Q1
Table 2. TLVx197-Q1 Capacitive Load Drive Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER
Capacitive Load
Phase Margin
RISO (Ω)
VALUE
100 pF
1000 pF
0.01 µF
0.1 µF
1 µF
45°
47
60°
45°
24
60°
45°
20
60°
51
45°
6.2
60°
45°
2
60°
4.7
360
100
15.8
Measured
Overshoot (%)
23.2 8.6
45.1°
10.4
22.5
9
22.1
8.7
23.1
8.6
21
8.6
Calculated PM
58.1°
45.8°
59.7°
46.1°
60.1°
45.2°
60.2°
47.2°
60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results,
see TI Precision Design TIDU032, Capacitive Load Drive Solution using an Isolation Resistor .
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7.3.6 Common-Mode Voltage Range
The TLVx197-Q1 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 39. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV greater than the positive supply. The P-channel pair is
active for inputs from 100 mV less than the negative supply to approximately (V+) – 1.5 V. There is a small
transition region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can
vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and
THD performance may be degraded compared to operation outside this region.
+Vsupply
IS1
VINœ
PCH1
NCH4
NCH3
PCH2
VIN+
e-trimTM
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
œVsupply
Figure 39. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The TLVx197-Q1 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, and causes the variance in the
transition region of the input stages to appear exaggerated relative to offset over the full common-mode range.
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 40 shows an illustration of the ESD circuits contained in the TLVx197-Q1 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+VS
VDD
TLVx197-Q1
R1
RS
100 ꢀ
100 ꢀ
INœ
œ
IN+
+
Power Supply
ESD Cell
RL
+
VIN
œ
VSS
œVS
TVS
Figure 40. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns); whereas, an EOS
event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-
circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the
PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
24
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLVx197-Q1 is approximately 200 ns.
7.4 Device Functional Modes
The TLVx197-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the TLVx197-Q1 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLVx197-Q1 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input and output, low offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the TLVx197-Q1 a robust, high-
performance operational amplifier for high-voltage automotive applications.
8.2 Typical Applications
8.2.1 16-Bit Precision Multiplexed Data-Acquisition System
Figure 41 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
sensor based applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the
TLVx197-Q1 and TLV140 to achieve excellent dynamic performance and linearity with the ADS8864.
1
2
3
4
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Very Low Output Impedance
Input-Filter Bandwidth
Voltage
Reference
TLVx197-Q1
+
CH0+
CH0-
RC Filter
Buffer
RC Filter
20-V,
10-kHz
Sine Wave
Reference Driver
+
Gain
Network
Gain
Network
TLVx197-Q1
TLVx197-Q1
+
4:2
Mux
REFP
+
TLVx197-Q1
VINP
Gain
Network
TLVx197-Q1
+
CH3+
TLVx197-Q1
+
Antialiasing
Filter
SAR
ADC
20-V,
10-kHz
Sine Wave
+
VINM
TLVx197-Q1
CH3-
n
CONV
16 Bits
400 kSPS
High-Voltage Level Translation
High-Voltage Multiplexed Input
Voltage
Divider
REF3240
OPA350
Shmidtt
Trigger
VCM Generation Circuit
Counter
Delay
n
5
Fast logic transition
Digital Counter For Multiplexer
Figure 41. TLVx197-Q1 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-
Voltage Inputs With Lowest Distortion
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Typical Applications (continued)
8.2.1.1 Design Requirements
The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest
distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.
The design requirements for this block design are:
•
•
•
•
•
System supply voltage: ±15 V
ADC supply voltage: 3.3 V
ADC sampling rate: 400 kSPS
ADC reference voltage (REFP): 4.096 V
System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
8.2.1.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for
highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 41. The circuit
is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output
buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast
sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design
considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input
analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each
analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit
resolution and lowest distortion system. Figure 41 includes the most important specifications for each individual
analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding
helps in the decision of an appropriate input filter and selection of a mux to meet the system settling
requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level
translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next
step is to design a digital interface to switch the mux input channels with minimum delay. The final design
challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage
with low offset, drift, and noise contributions.
8.2.1.3 Application Curve
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
–15
–10
–5
0
5
10
15
20
ADC Differential Input (V)
Figure 42. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TIPD151, 16-
Bit, 400 kSPS 4-Channell, Multiplexed Data Acquisition Ref erence Design for High Voltage Inputs, Low Distortion.
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8.2.2 Slew-Rate Limit for Input Protection
In control systems for motors, abrupt changes in voltages or currents can cause mechanical damages. By
controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at
a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional
op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output
current and slew rate of the TLVx197-Q1 make these devices an optimal amplifier to achieve slew-rate control for
both dual- and single-supply systems.Figure 43 shows the TLVx197-Q1 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
470 nF
R1
1.69 kΩ
VEE
VEE
R2
œ
1.6 MΩ
-
TLVx197-Q1
TLVx197-Q1
VIN
V+
+
VOUT
V+
+
VCC
RL
10 kΩ
VCC
Figure 43. Slew-Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see TIPD140, Single
Op-Amp Slew Rate Limiter Reference Design.
8.2.3 Precision Reference Buffer
The TLVx197-Q1 feature high output-current-drive capability and low input offset voltage, making the device an
excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the
10-µF ceramic capacitor shown in Figure 44, RISO, a 37.4-Ω isolation resistor, provides separation of two
feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output (VOUT).
Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized
stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still
provide a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability
components: RF, RFx, CF, and RISO
.
RF
1 kΩ
CF
39 nF
RFx
10 kΩ
RISO
37.4 Ω
œ
VOUT
TLVx197-Q1
+
V+
CL
10 µF
+
VREF
2.5 V
VCC
Figure 44. Precision Reference Buffer
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9 Power Supply Recommendations
The TLVx197-Q1 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Absolute
Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole. and through
the individual op amp. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
than in parallel with the noisy trace.
•
•
•
Place the external components as close as possible to the device. As illustrated in Figure 46, keep RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
For best performance, clean the PCB following board assembly.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove
moisture introduced into the device packaging during the cleaning process. A low-temperature, post-
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Examples
VIN
+
VOUT
RG
RF
Figure 45. Schematic Representation
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
RF
VS+
N/C
N/C
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
Figure 46. Operational Amplifier Board Layout for Noninverting Configuration
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SBOS935B –APRIL 2020–REVISED JULY 2020
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference design
11.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 3. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV197-Q1
TLV2197-Q1
TLV4197-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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11.6 Trademarks
e-trim, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV197QDGKRQ1
TLV2197QDGKRQ1
TLV4197QPWRQ1
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
TSSOP
DGK
DGK
PW
8
8
2500 RoHS & Green
2500 RoHS & Green
2000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
Q197
2BD6
NIPDAUAG
NIPDAU
14
T4197Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV197QDGKRQ1
TLV2197QDGKRQ1
TLV4197QPWRQ1
VSSOP
VSSOP
TSSOP
DGK
DGK
PW
8
8
2500
2500
2000
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.9
3.4
3.4
5.6
1.4
1.4
1.6
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV197QDGKRQ1
TLV2197QDGKRQ1
TLV4197QPWRQ1
VSSOP
VSSOP
TSSOP
DGK
DGK
PW
8
8
2500
2500
2000
366.0
366.0
356.0
364.0
364.0
356.0
50.0
50.0
35.0
14
Pack Materials-Page 2
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相关型号：
TLV2211IDBVTG4
Single, 10-V, 65-kHz operational amplifier with high output current (10 mA) | DBV | 5 | -40 to 85
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