TLV2254AQDRG4 [TI]
Advanced LinCMOS RAIL-TO-RAIL VERY LOW-POWER POERATIONAL AMPLIFIERS; 高级LinCMOS轨到轨极低功耗POERATIONAL放大器
| 型号： | TLV2254AQDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Advanced LinCMOS RAIL-TO-RAIL VERY LOW-POWER POERATIONAL AMPLIFIERS |
| 文件： | 总55页 (文件大小：1303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
D Output Swing Includes Both Supply Rails
D Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz
D Low Input Bias Current . . . 1 pA Typ
D Low Input Offset Voltage
850 µV Max at T = 25°C
A
D Wide Supply Voltage Range
2.7 V to 8 V
D Fully Specified for Both Single-Supply and
D Macromodel Included
Split-Supply Operation
D Available in Q-Temp Automotive
HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
D Very Low Power . . . 34 µA Per Channel Typ
D Common-Mode Input Voltage Range
Includes Negative Rail
description
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
The TLV2252 and TLV2254 are dual and
quadruple low-voltage operational amplifiers from
Texas Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLV225x family consumes only 34 µA of supply
current per channel. This micropower operation
makes them good choices for battery-powered
applications. This family is fully characterized at
3 V and 5 V and is optimized for low-voltage
applications. The noise performance has been
dramatically improved over previous generations
of CMOS amplifiers. The TLV225x has a noise
level of 19 nV/√Hz at 1kHz, four times lower than
competitive micropower solutions.
3
V
= 3 V
DD
2.5
2
T
= −40°C
A
T
= 25°C
A
1.5
1
T
= 85°C
A
T
= 125°C
A
0.5
0
The TLV225x, exhibiting high input impedance
and low noise, are excellent for small-signal
conditioning for high-impedance sources, such as
piezoelectric transducers. Because of the micro-
power dissipation levels combined with 3-V
operation, these devices work well in hand-held
monitoring and remote-sensing applications. In
0
200
400
600
800
| I
OH
| − High-Level Output Current − µA
Figure 1
addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when
interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV225xA family is
available and has a maximum input offset voltage of 850 µV.
The TLV2252/4 also make great upgrades to the TLV2322/4 in standard designs. They offer increased output
dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set allows them to
be used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption, make them ideal for high density, battery-powered equipment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
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Copyright 1997−2006, Texas Instruments Incorporated
ꢑ ꢋ ꢦ ꢡ ꢠꢈ ꢥꢌ ꢣꢤ ꢌꢠ ꢢꢦ ꢨꢎ ꢊꢋ ꢣ ꢣꢠ ꢐꢔ ꢁꢕ ꢙꢓ ꢛ ꢕꢮꢯꢄ ꢮꢄꢆ ꢊꢨꢨ ꢦꢊ ꢡ ꢊ ꢢꢍ ꢣꢍꢡ ꢤ ꢊ ꢡ ꢍ ꢣꢍ ꢤꢣꢍ ꢈ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252 AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
CERAMIC
FLATPACK
(U)
IO
‡
T
A
TSSOP
(PW)
†
AT 25°C
(JG)
(P)
850 µV
1500 µV
TLV2252AID
TLV2252ID
—
—
—
—
TLV2252AIP TLV2252AIPWLE
—
—
−40°C to 125°C
TLV2252IP
—
850 µV
1500 µV
TLV2252AQD
TLV2252QD
—
—
—
—
—
—
—
—
—
—
−40°C to 125°C
−55°C to 125°C
850 µV
1500 µV
—
—
TLV2252AMFK TLV2252AMJG
TLV2252MFK TLV2252MJG
—
—
—
—
TLV2252AMU
TLV2252MU
†
‡
§
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2252CDR).
The PW package is available only left-end taped and reeled.
Chips are tested at 25°C.
TLV2254 AVAILABLE OPTIONS
PACKAGED DEVICES
V
max
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
CERAMIC
FLATPACK
(W)
IO
‡
T
A
TSSOP
(PW)
†
AT 25°C
(J)
(N)
850 µV
1500 µV
TLV2254AID
TLV2254ID
—
—
—
—
TLV2254AIN TLV2254AIPWLE
—
—
−40°C to 125°C
TLV2254IN
—
850 µV
1500 µV
TLV2254AQD
TLV2254QD
—
—
—
—
—
—
—
—
—
—
−40°C to 125°C
−55°C to 125°C
850 µV
1500 µV
—
—
TLV2254AMFK
TLV2254MFK
TLV2254AMJ
TLV2254MJ
—
—
—
—
TLV2254AMW
TLV2254MW
†
‡
§
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2254CDR).
The PW package is available only left-end taped and reeled.
Chips are tested at 25°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252I, TLV2252AI
TLV2252Q, TLV2252AQ
D, P, OR PW PACKAGE
(TOP VIEW)
TLV2254I, TLV2254AI, TLV2254Q, TLV2254AQ . . . D OR N PACKAGE
TLV2254M, TLV2254AM . . . J OR W PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
V
DD+
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
2OUT
2IN−
2IN+
V
/GND
DD−
V
V
/GND
DD+
DD−
2IN+
2IN−
3IN+
3IN−
3OUT
TLV2252M, TLV2252AM . . . JG PACKAGE
(TOP VIEW)
8
2OUT
1OUT
1IN−
1IN+
V
DD+
1
2
3
4
8
7
6
5
2OUT
2IN−
2IN+
V
/GND
DD−
TLV2254I, TLV2254AI . . . PW PACKAGE
(TOP VIEW)
TLV2252M, TLV2252AM . . . U PACKAGE
(TOP VIEW)
1
1OUT
1IN −
1IN +
4OUT
4IN −
4IN +
14
NC
1OUT
1IN −
1IN +
/GND
NC
V
2OUT
2IN −
2IN +
1
10
9
V
V
/GND
DD+
DD −
+
2
3
4
5
2IN +
2IN −
2OUT
3IN +
3IN −
3OUT
CC
8
7
8
7
V
6
CC−
TLV2252M, TLV2252AM . . . FK PACKAGE
(TOP VIEW)
TLV2254M, TLV2254AM . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
3
2
1
20 19
18
NC
4IN+
NC
NC
1IN−
NC
1IN+
NC
4
5
6
7
8
4
5
6
7
8
2OUT
NC
17
16
15
14
17
16
15
14
V
/GND
V
DD−
DD+
NC
2IN−
NC
NC
1IN+
NC
3IN+
2IN+
9 10 11 12 13
9 10 11 12 13
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Template Release Date: 7−11−94
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SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
4
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
V
ID
DD
−0.3 V to V
I
DD−
DD+
Input current, I (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
DD+
DD−
Total current out of V
Duration of short-circuit current (at or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : I Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
A
Q Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, P, and PW packages . . . . . . . 260°C
J, JG, U, and W packages . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to V
.
DD −
2. Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought
below V − 0.3 V.
DD−
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 85°C
T = 125°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
D−8
D−14
FK
725 mW
5.8 mW/°C
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
8.4 mW/°C
377 mW
145 mW
950 mW
494 mW
190 mW
1375 mW
1375 mW
1050 mW
715 mW
275 mW
J
715 mW
275 mW
JG
546 mW
210 mW
N
P
1150 mW
1000 mW
525 mW
700 mW
700 mW
700 mW
9.2 mW/°C
8.0 mW/°C
4.2 mW/°C
5.6 mW/°C
5.5 mW/°C
5.5 mW/°C
598 mW
520 mW
273 mW
364 mW
370 mW
370 mW
230 mW
200 mW
105 mW
140 mW
150 mW
150 mW
PW−8
PW−14
U
W
recommended operating conditions
TLV225xI
TLV225xQ
TLV225xM
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Supply voltage, V
ꢀ ꢁ ꢂꢂ ꢃ ꢄꢅ ꢂ ꢆꢇ
Input voltage range, V
2.7
8
2.7
8
2.7
8
V
V
DD
V
V
V
V
−1.3
V
V
V
V
−1.3
V
V
V
V
−1.3
I
DD−
DD+
DD−
DD+
DD−
DD+
Common-mode input voltage, V
IC
−1.3
−1.3
−1.3
V
DD−
−40
DD+
DD−
−40
DD+
DD−
−55
DD+
Operating free-air temperature, T
125
125
125
°C
A
NOTE 1: All voltage values, except differential voltages, are with respect to V
DD −
.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252I electrical characteristics at specified free-air temperature, V
noted)
= 3 V (unless otherwise
DD
TLV2252I
TLV2252AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
200 1500
1750
MIN
TYP MAX
25°C
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage
long-term drift (see
Note 4)
25°C
25°C
0.003
0.003
0.5
µV/mo
V
V
= 1.5 V,
V
R
= 0,
= 50 Ω
DD
= 0,
IC
S
0.5
60
60
O
−40°C
to 85°C
150
150
I
I
Input offset current
Input bias current
pA
IO
Full range
1000
60
1000
60
25°C
1
1
−40°C
to 85°C
150
150
pA
V
IB
Full range
1000
1000
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
R
= 50 Ω,
|V | ≤5 mV
IO
ICR
OH
S
0
to
0
to
Full range
1.7
1.7
I
I
I
= −20 µA
= −75 µA
= −150 µA
= 1.5 V,
25°C
25°C
2.98
2.98
OH
OH
OH
2.9
2.8
2.8
2.9
2.8
2.8
High-level output
voltage
V
V
Full range
25°C
25°C
10
100
200
250
800
10
100
200
250
800
V
V
V
I
I
I
= 50 µA
= 500 µA
= 1 ꢈA
IC
IC
IC
OL
OL
OL
Full range
25°C
80
150
300
80
150
300
Low-level output
voltage
V
OL
= 1.5 V,
= 1.5 V,
mV
Full range
25°C
Full range
25°C
100
10
100
10
‡
R
R
= 100 kΩ
Large-signal differential
voltage amplification
V
V
= 1.5 V,
= 1 V to 2 V
L
L
IC
O
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
220
75
220
77
25°C
Full range
65
60
65
60
Common-mode
rejection ratio
V
IC
V
O
= 0 to 1.7 V,
= 1.5 V,
CMRR
dB
R
= 50 Ω
S
†
‡
Full range is − 40°C to 125°C.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖ
ꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 3 V (unless otherwise
DD
TLV2252I
TLV2252AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
Supply voltage
rejection ratio
25°C
80
95
80
100
V
V
= 2.7 V to 8 V,
DD
IC
k
dB
SVR
= V
/2,
No load
DD
Full range
80
80
(∆V
/∆V )
DD
IO
25°C
Full range
68
125
150
68
125
150
I
Supply current
V
O
= 1.5 V,
No load
µA
DD
†
Full range is − 40°C to 125°C.
TLV2252I operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2252I
TLV2252AI
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
TYP MAX
0.07
0.1
0.07
0.1
V
R
C
= 1.1 V to 1.9 V,
25°C
O
L
L
‡
= 100 kΩ ,
SR
Slew rate at unity gain
V/µs
Full
range
‡
0.05
0.05
= 100 pF
f = 10 Hz
f = 1 kHz
25°C
25°C
35
19
35
19
Equivalent input noise
voltage
nV/√Hz
µV
V
n
Peak-to-peak
equivalent input noise
voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.6
1.1
0.6
1.1
V
I
N(PP)
Equivalent input noise
current
25°C
25°C
25°C
0.6
0.187
60
0.6
0.187
60
fA/√Hz
MHz
n
‡
f = 1 kHz,
R
= 50 kΩ ,
L
Gain-bandwidth product
‡
C
= 100 pF
L
Maximum output-swing
bandwidth
V
R
= 1 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
kHz
‡
‡
C
= 100 pF
L
L
Phase margin at unity
gain
φ
m
25°C
25°C
63°
63°
‡
‡
R
= 50 kΩ ,
C
= 100 pF
L
Gain margin
15
15
dB
†
‡
Full range is −40°C to 125°C.
Referenced to 1.5 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252I electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLV2252I
TLV2252AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
200 1500
1750
MIN
TYP MAX
25°C
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage long-
term drift (see Note 4)
25°C
0.003
0.003
0.5
µV/mo
25°C
0.5
1
60
60
V
V
=
2.5 V,
V
= 0,
= 50 Ω
DD
= 0,
IC
R
S
−40°C
to 85°C
O
150
150
I
I
Input offset current
Input bias current
pA
pA
IO
Full range
1000
60
1000
60
25°C
1
−40°C
to 85°C
150
150
IB
Full range
1000
1000
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
|V | ≤5 mV,
IO
R
= 50 Ω
S
V
V
ICR
OH
0
to
3.5
0
to
3.5
Full range
I
I
I
= −20 µA
= −75 µA
= −150 µA
= 2.5 V,
25°C
25°C
4.98
4.94
4.98
4.94
OH
OH
OH
4.9
4.8
4.8
4.9
4.8
4.8
V
High-level output voltage
Low-level output voltage
Full range
25°C
4.88
0.01
4.88
0.01
25°C
V
V
V
I
I
I
= 50 µA
= 500 µA
= 1 ꢈA
IC
IC
IC
OL
OL
OL
Full range
25°C
0.06
0.15
0.15
0.3
0.06
0.15
0.15
0.3
0.09
0.2
0.09
0.2
V
OL
= 2.5 V,
= 2.5 V,
V
Full range
25°C
Full range
25°C
0.3
0.3
100
10
350
100
10
350
‡
R
R
= 100 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
1700
1700
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
200
83
200
83
25°C
70
70
70
70
Common-mode rejection
ratio
V
= 2.5 V,
V
= 0 to 2.7 V,
O
IC
= 50 Ω
CMRR
dB
R
Full range
S
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓ
ꢗ
ꢁ
ꢑ
ꢘ
ꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 5 V (unless otherwise
DD
TLV2252I
TLV2252AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
80
TYP MAX
MIN
80
TYP MAX
25°C
Full range
25°C
95
95
Supply voltage rejection
V
V
= 4.4 V to 8 V,
DD
IC
k
dB
SVR
ratio (∆V
DD
/∆V
IO
)
= V
/2,
No load
80
80
DD
70
125
150
70
125
150
I
Supply current
V
O
= 2.5 V,
No load
µA
DD
Full range
†
Full range is − 40°C to 125°C.
TLV2252I operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2252I
TLV2252AI
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
TYP MAX MIN
TYP MAX
25°C
0.07
0.12
0.07
0.05
0.12
‡
V
C
= 1.5 V to 3.5 V,
R
= 100 kΩ ,
L
O
L
SR
Slew rate at unity gain
Full
range
‡
= 100 pF
0.05
f = 10 Hz
f = 1 kHz
25°C
25°C
36
19
36
19
Equivalent input noise
voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.1
0.7
1.1
V
I
µV
N(PP)
Equivalent input noise
current
25°C
25°C
0.6
0.6
fA/√Hz
n
V
= 0.5 V to 2.5 V,
A
= 1
0.2%
1%
0.2%
1%
O
V
Total harmonic
distortion plus noise
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.2
30
0.2
30
MHz
kHz
‡
C
= 100 pF
L
Maximum output-swing
bandwidth
V
R
= 2 V,
‡,
A
= 1,
O(PP)
L
V
B
OM
‡
= 50 kΩ
C
= 100 pF
L
L
Phase margin at unity
gain
φ
m
25°C
25°C
63°
63°
‡
‡
R
= 50 kΩ ,
C
= 100 pF
L
Gain margin
15
15
dB
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254I electrical characteristics at specified free-air temperature, V
noted)
= 3 V (unless otherwise
DD
TLV2254I
TLV2254AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
200 1500
1750
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature
coefficient of input
offset voltage
25°C
to 85°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage
long-term drift
(see Note 4)
25°C
25°C
0.003
0.5
0.003
0.5
µV/mo
V
V
=
1.5 V,
V
R
= 0,
= 50 Ω
S
DD
= 0,
IC
60
60
O
−40°C
to 85°C
150
150
I
I
Input offset current
Input bias current
pA
IO
Full range
1000
60
1000
60
25°C
1
1
−40°C
to 85°C
150
150
pA
V
IB
Full range
1000
1000
0
−0.3
to 2 to 2.2
0
−0.3
to 2 to 2.2
25°C
Common-mode input
voltage range
R
= 50 Ω,
S
V
|V | ≤5 mV
IO
ICR
OH
0
0
Full range
to 1.7
to 1.7
I
I
I
= −20 µA
= −75 µA
= −150 µA
= 1.5 V,
25°C
25°C
2.98
2.98
OH
OH
OH
2.9
2.8
2.8
2.9
2.8
2.8
High-level output
voltage
V
V
Full range
25°C
25°C
10
100
200
225
800
10
100
200
225
800
V
IC
V
IC
V
IC
I
I
I
= 50 µA
= 500 µA
= 1 ꢈA
OL
OL
OL
Full range
25°C
80
150
300
80
150
300
Low-level output
voltage
V
= 1.5 V,
= 1.5 V,
mV
OL
Full range
25°C
Full range
25°C
100
10
100
10
Large-signal
differential voltage
amplification
‡
R
R
= 100 kΩ
V
IC
V
O
= 1.5 V,
= 1 V to 2 V
L
L
Full range
25°C
A
V/mV
VD
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
N package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
220
75
220
77
25°C
65
60
65
60
Common-mode
rejection ratio
V = 0 to 1.7 V,
IC
= 50 Ω
V
O
= 1.5 V,
CMRR
dB
R
Full range
S
†
‡
Full range is − 40°C to 125°C.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓ
ꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 3 V (unless otherwise
DD
TLV2254I
TLV2254AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
Supply voltage
rejection ratio
25°C
80
95
80
100
V
V
= 2.7 V to 8 V,
DD
IC
k
dB
SVR
= V
/2,
No load
DD
Full range
80
80
(∆V
DD
/∆V )
IO
25°C
Full range
135
250
300
135
250
300
Supply current
(four amplifiers)
I
V
O
= 1.5 V,
No load
µA
DD
†
Full range is − 40°C to 125°C.
TLV2254I operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2254I
TLV2254AI
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
0.07
0.05
TYP
MAX
MIN
TYP
MAX
V
R
C
= 0.7 V to 1.7 V,
O
L
L
0.1
0.07
0.05
0.1
25°C
‡
= 100 kΩ ,
SR
Slew rate at unity gain
Equivalent input noise voltage
‡
Full range
25°C
= 100 pF
f = 10 Hz
35
19
35
19
nV/√Hz
V
n
f = 1 kHz
25°C
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
0.6
1.1
0.6
0.6
1.1
0.6
Peak-to-peak equivalent input
noise voltage
V
I
µV
N(PP)
25°C
Equivalent input noise current
25°C
fA/√Hz
n
f = 1 kHz,
‡
R
C
= 50 kΩ ,
Gain-bandwidth product
25°C
25°C
0.187
60
0.187
60
MHz
kHz
dB
L
L
‡
= 100 pF
V
A
R
= 1 V,
O(PP)
= 1,
Maximum output-swing
bandwidth
V
B
OM
‡
= 50 kΩ ,
L
L
‡
C
= 100 pF
‡
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
63°
63°
R
C
= 50 kΩ ,
L
L
‡
= 100 pF
15
15
†
‡
Full range is − 40°C to 85°C.
Referenced to 1.5 V
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254I electrical characteristics at specified free-air temperature, V
noted)
= 5 V (unless otherwise
DD
TLV2254I
TLV2254AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
200 1500
1750
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature
coefficient of input
offset voltage
25°C
to 85°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage
long-term drift
(see Note 4)
25°C
25°C
0.003
0.5
0.003
0.5
µV/mo
V
V
=
2.5 V,
V
= 0,
= 50 Ω
DD
= 0,
IC
R
60
60
O
S
−40°C
to 85°C
150
150
I
I
Input offset current
Input bias current
pA
IO
Full range
1000
60
1000
60
25°C
1
1
−40°C
to 85°C
150
150
pA
V
IB
Full range
1000
1000
0
−0.3
to 4 to 4.2
0
−0.3
to 4 to 4.2
25°C
Common-mode input
voltage range
V
|V | ≤5 mV,
IO
R
= 50 Ω
S
ICR
OH
0
0
Full range
to 3.5
to 3.5
I
I
I
= −20 µA
= −75 µA
= −150 µA
= 2.5 V,
25°C
25°C
4.98
4.94
4.98
4.94
OH
OH
OH
4.9
4.8
4.8
4.9
4.8
4.8
High-level output
voltage
V
V
Full range
25°C
4.88
0.01
4.88
0.01
25°C
V
V
V
I
I
I
= 50 µA
= 500 µA
= 1 ꢈA
IC
IC
IC
OL
OL
OL
Full range
25°C
0.06
0.15
0.15
0.3
0.06
0.15
0.15
0.3
0.09
0.2
0.09
0.2
Low-level output
voltage
V
= 2.5 V,
= 2.5 V,
V
OL
Full range
25°C
Full range
25°C
0.3
0.3
100
10
350
100
10
350
Large-signal
differential voltage
amplification
‡
R
R
= 100 kΩ
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
V/mV
VD
‡
1700
1700
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
N package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
200
83
200
83
25°C
70
70
70
70
Common-mode
rejection ratio
V
R
= 0 to 2.7 V,
= 50 Ω
V
O
= 2.5 V,
IC
CMRR
dB
Full range
S
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘ
ꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254I electrical characteristics at specified free-air temperature, V
noted) (continued)
= 5 V (unless otherwise
DD
TLV2254I
TLV2254AI
UNIT
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP MAX
MIN
TYP MAX
Supply voltage
rejection ratio
25°C
80
95
80
95
V
V
= 4.4 V to 8 V,
DD
IC
k
dB
SVR
= V
/2,
No load
DD
Full range
80
80
(∆V
DD
/∆V )
IO
25°C
140
250
300
140
250
300
Supply current
(four amplifiers)
I
V
O
= 2.5 V,
No load
µA
DD
Full range
†
Full range is − 40°C to 125°C.
TLV2254I operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2254I
TLV2254AI
†
PARAMETER
TEST CONDITIONS
UNIT
V/µs
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
0.07
0.12
0.07
0.12
‡
Slew rate at unity
gain
V
C
= 1.4 V to 2.6 V,
R
= 100 kΩ ,
L
O
L
SR
Full
range
‡
= 100 pF
0.05
0.05
f = 10 Hz
f = 1 kHz
25°C
25°C
36
19
36
19
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.1
0.7
1.1
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.2%
1%
0.2%
1%
O
V
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.2
30
0.2
30
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
‡
‡
C
= 100 pF
L
L
Phase margin at
unity gain
φ
m
25°C
25°C
63°
63°
‡
‡
R
= 50 kΩ ,
C
= 100 pF
L
Gain margin
15
15
dB
†
‡
Full range is − 40°C to 125°C.
Referenced to 2.5 V
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 3 V
DD
TLV2252Q,
TLV2252M
TLV2252AQ,
TLV2252AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
200 1500
1750
200
0.5
850
V
Input offset voltage
µV
IO
Full range
1000
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
0.5
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
=
1.5 V,
V
R
= 0,
= 50 Ω
S
DD
= 0,
IC
25°C
0.003
0.5
0.003
0.5
µV/mo
O
25°C
125°C
25°C
60
1000
60
60
1000
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
1000
1000
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
V
V
R
= 50 Ω,
|V | ≤5 mV
IO
V
V
ICR
OH
OL
S
0
to
1.7
0
to
1.7
Full range
I
I
I
= −20 µA
= −75 µA
25°C
25°C
2.98
2.98
OH
OH
OH
2.9
2.8
2.8
2.9
2.8
2.8
High-level output
voltage
Full range
25°C
= −150 µA
V
IC
= 1.5 V,
I
I
= 50 µA
25°C
10
10
OL
25°C
100
150
165
300
300
100
150
165
300
300
V
IC
= 1.5 V,
= 1.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
mV
200
250
800
200
250
800
V
IC
I
= 1 ꢈA
OL
Full range
25°C
100
10
100
10
‡
R
R
= 100 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 1.5 V,
= 1 V to 2 V
L
L
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
220
75
220
77
25°C
Full range
25°C
65
60
80
80
65
60
80
80
Common-mode rejection
ratio
V
O
= 1.5 V,
V
R
= 0 to 1.7 V,
= 50 Ω
IC
S
CMRR
dB
dB
µA
95
68
100
68
Supply voltage rejection
V
= 2.7 V to 8 V,
DD
k
SVR
ratio (∆V
DD
/∆V
IO
)
V
IC
= V
/2,
No load
Full range
25°C
DD
125
150
125
150
I
Supply current
V
O
= 1.5 V,
No load
DD
Full range
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓ
ꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252Q, and TLV2252M operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2252Q,
TLV2252M
TLV2252AQ,
TLV2252AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
TYP MAX
25°C
0.07
0.05
0.1
0.07
0.05
0.1
‡
V
C
= 0.8 V to 1.4 V,
‡
= 100 pF
R
= 100 kΩ ,
L
O
L
SR
Slew rate at unity gain
V/µs
Full
range
f = 10 Hz
f = 1 kHz
25°C
25°C
35
19
35
19
Equivalent input noise
voltage
nV/√Hz
µV
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.6
1.1
0.6
1.1
V
I
N(PP)
Equivalent input noise
current
25°C
25°C
0.6
0.6
fA/√Hz
n
‡
Gain-bandwidth
product
f = 1 kHz,
‡
R
= 50 kΩ ,
L
0.187
0.187
MHz
C
= 100 pF
L
Maximum
output-swing
bandwidth
V
R
= 1 V,
= 50 kΩ ,
A
C
= 1,
= 100 pF
O(PP)
L
V
B
25°C
60
60
kHz
dB
OM
‡
‡
L
L
Phase margin at unity
gain
φ
m
25°C
25°C
63°
63°
‡
‡
R
= 50 kΩ ,
C
= 100 pF
L
Gain margin
15
15
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 5 V
DD
TLV2252Q,
TLV2252M
TLV2252AQ,
TLV2252AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
200 1500
1750
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature coefficient
of input offset voltage
25°C
to 85°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage long-
term drift (see Note 4)
V
V
=
2.5 V,
V
= 0,
= 50 Ω
DD
= 0,
IC
R
25°C
0.003
0.5
0.003
0.5
µV/mo
S
O
25°C
125°C
25°C
60
1000
60
60
1000
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
1000
1000
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
V
V
|V | ≤5 mV,
IO
R
= 50 Ω
S
V
V
ICR
OH
OL
0
to
3.5
0
to
3.5
Full range
I
I
I
= −20 µA
= −75 µA
25°C
25°C
4.98
4.94
4.98
4.94
OH
OH
OH
4.9
4.8
4.8
4.9
4.8
4.8
High-level output voltage
Low-level output voltage
Full range
25°C
= −150 µA
4.88
0.01
0.09
4.88
0.01
0.09
V
IC
= 2.5 V,
I
I
= 50 µA
25°C
OL
25°C
0.15
0.15
0.3
0.15
0.15
0.3
V
= 2.5 V,
= 2.5 V,
= 500 µA
IC
OL
Full range
25°C
V
0.2
350
0.2
350
V
IC
I
= 1 ꢈA
OL
Full range
25°C
0.3
0.3
100
10
100
10
‡
R
R
= 100 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
1700
1700
= 1 MΩ
Differential input
resistance
12
10
12
10
Ω
Ω
r
r
25°C
25°C
25°C
25°C
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
P package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
200
83
200
83
25°C
Full range
25°C
70
70
80
80
70
70
80
80
Common-mode rejection
ratio
V
IC
V
O
= 0 to 2.7 V,
= 2.5 V,
CMRR
dB
dB
R
= 50 Ω
S
95
95
Supply voltage rejection
V
= 4.4 V to 8 V,
DD
k
SVR
ratio (∆V
DD
/∆V
IO
)
V
IC
= V
/2,
No load
Full range
DD
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓ
ꢗ
ꢁ
ꢑ
ꢘ
ꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2252Q, and TLV2252M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 5 V
DD
TLV2252Q,
TLV2252M
TLV2252AQ,
TLV2252AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
70 125
150
25°C
70
125
150
I
Supply current
V
O
= 2.5 V,
No load
µA
DD
Full range
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2252Q, and TLV2252M operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2252Q,
TLV2252M
TLV2252AQ,
TLV2252AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX MIN
TYP MAX
0.07
0.05
0.12
0.07
0.05
0.12
V
R
C
= 1.25 V to 2.75 V,
25°C
O
L
L
‡
= 100 kΩ ,
SR
Slew rate at unity gain
V/µs
Full
range
‡
= 100 pF
f = 10 Hz
f = 1 kHz
25°C
25°C
36
19
36
19
Equivalent input noise
voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.1
0.7
1.1
V
I
µV
N(PP)
Equivalent input noise
current
25°C
25°C
0.6
0.6
fA/√Hz
n
V
= 0.5 V to 2.5 V,
A
= 1
0.2%
1%
0.2%
1%
O
V
Total harmonic
distortion plus noise
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
f = 50 kHz,
R
= 50 kΩ ,
L
Gain-bandwidth product
25°C
25°C
0.2
30
0.2
30
MHz
kHz
‡
C
= 100 pF
L
Maximum output-swing
bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
‡
‡
C
= 100 pF
L
L
Phase margin at unity
gain
φ
m
25°C
25°C
63°
63°
‡
‡
R
= 50 kΩ ,
C
= 100 pF
L
Gain margin
15
15
dB
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 3 V
DD
TLV2254Q,
TLV2254M
TLV2254AQ,
TLV2254AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
200 1500
1750
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature coefficient
of input offset voltage
25°C
to 125°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage
long-
term drift (see Note 4)
V
V
=
1.5 V,
V
R
= 0,
= 50 Ω
S
DD
= 0,
IC
25°C
0.003
0.5
0.003
0.5
µV/mo
O
25°C
125°C
25°C
60
1000
60
60
1000
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
1000
1000
0
to
2
−0.3
to
2.2
0
to
2
−0.3
to
2.2
25°C
Common-mode input
voltage range
V
R
= 50 Ω,
|V | ≤5 mV
IO
V
V
ICR
S
0
to
1.7
0
to
1.7
Full range
I
I
I
= −20 µA
= −75 µA
25°C
25°C
2.98
2.98
OH
OH
OH
2.9
2.8
2.8
2.9
2.8
2.8
High-level output
voltage
V
V
OH
Full range
25°C
= −150 µA
V
IC
= 1.5 V,
I
I
= 50 µA
25°C
10
10
OL
25°C
100
150
165
300
300
100
150
165
300
300
V
IC
= 1.5 V,
= 1.5 V,
= 500 µA
Low-level output
voltage
OL
Full range
25°C
mV
OL
200
225
800
200
225
800
V
IC
I
= 1 ꢈA
OL
Full range
25°C
100
10
100
10
‡
R
R
= 100 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 1.5 V,
= 1 V to 2 V
L
L
Full range
25°C
A
VD
V/mV
‡
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
N package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
220
75
220
77
25°C
65
60
65
60
Common-mode
rejection ratio
V
R
= 0 to 1.7 V,
= 50 Ω
V
O
= 1.5 V,
IC
S
CMRR
dB
dB
Full range
Supply voltage
rejection ratio
25°C
80
80
95
80
80
100
V
V
= 2.7 V to 8 V,
= V
DD
DD
IC
k
SVR
/2,
No load
Full range
(∆V
DD
/∆V )
IO
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖ
ꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 3 V
DD
TLV2254Q,
TLV2254M
TLV2254AQ,
TLV2254AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
135 250
300
25°C
135
250
300
Supply current
(four amplifiers)
I
V
O
= 1.5 V,
No load
µA
DD
Full range
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2254Q, and TLV2254M operating characteristics at specified free-air temperature, V
= 3 V
DD
TLV2254Q,
TLV2254M
TLV2254AQ,
TLV2254AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
MIN
TYP
MAX
V
R
C
= 0.5 V to 1.7 V,
0.07
0.05
0.1
0.07
0.05
0.1
O
L
L
25°C
‡
= 100 kΩ ,
SR
Slew rate at unity gain
V/µs
‡
Full range
25°C
= 100 pF
f = 10 Hz
35
19
35
19
nV/√Hz
V
n
Equivalent input noise voltage
f = 1 kHz
25°C
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
0.6
1.1
0.6
0.6
1.1
0.6
Peak-to-peak equivalent input
noise voltage
V
I
µV
N(PP)
25°C
Equivalent input noise current
25°C
fA/√Hz
n
f = 1 kHz,
‡
R
C
= 50 kΩ ,
Gain-bandwidth product
25°C
25°C
0.187
60
0.187
60
MHz
kHz
dB
L
L
‡
= 100 pF
V
A
R
= 1 V,
O(PP)
= 1,
Maximum output-swing
bandwidth
V
B
OM
‡
= 50 kΩ ,
L
L
‡
C
= 100 pF
‡
φ
m
Phase margin at unity gain
Gain margin
25°C
25°C
63°
63°
R
C
= 50 kΩ ,
L
L
‡
= 100 pF
15
15
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 1.5 V
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, V
(unless otherwise noted)
= 5 V
DD
TLV2254Q,
TLV2254M
TLV2254AQ,
TLV2254AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
25°C
200 1500
1750
200
850
V
IO
Input offset voltage
µV
Full range
1000
Temperature coefficient
of input offset voltage
25°C
to 125°C
α
VIO
0.5
0.5
µV/°C
Input offset voltage
long-term drift
(see Note 4)
V
V
=
2.5 V,
V
= 0,
= 50 Ω
DD
= 0,
IC
R
25°C
0.003
0.5
0.003
0.5
µV/mo
O
S
25°C
125°C
25°C
60
1000
60
60
1000
60
I
I
Input offset current
Input bias current
pA
pA
IO
1
1
IB
125°C
1000
1000
0
to
4
−0.3
to
4.2
0
to
4
−0.3
to
4.2
25°C
Common-mode input
voltage range
V
|V | ≤5 mV,
IO
R
= 50 Ω
S
V
V
ICR
0
to
3.5
0
to
3.5
Full range
I
I
I
= −20 µA
= −75 µA
25°C
25°C
4.98
4.94
4.98
4.94
OH
OH
OH
4.9
4.8
4.8
4.9
4.8
4.8
High-level output
voltage
V
V
OH
Full range
25°C
= −150 µA
4.88
0.01
0.09
4.88
0.01
0.09
V
IC
= 2.5 V,
I
I
= 50 µA
25°C
OL
25°C
0.15
0.15
0.3
0.15
0.15
0.3
V
= 2.5 V,
= 2.5 V,
= 500 µA
Low-level output
voltage
IC
OL
Full range
25°C
V
OL
0.2
350
0.2
350
V
IC
I
= 1 ꢈA
OL
Full range
25°C
0.3
0.3
100
10
100
10
‡
R
R
= 100 kΩ
Large-signal differential
voltage amplification
V
IC
V
O
= 2.5 V,
= 1 V to 4 V
L
L
Full range
25°C
A
VD
V/mV
‡
1700
1700
= 1 MΩ
Differential input
resistance
12
10
12
10
r
r
25°C
25°C
25°C
25°C
Ω
Ω
i(d)
i(c)
Common-mode input
resistance
12
10
12
10
Common-mode input
capacitance
c
z
f = 10 kHz,
f = 25 kHz,
N package
8
8
pF
Ω
i(c)
o
Closed-loop output
impedance
A
V
= 10
200
83
200
83
25°C
70
70
70
70
Common-mode
rejection ratio
V
R
= 0 to 2.7 V,
= 50 Ω
V
= 2.5 V,
IC
O
CMRR
dB
Full range
S
Supply voltage
rejection ratio
25°C
80
80
95
80
80
95
V
V
= 4.4 V to 8 V,
DD
IC
k
dB
SVR
= V
/2,
No load
DD
Full range
(∆V
DD
/∆V )
IO
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at T = 150°C extrapolated
A
to T = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TLV2254Q, and TLV2254M electrical characteristics at specified free-air temperature, V
(unless otherwise noted) (continued)
= 5 V
DD
TLV2254Q,
TLV2254M
TLV2254AQ,
TLV2254AM
†
PARAMETER
TEST CONDITIONS
T
A
UNIT
MIN
TYP MAX
MIN
TYP MAX
140 250
300
25°C
140
250
300
Supply current
(four amplifiers)
I
V
O
= 2.5 V,
No load
µA
DD
Full range
†
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
TLV2254Q, and TLV2254M operating characteristics at specified free-air temperature, V
= 5 V
DD
TLV2254Q,
TLV2254M
TLV2254AQ,
TLV2254AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP MAX
MIN
TYP MAX
0.07
0.12
0.07
0.12
25°C
‡
Slew rate at unity
gain
V
= 0.5 V to 3.5 V,
R
= 100 kΩ ,
O
L
SR
V/µs
Full
range
‡
C = 100 pF
L
0.05
0.05
f = 10 Hz
f = 1 kHz
25°C
25°C
36
19
36
19
Equivalent input
noise voltage
nV/√Hz
V
n
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
25°C
0.7
1.1
0.7
1.1
V
I
µV
N(PP)
Equivalent input
noise current
25°C
25°C
0.6
0.6
fA/√Hz
n
Total harmonic
distortion plus
noise
V
= 0.5 V to 2.5 V,
A
= 1
0.2%
1%
0.2%
1%
O
V
f = 20 kHz,
THD + N
A
V
= 10
‡
R
= 50 kΩ
L
‡
Gain-bandwidth
product
f = 50 kHz,
R
= 50 kΩ ,
L
25°C
25°C
0.2
30
0.2
30
MHz
kHz
‡
C
= 100 pF
L
Maximum output-
swing bandwidth
V
R
= 2 V,
= 50 kΩ ,
A
= 1,
O(PP)
L
V
B
OM
‡
‡
C
= 100 pF
L
L
Phase margin at
unity gain
φ
m
25°C
25°C
63°
63°
‡
‡
R
= 50 kΩ ,
C
= 100 pF
L
Gain margin
15
15
dB
†
‡
Full range is −40°C to 125°C for Q level part, −55°C to 125°C for M level part.
Referenced to 2.5 V
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Distribution
vs Common-mode voltage
2 − 5
6, 7
V
IO
Input offset voltage
α
Input offset voltage temperature coefficient
Input bias and input offset currents
Distribution
8 − 11
12
VIO
I
/I
vs Free-air temperature
IB IO
vs Supply voltage
vs Free-air temperature
13
14
V
I
Input voltage
V
V
V
High-level output voltage
vs High-level output current
vs Low-level output current
vs Frequency
15, 18
16, 17, 19
20
OH
Low-level output voltage
OL
Maximum peak-to-peak output voltage
O(PP)
vs Supply voltage
vs Free-air temperature
21
22
I
Short-circuit output current
OS
V
Differential input voltage
vs Output voltage
vs Load resistance
23, 24
25
ID
A
VD
Differential voltage amplification
vs Frequency
vs Free-air temperature
26, 27
28, 29
A
Large-signal differential voltage amplification
Output impedance
VD
o
z
vs Frequency
30, 31
vs Frequency
vs Free-air temperature
32
33
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36
k
Supply-voltage rejection ratio
Supply current
SVR
I
vs Supply voltage
37, 38
DD
vs Load capacitance
vs Free-air temperature
39
40
SR
Slew rate
V
O
V
O
V
O
V
O
V
n
Inverting large-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Voltage-follower small-signal pulse response
Equivalent input noise voltage
41, 42
43, 44
45, 46
47, 48
49, 50
51
vs Frequency
Input noise voltage
Over a 10-second period
vs Frequency
Integrated noise voltage
52
THD + N
Total harmonic distortion plus noise
vs Frequency
53
vs Supply voltage
vs Free-air temperature
54
55
Gain-bandwidth product
Phase margin
vs Frequency
vs Load capacitance
26, 27
56
φ
m
Gain margin
vs Load capacitance
vs Load capacitance
vs Load capacitance
57
58
59
B
1
Unity-gain bandwidth
Overestimation of phase margin
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘ
ꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2252
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2252
INPUT OFFSET VOLTAGE
20
15
10
20
15
10
1020 Amplifiers From 1 Wafer Lot
1020 Amplifiers From 1 Wafer Lot
V
T
=
1.5 V
V
DD
=
2.5 V
T = 25°C
A
DD
= 25°C
A
5
0
5
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 2
Figure 3
DISTRIBUTION OF TLV2254
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2254
INPUT OFFSET VOLTAGE
35
30
25
20
15
35
30
682 Amplifiers From 1 Wafer Lot
682 Amplifiers From 1 Wafer Lot
V
T
=
1.5 V
V
T
=
2.5 V
DD
DD
= 25°C
= 25°C
A
A
25
20
15
10
5
10
5
0
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 4
Figure 5
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†
†
INPUT OFFSET VOLTAGE
INPUT OFFSET VOLTAGE
vs
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
1
1
V
R
T
= 5 V
= 50 Ω
= 25°C
V
R
T
= 3 V
= 50 Ω
= 25°C
DD
S
A
DD
S
A
0.8
0.8
0.6
0.4
0.2
0.6
0.4
0.2
0
−0.2
−0.4
0
−0.2
−0.4
−0.6
−0.8
−0.6
−0.8
−1
−1
−1
−1
0
1
2
3
4
5
0
1
2
3
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 6
Figure 7
DISTRIBUTION OF TLV2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
†
†
25
20
15
25
20
15
62 Amplifiers From 1 Wafer Lot
62 Amplifiers From 1 Wafer Lot
V
=
2.5 V
P Package
= 25°C to 85°C
V
=
1.5 V
P Package
= 25°C to 85°C
DD
DD
T
T
A
A
10
5
10
5
0
−2
0
−2
−1
0
1
2
−1
0
1
2
α
− Temperature Coefficient − µV/°C
α
− Temperature Coefficient − µV/°C
VIO
VIO
Figure 8
Figure 9
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLV2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
25
20
15
10
25
20
15
10
62 Amplifiers From 1 Wafer Lot
62 Amplifiers From 1 Wafer Lot
V
=
1.5 V
P Package
= 25°C to 85°C
DD
V
=
2.5 V
P Package
= 25°C to 85°C
DD
T
A
T
A
5
0
5
0
−2
−1
0
1
2
−2
−1
0
1
2
α
− Temperature Coefficient
α
− Temperature Coefficient
VIO
VIO
of Input Offset Voltage − µV/°C
of Input Offset Voltage − µV/°C
Figure 10
Figure 11
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
†
INPUT BIAS AND INPUT OFFSET CURRENTS
vs
FREE-AIR TEMPERATURE
2.5
35
30
25
R
T
= 50 Ω
= 25°C
V
V
V
= 2.5 V
= 0
= 0
= 50 Ω
S
A
DD
IC
O
2
1.5
1
R
S
0.5
0
20
15
10
5
| V | ≤5 mV
IO
−0.5
−1
I
IB
−1.5
−2
I
IO
−2.5
0
25
1
1.5
2
2.5
3
3.5
4
45
65
85
105
125
| V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 12
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†‡
†‡
INPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5
4
3
2
1
3
2.5
2
V
DD
= 5 V
V
= 3 V
DD
T
= −40°C
= 25°C
A
T
A
| V | ≤5 mV
IO
1.5
1
T
= 85°C
A
T
A
= 125°C
0
0.5
0
−1
−55 −35 −15
5
25
45
65 85 105 125
0
200
400
600
800
T
A
− Free-Air Temperature − °C
| I
OH
| − High-Level Output Current − µA
Figure 14
Figure 15
†‡
‡
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
1.4
1.2
1
1.2
1
V
T
= 3 V
V
V
= 3 V
= 1.5 V
DD
= 25°C
DD
IC
A
T
= 125°C
= 85°C
A
V
= 0
IC
0.8
0.6
0.4
0.2
0
T
A
0.8
0.6
V
IC
= 0.75 V
T
= 25°C
A
V
IC
= 1.5 V
0.4
T
A
= − 40°C
0.2
0
0
1
2
3
4
5
0
1
2
3
4
5
I − Low-Level Output Current − mA
OL
I
− Low-Level Output Current − mA
OL
Figure 16
Figure 17
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖ
ꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†‡
†‡
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5
4
3
1.4
1.2
V
V
= 5 V
V
= 5 V
DD
= 2.5 V
DD
T
= 125°C
A
IC
1
T
= −40°C
= 25°C
= 85°C
T
A
= 85°C
A
0.8
T
A
= 25°C
T
A
0.6
0.4
0.2
0
2
1
0
T
A
T
= −40°C
A
T
= 125°C
A
0
200
400
600
800
0
1
2
3
4
5
6
| I
OH
| − High-Level Output Current − µA
I
− Low-Level Output Current − mA
OL
Figure 18
Figure 19
‡
SHORT-CIRCUIT OUTPUT CURRENT
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
FREQUENCY
10
9
8
7
6
5
4
3
2
1
5
R = 50 kΩ
V
= 5 V
I
DD
DD
T
= 25°C
A
4
V
= −100 mV
ID
3
2
V
= 3 V
V
= V /2
DD
O
T
= 25°C
A
V
IC
= V /2
DD
1
0
V
= 100 mV
0
ID
−1
2
3
4
5
6
7
8
2
3
4
5
10
10
10
10
V
− Supply Voltage − V
DD
f − Frequency − Hz
Figure 20
Figure 21
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V = 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD DD
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
‡
†
DIFFERENTIAL INPUT VOLTAGE
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
11
1000
800
V
= 3 V
V
V
= 2.5 V
DD
I
O
10
9
R = 50 kΩ
=
5 V
DD
V
T
A
= 1.5 V
= 25°C
IC
600
8
V
ID
= −100 mV
400
7
6
5
4
200
0
−200
−400
−600
−800
3
2
1
V
ID
= 100 mV
0
−1
−75
−1000
0
0.5
1
1.5
2
2.5
3
−50 −25
0
25
50
75
100 125
V
O
− Output Voltage − V
T
A
− Free-Air Temperature − °C
Figure 22
Figure 23
‡
DIFFERENTIAL INPUT VOLTAGE
†‡
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
OUTPUT VOLTAGE
LOAD RESISTANCE
1000
800
4
10
3
10
2
10
1
10
V
T
= 2 V
V
V
R
= 5 V
O(PP)
= 25°C
DD
IC
L
= 2.5 V
= 50 kΩ
= 25°C
A
600
T
A
400
V
DD
= 5 V
V
200
0
= 3 V
DD
−200
−400
−600
−800
−1000
1
1
10
2
3
10
1
10
0
1
2
3
4
5
V
O
− Output Voltage − V
R
− Load Resistance − kΩ
L
Figure 24
Figure 25
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
180°
135°
V
R
= 5 V
= 50 kΩ
DD
L
L
C = 100 pF
T
A
= 25°C
40
90°
45°
Phase Margin
20
0
Gain
0°
−20
−40
−45°
−90°
3
4
5
6
7
10
10
10
10
10
†
f − Frequency − Hz
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
80
60
180°
135°
V
= 3 V
DD
R = 50 kΩ
L
L
C = 100 pF
T
A
= 25°C
40
90°
45°
Phase Margin
20
0
Gain
0°
−20
−40
−45°
−90°
3
4
5
6
7
10
10
10
10
10
f − Frequency − Hz
Figure 27
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†‡
†‡
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4
3
4
3
10
10
10
10
V
V
V
= 5 V
= 2.5 V
= 1 V to 4 V
DD
IC
O
V
V
V
= 3 V
= 1.5 V
= 0.5 V to 2.5 V
DD
IC
O
R
= 1 MΩ
L
R
= 1 MΩ
= 50 kΩ
L
R
R
= 50 kΩ
L
L
2
2
1
10
10
10
1
10
−75 −50 −25
0
25
50
75
100 125
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 28
Figure 29
‡
‡
OUTPUT IMPEDANCE
OUTPUT IMPEDANCE
vs
vs
FREQUENCY
FREQUENCY
1000
100
10
1000
100
10
V
T
= 5 V
= 25°C
V
T
= 3 V
= 25°C
DD
A
DD
A
A
= 100
V
A
= 100
V
A
= 10
= 1
A
= 10
= 1
V
V
1
1
A
V
A
V
0.1
10
0.1
10
2
3
4
5
6
2
3
4
5
6
10
10
10
10
10
10
10
10
f− Frequency − Hz
f− Frequency − Hz
Figure 30
Figure 31
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
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ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†‡
†
COMMON-MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
100
80
94
92
90
88
86
84
82
V
V
= 5 V
= 2.5 V
T
A
= 25°C
DD
IC
V
V
= 3 V
= 1.5 V
DD
IC
V
DD
= 5 V
60
40
20
0
V
DD
= 3 V
80
4
5
6
10
1
2
3
10
10
10
10
10
− 75 − 50 − 25
0
25
50
75 100
125
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 32
Figure 33
†
†
SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
80
100
80
60
40
20
V
T
= 3 V
V
T
= 5 V
= 25°C
DD
= 25°C
DD
A
k
SVR+
A
60
k
SVR+
k
SVR−
40
k
SVR−
20
0
0
−20
−20
1
2
3
4
5
6
10
6
1
2
3
4
5
10
10
10
10
10
10
10
10
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 34
Figure 35
†
‡
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
= 3 V, all loads are referenced to 1.5 V.
DD
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢂꢃ ꢃꢄ ꢅ ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
TLV2252
SUPPLY CURRENT
vs
†
†
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
110
105
120
100
80
60
40
20
0
V
V
= 2.7 V to 8 V
DD
= V = V /2
DD
V
= 0
O
IC
O
No Load
T
= −40°C
= 85°C
A
100
95
T
A
T
A
= 25°C
90
−75 −50 −25
0
25
50
75 100
125
0
1
2
3
4
5
6
7
8
T
A
− Free-Air Temperature − °C
V
DD
− Supply Voltage − V
Figure 36
Figure 37
TLV2254
SUPPLY CURRENT
†
‡
SLEW RATE
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
0.2
0.18
0.16
0.14
0.12
0.1
240
200
160
120
80
V
= 5 V
DD
= −1
V
= 0
O
A
V
A
No Load
T
= 25°C
T
= −40°C
A
SR−
T
= 85°C
A
SR+
T
A
= 25°C
0.08
0.06
0.04
40
0.02
0
0
1
2
3
4
10
0
1
2
3
4
5
6
7
8
10
10
10
| V
DD
| − Supply Voltage − V
C
− Load Capacitance − pF
L
Figure 38
Figure 39
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†‡
SLEW RATE
vs
INVERTING LARGE-SIGNAL PULSE
†
FREE-AIR TEMPERATURE
RESPONSE
0.2
3
2.5
2
V
= 5 V
= 50 kΩ
= 100 pF
= 1
DD
V
= 3 V
= 50 kΩ
= 100 pF
= −1
DD
R
C
A
L
L
V
R
C
A
L
L
V
0.16
T
A
= 25°C
SR−
0.12
0.08
1.5
1
SR+
0.04
0
0.5
0
0
10 20 30 40 50 60 70 80 90 100
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
t − Time − µs
Figure 40
Figure 41
INVERTING LARGE-SIGNAL PULSE
VOLTAGE-FOLLOWER LARGE-SIGNAL
†
†
RESPONSE
PULSE RESPONSE
5
3
2.5
2
V
R
C
A
= 5 V
V
= 3 V
= 50 kΩ
= 100 pF
= 1
DD
L
L
DD
= 50 kΩ
= 100 pF
= −1
R
C
A
T
L
L
V
4
3
2
V
= 25°C
T
A
= 25°C
A
1.5
1
1
0
0.5
0
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
t − Time − µs
t − Time − µs
Figure 42
Figure 43
†
‡
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
For all curves where V = 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD DD
33
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ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢇ
ꢔ
ꢁ
ꢕ
ꢀ
ꢑ
ꢕ
ꢓ
ꢇ
ꢔ
ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER LARGE-SIGNAL
INVERTING SMALL-SIGNAL
†
†
PULSE RESPONSE
PULSE RESPONSE
0.95
0.9
5
4
V
= 5 V
= 50 kΩ
= 100 pF
= 1
V
= 3 V
DD
L
L
DD
L
L
R
C
A
R
C
A
= 50 kΩ
= 100 pF
= −1
V
A
V
A
T
= 25°C
T
= 25°C
0.85
0.8
3
2
0.75
0.7
1
0
0.65
0.6
0
10
20
30
40
50
0
10 20 30 40 50 60 70 80 90 100
t − Time − µs
t − Time − µs
Figure 44
Figure 45
VOLTAGE-FOLLOWER SMALL-SIGNAL
INVERTING SMALL-SIGNAL
†
†
PULSE RESPONSE
PULSE RESPONSE
0.95
2.65
2.6
V
= 3 V
= 50 kΩ
= 100 pF
= 1
V
= 5 V
DD
L
L
DD
L
L
R
C
A
R
C
A
= 50 kΩ
= 100 pF
= −1
0.9
0.85
0.8
V
A
V
A
T
= 25°C
T
= 25°C
2.55
2.5
0.75
0.7
2.45
2.4
0.65
0.6
0
10
20
30
40
50
0
10
20
30
40
50
t − Time − µs
t − Time − µs
Figure 46
Figure 47
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†
EQUIVALENT INPUT NOISE VOLTAGE
vs
VOLTAGE-FOLLOWER SMALL-SIGNAL
†
FREQUENCY
PULSE RESPONSE
60
50
2.65
2.6
V
R
C
= 5 V
= 50 kΩ
= 100 pF
= 1
DD
L
L
V
R
T
A
= 3 V
= 20 Ω
= 25°C
DD
S
A
V
A
T
= 25°C
40
30
2.55
2.5
20
10
0
2.45
2.4
1
2
3
4
10
10
10
10
0
10
20
30
40
50
f − Frequency − Hz
t − Time − µs
Figure 48
Figure 49
†
EQUIVALENT INPUT NOISE VOLTAGE
INPUT NOISE VOLTAGE OVER
vs
†
A 10-SECOND PERIOD
FREQUENCY
1000
750
500
250
0
60
50
40
30
20
V
R
T
A
= 5 V
= 20 Ω
= 25°C
DD
S
V
= 5 V
DD
f = 0.1 Hz to 10 Hz
T
A
= 25°C
−250
−500
10
0
−750
−1000
1
2
3
4
10
0
2
4
6
8
10
10
10
10
f − Frequency − Hz
t − Time − s
Figure 50
Figure 51
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V = 3 V, all loads are referenced to 1.5 V.
DD
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
†
†
INTEGRATED NOISE VOLTAGE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
100
1
Calculated Using Ideal Pass-Band Filter
Low Frequency = 1 Hz
A
V
= 100
T
= 25°C
A
10
0.1
A
V
= 10
1
0.01
A
V
= 1
V
R
T
A
= 5 V
= 50 kΩ
= 25°C
DD
L
0.001
0.1
1
2
3
4
5
1
10
2
3
4
5
10
10
10
10
10
10
1
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 52
Figure 53
†‡
GAIN-BANDWIDTH PRODUCT
vs
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
300
260
V
DD
= 5 V
220
210
200
f = 10 kHz
R
C
= 50 kHz
= 100 pF
L
L
220
180
140
100
190
180
170
−75 −50 −25
0
25
50
75
100
125
0
1
2
V
3
4
5
6
7
8
T
A
− Free-Air Temperature − °C
− Supply Voltage − V
DD
Figure 54
Figure 55
†
For all curves where V
DD
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
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ꢆ
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ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓ
ꢗ
ꢁ
ꢑ
ꢘ
ꢕ
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ꢔ
ꢑ
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ꢁ
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ꢐ
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ꢛ
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ꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN MARGIN
vs
LOAD CAPACITANCE
75°
60°
45°
20
15
10
T
A
= 25°C
R
= 200 Ω
null
R
= 500 Ω
null
R
= 500 Ω
null
R
= 200 Ω
= 100 Ω
null
R
= 100 Ω
R
null
null
R
= 50 Ω
= 10 Ω
null
R
= 50 Ω
= 10 Ω
null
30°
R
null
R
null
50 kΩ
5
0
V
15°
0°
DD +
DD −
R
= 0
null
50 kΩ
R
null
R
= 0
V
−
+
null
I
C
L
T
= 25°C
A
V
1
2
3
4
10
10
10
10
1
2
L
3
4
5
10
10
10
C
10
10
C
− Load Capacitance − pF
− Load Capacitance − pF
L
Figure 56
Figure 57
†
OVERESTIMATION OF PHASE MARGIN
vs
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
25
T
= 25°C
200
175
150
A
T
A
= 25°C
R
= 500 Ω
null
20
15
10
5
125
100
R
= 100 Ω
null
R
= 200 Ω
null
R
= 50 Ω
= 10 Ω
null
75
50
R
null
25
0
10
1
2
3
4
5
10
10
10
10
0
10
1
2
3
4
5
10
10
C
10
10
C − Load Capacitance − pF
L
− Load Capacitance − pF
†
L
See application information
Figure 58
Figure 59
†
‡
For all curves where V
= 5 V, all loads are referenced to 2.5 V. For all curves where V
= 3 V, all loads are referenced to 1.5 V.
DD
DD
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢈ
ꢁ
ꢎ
ꢋ
ꢂ ꢖꢓꢗ ꢁ ꢑꢘꢕꢙ ꢑꢘꢖ ꢓ ꢑ ꢙꢖ ꢓꢇꢀꢔ ꢑ ꢚꢇ ꢁ ꢇꢐ ꢙꢁ ꢔꢛ ꢔꢖ ꢓꢒ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓꢇ ꢔ ꢁꢕꢀꢑ ꢕꢓꢇꢔ ꢁ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
APPLICATION INFORMATION
driving large capacitive loads
The TLV2252 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(R
= 0).
null
A smaller series resistor (R ) at the output of the device (see Figure 60) improves the gain and phase margins
null
when driving large capacitive loads. Figure 55 and Figure 56 show the effects of adding series resistances of
10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first adds a zero
to the transfer function and the second reduces the frequency of the pole associated with the output load in the
transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
–1
ǒ2 × π × UGBW × R
LǓ
(1)
∆φ
Where :
+ tan
× C
m1
null
∆φ
+ improvement in phase margin
m1
UGBW + unity-gain bandwidth frequency
R
+ output series resistance
+ load capacitance
null
C
L
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 kΩ
V
DD+
50 kΩ
R
null
V
I
−
+
C
L
V
DD−
/GND
Figure 60. Series-Resistance Circuit
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢑ
ꢁ
ꢂ
ꢃ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢓꢇꢔ ꢁꢕ ꢀꢑ ꢕꢓ ꢇ ꢔꢁ
ꢃ
ꢄ
ꢅ
ꢇ
ꢜ
ꢇ
ꢈ
ꢉ
ꢘ
ꢊ
ꢖ
ꢋ
ꢓ
ꢌ
ꢍ
ꢑ
ꢈ
ꢙ
ꢁ
ꢖ
ꢎ
ꢋ
ꢓ
ꢏ
ꢇ
ꢐ
ꢀ
ꢒ
ꢂ
ꢖ
ꢓꢗ
ꢁ
ꢑ
ꢘꢕ
ꢙ
ꢑ
ꢔ
ꢑ
ꢚ
ꢇ
ꢁ
ꢇ
ꢐ
ꢙ
ꢁ
ꢔ
ꢛ
ꢔ
ꢖꢓ
ꢒ
SLOS185D − FEBRUARY 1997 − REVISED AUGUST 2006
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 61 are generated using
the TLV2252 typical electrical and operating characteristics at T = 25°C. Using this information, output
A
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
DLN
3
EGND
+
−
V
CC+
92
9
FB
+
91
90
RSS
ISS
RO2
−
+
−
+
VB
DLP
RP
2
VLP
VLN
HLIM
−
+
−
10
+
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
−
DE
VAD
5
54
V
CC−
−
+
4
VE
OUT
.SUBCKT TLV225x 1 2 3 4 5
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
60
60
8
11
12
5
37.23E3
37.23E3
84
C1
11
6
12
7
6.369E−12
C2
25.00E−12
DC
5
53
5
DX
DX
DX
DX
DX
7
99
4
84
DE
54
90
92
4
3
71.43E3
64.52E6
−.5
DLP
DLN
DP
91
90
3
10
60
9
99
4
0
DC 0
EGND
FB
99
7
0
99
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
3
53
4
DC .605
DC .605
DC 0
54
7
+ VLN 0 57.62E6 −60E6 60E6 60E6 −60E6
VLIM
VLP
VLN
8
GA
6
0
6
11
10
12 26.86E−6
99 2.686E−9
91
0
0
DC −0.235
DC 7.5
GCM
ISS
HLIM
J1
0
92
3
10
0
DC 3.1E−6
VLIM 1K
10 JX
10 JX
100.0E3
.MODEL DX D (IS=800.0E−18)
90
11
12
6
.MODEL JX PJF (IS=500.0E−15 BETA=139E−6
2
1
+ VTO=−.05)
.ENDS
J2
R2
9
Figure 61. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
FK
U
5962-9550401Q2A
5962-9550401QHA
5962-9550401QPA
5962-9550403Q2A
5962-9550403QHA
5962-9550403QPA
5962-9566601Q2A
5962-9566601QHA
5962-9566601QPA
5962-9566602Q2A
5962-9566602QCA
5962-9566602QDA
5962-9566603Q2A
5962-9566603QHA
5962-9566603QPA
5962-9566604Q2A
5962-9566604QCA
5962-9566604QDA
TLV2252AID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
20
10
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CFP
JG
FK
U
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CDIP
CFP
JG
FK
J
20
14
14
20
10
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
LCCC
CFP
FK
U
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
CDIP
LCCC
CDIP
CFP
JG
FK
J
20
14
14
8
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252AIDG4
TLV2252AIDR
TLV2252AIDRG4
TLV2252AIP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TLV2252AIPE4
TLV2252AIPW
TLV2252AIPWG4
PDIP
P
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
TSSOP
TSSOP
PW
PW
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
150 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252AIPWLE
TLV2252AIPWR
OBSOLETE TSSOP
PW
PW
8
8
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252AIPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252AMFKB
TLV2252AMJGB
TLV2252AQD
ACTIVE
ACTIVE
NRND
LCCC
CDIP
SOIC
FK
JG
D
20
8
1
1
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB N / A for Pkg Type
8
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2252AQDG4
TLV2252AQDR
ACTIVE
NRND
SOIC
SOIC
D
D
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500
Pb-Free
CU NIPDAU Level-2-250C-1 YEAR/
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
(RoHS)
Level-1-235C-UNLIM
TLV2252AQDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252CP
TLV2252ID
ACTIVE
ACTIVE
PDIP
SOIC
P
D
8
8
TBD
Call TI
Call TI
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252IDG4
TLV2252IDR
TLV2252IDRG4
TLV2252IP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2252IPE4
50
Pb-Free
(RoHS)
TLV2252MFKB
TLV2252MJGB
TLV2252MUB
TLV2252QD
ACTIVE
ACTIVE
ACTIVE
NRND
LCCC
CDIP
CFP
FK
JG
U
20
8
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
10
8
1
SOIC
SOIC
D
75
CU NIPDAU Level-1-220C-UNLIM
TLV2252QDG4
ACTIVE
D
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2252QDR
NRND
SOIC
SOIC
D
D
8
8
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2252QDRG4
ACTIVE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254AID
TLV2254AIDG4
TLV2254AIDR
TLV2254AIDRG4
TLV2254AIN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
14
14
14
14
14
14
50 Green (RoHS &
no Sb/Br)
Call TI
Call TI
Call TI
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
50 Green (RoHS &
no Sb/Br)
SOIC
D
2500 Green (RoHS &
no Sb/Br)
SOIC
D
2500 Green (RoHS &
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
TLV2254AINE4
TLV2254AIPW
TLV2254AIPWG4
PDIP
N
25
Pb-Free
(RoHS)
TSSOP
TSSOP
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254AIPWLE
TLV2254AIPWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254AIPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254AMFKB
TLV2254AMJB
TLV2254AMWB
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
Drawing
TLV2254AQD
ACTIVE
ACTIVE
D
D
14
14
50
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2254AQDG4
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254AQDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2254AQDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254ID
TLV2254IDG4
TLV2254IDR
TLV2254IDRG4
TLV2254IN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
D
N
N
14
14
14
14
14
14
50 Green (RoHS &
no Sb/Br)
Call TI
Call TI
Call TI
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
50 Green (RoHS &
no Sb/Br)
2500 Green (RoHS &
no Sb/Br)
2500 Green (RoHS &
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
POST-PLATE N / A for Pkg Type
TLV2254INE4
25
Pb-Free
(RoHS)
TLV2254MFKB
TLV2254MJB
TLV2254MWB
TLV2254QD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
14
14
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
D
1
SOIC
SOIC
50
CU NIPDAU Level-1-220C-UNLIM
TLV2254QDG4
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2254QDR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
TLV2254QDRG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262AMFKB
TLV2262AMJGB
TLV2262AMUB
TLV2262MFKB
TLV2262MJGB
TLV2262MUB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
JG
U
20
8
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
10
20
8
LCCC
CDIP
CFP
FK
JG
U
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
10
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
(mm)
12
TLV2252AIDR
TLV2252AIPWR
TLV2252IDR
D
PW
D
8
8
SITE 60
SITE 41
SITE 60
SITE 60
SITE 41
SITE 60
6.4
7.0
6.4
6.5
7.0
6.5
5.2
3.6
5.2
9.0
5.6
9.0
2.1
1.6
2.1
2.1
1.6
2.1
8
8
8
8
8
8
12
12
12
16
12
16
Q1
Q1
Q1
Q1
Q1
Q1
12
8
12
TLV2254AIDR
TLV2254AIPWR
TLV2254IDR
D
14
14
14
16
PW
D
12
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
TLV2252AIDR
TLV2252AIPWR
TLV2252IDR
D
PW
D
8
8
SITE 60
SITE 41
SITE 60
SITE 60
SITE 41
SITE 60
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
29.0
29.0
29.0
33.0
29.0
33.0
8
TLV2254AIDR
TLV2254AIPWR
TLV2254IDR
D
14
14
14
PW
D
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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