TLV2264A-Q1 [TI]
汽车类四路、高级 LinCMOS、轨到轨精密运算放大器;
| 型号： | TLV2264A-Q1 |
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TEXAS INSTRUMENTS |
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TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193–DECEMBER 2008
Advanced LinCMOS™ RAIL-TO-RAIL OPERATIONAL AMPLIFIERS
1
FEATURES
TLV2262A
PW PACKAGE
(TOP VIEW)
23
•
Qualified for Automotive Applications
Output Swing Includes Both Supply Rails
Low Noise . . . 12 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
•
•
•
•
1OUT
1IN-
1
2
3
4
8
7
6
5
VDD+
2OUT
2IN-
Fully Specified for Both Single-Supply and
Split-Supply Operation
1IN+
V
DD- /GND
2IN+
•
•
Low Power . . . 500 µA Max
Common-Mode Input Voltage Range Includes
Negative Rail
TLV2264A
PW PACKAGE
(TOP VIEW)
•
Low Input Offset Voltage . . .
950 µV Max at TA = 25°C
1
2
3
14
13
12
•
•
Wide Supply Voltage Range . . . 2.7 V to 8 V
Macromodel Included
1OUT
1IN
4OUT
4IN
+
+
1IN
4IN
4
5
6
7
11
10
9
VDD+
V
DD- /GND
+
+
-
2IN
3IN
3IN
-
2IN
8
2OUT
3OUT
DESCRIPTION
The TLV2262 and TLV2264 are dual and quad low voltage operational amplifiers from Texas Instruments. Both
devices exhibit rail-to-rail output performance for increased dynamic range in single or split supply applications.
The TLV226x family offers a compromise between the micropower TLV225x and the ac performance of the
TLC227x. It has low supply current for battery-powered applications, while still having adequate ac performance
for applications that demand it. This family is fully characterized at 3 V and 5 V and is optimized for low-voltage
applications. The noise performance has been dramatically improved over previous generations of CMOS
amplifiers. Figure 1 depicts the low level of noise voltage for this CMOS amplifier, which has only 200 µA (typ) of
supply current per amplifier.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Advanced LinCMOS is a trademark of Texas Instruments.
Parts, PSpice are trademarks of MicroSim Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLV2262A-Q1, TLV2264A-Q1
SGLS193–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
V
DD
= 3 V
3.5
3
T = −55°C
A
2.5
2
T = 125°C
A
T = 25°C
A
1.5
1
T = 85°C
A
T = −40°C
A
0.5
0
0
500
1000
1500
2000
| I | − High-Level Output Current − µA
OH
Figure 1.
The TLV226x, exhibiting high input impedance and low noise, are excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric transducers. Because of the micropower dissipation levels
combined with 3-V operation, these devices work well in hand-held monitoring and remote-sensing applications.
In addition, the rail-to-rail output feature with single or split supplies makes this family a great choice when
interfacing with analog-to-digital converters (ADCs). For precision applications, the TLV226xA family is available
and has a maximum input offset voltage of 950 µV.
The TLV2262/4 also makes great upgrades to the TLV2332/4 in standard designs. They offer increased output
dynamic range, lower noise voltage and lower input offset voltage. This enhanced feature set allows them to be
used in a wider range of applications. For applications that require higher output drive and wider input voltage
range, see the TLV2432 and TLV2442 devices. If your design requires single amplifiers, please see the
TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23 package. Their
small size and low power consumption make them ideal for high density, battery-powered equipment.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
TSSOP – PW (8 pin)
TSSOP – PW (14 pin)
ORDERABLE PART NUMBER
TLV2262AQPWRQ1
TOP-SIDE MARKING
TQ262A
P2264AQ
Reel of 2000
Reel of 2000
–40°C to 125°C
TLV2264AQPWRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193–DECEMBER 2008
EQUIVALENT SCHEMATIC (EACH AMPLIFIER)
V
DD+
Q3
Q6
Q9
Q12
Q14
Q16
R6
IN+
IN−
OUT
C1
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
R3
Q5
R4
Q7
Q8
Q10
Q11
R1
R2
V
DD−/ GND
Table 1. Actual Device Component Count
COMPONENT
Transistors
TLV2262
TLV2264
38
28
9
76
54
18
6
Resistors
Diodes
Capacitors
3
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SGLS193–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VDD
VID
VI
Supply voltage(2)
Differential input voltage(3)
–0.3 V to 16 V
±VDD
Input voltage range
(VDD– – 0.3 V) to VDD+
±5 mA
II
Input current, any input
IO
Output current
±50 mA
Total current into VDD+
±50 mA
Total current out of VDD–
±50 mA
Duration of short-circuit current (at or below) 25°C(4)
Continuous total power dissipation
Operating free-air temperature range
Storage temperature range
Unlimited
PD
TA
See Dissipation Rating Table
–40°C to 125°C
–65°C to 150°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to VDD–
.
(3) Differential voltages are at the noninverting input with respect to the inverting input. Excessive current flows when input is brought below
VDD– – 0.3 V.
(4) The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PACKAGE
POWER RATING
PW-8
525 mW
4.2 mW/°C
5.6 mW/°C
273 mW
364 mW
105 mW
140 mW
PW-14
700 mW
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
VDD±
VI
Supply voltage(1)
2.7
8
V
V
Input voltage
VDD– VDD+ –1.3
VDD– VDD+ –1.3
VIC
TA
Common-mode input voltage
Operating free-air temperature
V
–40
125
°C
(1) All voltage values, except differential voltages, are with respect to VDD–
.
4
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193–DECEMBER 2008
TLV2262A ELECTRICAL CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
300
950
mV
VIO
Input offset voltage
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
Full range
1500
Temperature coefficient
of input offset voltage
αVIO
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
25°C to 125°C
25°C
2
µV/°C
Input offset voltage long-term
drift(1)
0.003
0.5
µV/mo
25°C
125°C
25°C
60
pA
IIO
Input offset current
Input bias current
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
800
1
60
pA
IIB
125°C
800
0
–0.3
25°C
to 2 to 2.2
Common-mode input voltage
range
VICR
RS = 50 Ω, | VIO | ≤ 5 mV
V
0
Full range
to 1.7
IOH = –20 µA
IOH = –100 µA
25°C
25°C
2.99
2.85
2.82
2.7
VOH
High-level output voltage
Low-level output voltage
Full range
25°C
V
IOH = –400 µA
Full range
25°C
2.55
IOL = 50 µA
10
25°C
100
150
IOL = 500 µA
VOL
VIC = 1.5 V
Full range
25°C
165
300
300
mV
200
100
IOL = 1 mA
Full range
25°C
60
25
RL = 50 kΩ(2)
Large-signal differential
voltage amplification
AVD
VIC = 1.5 V, VO = 1 V to 2 V
Full range
25°C
V/mV
RL = 1 MΩ(2)
100
ri(d)
ri(c)
ci(c)
zo
Differential input resistance
25°C
1012
Ω
Ω
Common-mode input
resistance
25°C
25°C
25°C
1012
Common-mode input
capacitance
f = 10 kHz
8
pF
Closed-loop output
impedance
f = 100 kHz, AV = 10
270
77
Ω
25°C
Full range
25°C
65
60
80
80
Common-mode rejection
ratio
CMRR
kSVR
IDD
VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω
VDD = 2.7 V to 8 V, VIC = VDD/2, No load
VO = 1.5 V, No load
dB
dB
µA
100
400
Supply voltage rejection ratio
(ΔVDD/ΔVIO
)
Full range
25°C
500
500
Supply current
Full range
(1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(2) Referenced to 1.5 V
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TLV2262A-Q1, TLV2264A-Q1
SGLS193–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
TLV2262A OPERATING CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
25°C
MIN
0.35
0.25
TYP
MAX
UNIT
VO = 0.5 V to 1.7 V, RL = 50 kΩ(1)
,
0.55
SR
Vn
Slew rate at unity gain
V/µs
CL = 100 pF(1)
Full range
25°C
f = 10 Hz
43
12
Equivalent input noise
voltage
nV/√Hz
f = 1 kHz
25°C
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
0.6
Peak-to-peak equivalent
input noise voltage
VN(PP)
In
µV
fA/√Hz
%
25°C
1
Equivalent input noise current
25°C
0.6
AV = 1
AV = 10
f = 1 kHz, RL = 50 kΩ(1), CL = 100 pF(1)
25°C
0.03
0.05
0.67
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
THD+N
noise
RL = 50 kΩ(1)
25°C
Gain-bandwidth product
25°C
MHz
kHz
Maximum output-swing
bandwidth
VO(PP) = 1 V, AV = 1, RL = 50 kΩ(1)
,
BOM
ts
25°C
395
CL = 100 pF(1)
To 0.1%
25°C
25°C
25°C
25°C
5.6
12.5
55
AV = –1, Step = 1 V to 2 V,
Settling time
µs
RL = 50 kΩ(1), CL = 100 pF(1)
To 0.01%
φm
Phase margin at unity gain
Gain margin
RL = 50 kΩ(1), CL = 100 pF(1)
RL = 50 kΩ(1), CL = 100 pF(1)
°
Gm
11
dB
(1) Referenced to 1.5 V
6
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193–DECEMBER 2008
TLV2262A ELECTRICAL CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
300
950
mV
VIO
Input offset voltage
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
Full range
1500
Temperature coefficient
of input offset voltage
αVIO
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
25°C to 125°C
25°C
2
µV/°C
Input offset voltage long-term
drift(1)
0.003
0.5
µV/mo
25°C
125°C
25°C
60
pA
IIO
Input offset current
Input bias current
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
800
1
60
pA
IIB
125°C
800
0
–0.3
25°C
to 4 to 4.2
Common-mode input voltage
range
VICR
RS = 50 Ω, | VIO | ≤ 5 mV
V
0
Full range
to 3.5
IOH = –20 µA
IOH = –100 µA
25°C
25°C
4.99
4.94
4.85
4.82
4.7
VOH
High-level output voltage
Low-level output voltage
Full range
25°C
V
4.85
IOH = –400 µA
Full range
25°C
4.5
IOL = 50 µA
0.01
0.09
25°C
0.15
IOL = 500 µA
VOL
VIC = 2.5 V
Full range
25°C
0.15
0.3
V
0.2
IOL = 1 mA
Full range
25°C
0.3
80
50
170
RL = 50 kΩ(2)
Large-signal differential
voltage amplification
AVD
VIC = 2.5 V, VO = 1 V to 4 V
Full range
25°C
V/mV
RL = 1 MΩ(2)
550
ri(d)
ri(c)
ci(c)
zo
Differential input resistance
25°C
1012
Ω
Ω
Common-mode input
resistance
25°C
25°C
25°C
1012
Common-mode input
capacitance
f = 10 kHz
8
pF
Closed-loop output
impedance
f = 100 kHz, AV = 10
240
83
Ω
25°C
Full range
25°C
70
70
80
80
Common-mode rejection
ratio
CMRR
kSVR
IDD
VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω
VDD = 4.4 V to 8 V, VIC = VDD/2, No load
VO = 2.5 V, No load
dB
dB
µA
95
Supply voltage rejection ratio
(ΔVDD/ΔVIO
)
Full range
25°C
400
500
500
Supply current
Full range
(1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(2) Referenced to 2.5 V
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TLV2262A-Q1, TLV2264A-Q1
SGLS193–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
TLV2262A OPERATING CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
25°C
MIN
0.35
0.25
TYP
MAX
UNIT
VO = 0.5 V to 3.5 V, RL = 50 kΩ(1)
,
0.55
SR
Vn
Slew rate at unity gain
V/µs
CL = 100 pF(1)
Full range
25°C
f = 10 Hz
40
12
Equivalent input noise
voltage
nV/√Hz
f = 1 kHz
25°C
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
0.7
Peak-to-peak equivalent
input noise voltage
VN(PP)
In
µV
fA/√Hz
%
25°C
1.3
Equivalent input noise current
25°C
0.6
AV = 1
AV = 10
f = 50 kHz, RL = 50 kΩ(1), CL = 100 pF(1)
25°C
0.017
0.03
0.71
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
THD+N
noise
RL = 50 kΩ(1)
25°C
Gain-bandwidth product
25°C
MHz
kHz
Maximum output-swing
bandwidth
VO(PP) = 2 V, AV = 1, RL = 50 kΩ(1)
,
BOM
ts
25°C
185
CL = 100 pF(1)
To 0.1%
25°C
25°C
25°C
25°C
6.4
14.1
56
AV = –1, Step = 0.5 V to 2.5 V,
Settling time
µs
RL = 50 kΩ(1), CL = 100 pF(1)
To 0.01%
φm
Phase margin at unity gain
Gain margin
RL = 50 kΩ(1), CL = 100 pF(1)
RL = 50 kΩ(1), CL = 100 pF(1)
°
Gm
11
dB
(1) Referenced to 2.5 V
8
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
www.ti.com ........................................................................................................................................................................................... SGLS193–DECEMBER 2008
TLV2264A ELECTRICAL CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
300
950
mV
VIO
Input offset voltage
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
Full range
1500
Temperature coefficient
of input offset voltage
αVIO
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
25°C to 125°C
25°C
2
µV/°C
Input offset voltage long-term
drift(1)
0.003
0.5
µV/mo
25°C
125°C
25°C
60
pA
IIO
Input offset current
Input bias current
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±1.5 V, VIC = 0, VO = 0, RS = 50 Ω
800
1
60
pA
IIB
125°C
800
0
–0.3
25°C
to 2 to 2.2
Common-mode input voltage
range
VICR
RS = 50 Ω, | VIO | ≤ 5 mV
V
0
Full range
to 1.7
IOH = –20 µA
IOH = –100 µA
25°C
25°C
2.99
2.85
2.82
2.7
VOH
High-level output voltage
Low-level output voltage
Full range
25°C
V
IOH = –400 µA
Full range
25°C
2.6
IOL = 50 µA
10
25°C
100
150
IOL = 500 µA
VOL
VIC = 1.5 V
Full range
25°C
150
300
300
mV
200
100
IOL = 1 mA
Full range
25°C
60
25
RL = 50 kΩ(2)
Large-signal differential
voltage amplification
AVD
VIC = 1.5 V, VO = 1 V to 2 V
Full range
25°C
V/mV
RL = 1 MΩ(2)
100
ri(d)
ri(c)
ci(c)
zo
Differential input resistance
25°C
1012
Ω
Ω
Common-mode input
resistance
25°C
25°C
25°C
1012
Common-mode input
capacitance
f = 10 kHz
8
pF
Closed-loop output
impedance
f = 100 kHz, AV = 10
270
77
Ω
25°C
Full range
25°C
65
60
80
80
Common-mode rejection
ratio
CMRR
kSVR
IDD
VIC = 0 to 1.7 V, VO = 1.5 V, RS = 50 Ω
VDD = 2.7 V to 8 V, VIC = VDD/2, No load
VO = 1.5 V, No load
dB
dB
100
0.8
Supply voltage rejection ratio
(ΔVDD/ΔVIO
)
Full range
25°C
1
1
Supply current
mA
Full range
(1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(2) Referenced to 1.5 V
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): TLV2262A-Q1 TLV2264A-Q1
TLV2262A-Q1, TLV2264A-Q1
SGLS193–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
TLV2264A OPERATING CHARACTERISTICS
VDD = 3 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
25°C
MIN
0.35
0.25
TYP
MAX
UNIT
VO = 0.5 V to 1.7 V, RL = 50 kΩ(1)
,
0.55
SR
Vn
Slew rate at unity gain
V/µs
CL = 100 pF(1)
Full range
25°C
f = 10 Hz
43
12
Equivalent input noise
voltage
nV/√Hz
f = 1 kHz
25°C
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
0.6
Peak-to-peak equivalent
input noise voltage
VN(PP)
In
µV
fA/√Hz
%
25°C
1
Equivalent input noise current
25°C
0.6
AV = 1
AV = 10
f = 1 kHz, RL = 50 kΩ(1), CL = 100 pF(1)
25°C
0.03
0.05
0.67
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
THD+N
noise
RL = 50 kΩ(1)
25°C
Gain-bandwidth product
25°C
MHz
kHz
Maximum output-swing
bandwidth
VO(PP) = 1 V, AV = 1, RL = 50 kΩ(1)
,
BOM
ts
25°C
395
CL = 100 pF(1)
To 0.1%
25°C
25°C
25°C
25°C
5.6
12.5
55
AV = –1, Step = 1 V to 2 V,
Settling time
µs
RL = 50 kΩ(1), CL = 100 pF(1)
To 0.01%
φm
Phase margin at unity gain
Gain margin
RL = 50 kΩ(1), CL = 100 pF(1)
RL = 50 kΩ(1), CL = 100 pF(1)
°
Gm
11
dB
(1) Referenced to 1.5 V
10
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TLV2264A ELECTRICAL CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
300
950
mV
VIO
Input offset voltage
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
Full range
1500
Temperature coefficient
of input offset voltage
αVIO
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
25°C to 125°C
25°C
2
µV/°C
Input offset voltage long-term
drift(1)
0.003
0.5
µV/mo
25°C
125°C
25°C
60
pA
IIO
Input offset current
Input bias current
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
VDD± = ±2.5 V, VIC = 0, VO = 0, RS = 50 Ω
800
1
60
pA
IIB
125°C
800
0
–0.3
25°C
to 4 to 4.2
Common-mode input voltage
range
VICR
RS = 50 Ω, | VIO | ≤ 5 mV
V
0
Full range
to 3.5
IOH = –20 µA
IOH = –100 µA
25°C
25°C
4.99
4.94
4.85
4.82
4.7
VOH
High-level output voltage
Low-level output voltage
Full range
25°C
V
4.85
IOH = –400 µA
Full range
25°C
4.5
IOL = 50 µA
0.01
0.09
25°C
0.15
IOL = 500 µA
VOL
VIC = 2.5 V
Full range
25°C
0.15
0.3
V
0.2
IOL = 1 mA
Full range
25°C
0.3
80
50
170
RL = 50 kΩ(2)
Large-signal differential
voltage amplification
AVD
VIC = 2.5 V, VO = 1 V to 4 V
Full range
25°C
V/mV
RL = 1 MΩ(2)
550
ri(d)
ri(c)
ci(c)
zo
Differential input resistance
25°C
1012
Ω
Ω
Common-mode input
resistance
25°C
25°C
25°C
1012
Common-mode input
capacitance
f = 10 kHz
8
pF
Closed-loop output
impedance
f = 100 kHz, AV = 10
240
83
Ω
25°C
Full range
25°C
70
70
80
80
Common-mode rejection
ratio
CMRR
kSVR
IDD
VIC = 0 to 2.7 V, VO = 2.5 V, RS = 50 Ω
VDD = 4.4 V to 8 V, VIC = VDD/2, No load
VO = 2.5 V, No load
dB
dB
95
Supply voltage rejection ratio
(ΔVDD/ΔVIO
)
Full range
25°C
0.8
1
1
Supply current
mA
Full range
(1) Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
(2) Referenced to 2.5 V
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TLV2264A OPERATING CHARACTERISTICS
VDD = 5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
25°C
MIN
0.35
0.25
TYP
MAX
UNIT
VO = 0.5 V to 3.5 V, RL = 50 kΩ(1)
,
0.55
SR
Vn
Slew rate at unity gain
V/µs
CL = 100 pF(1)
Full range
25°C
f = 10 Hz
40
12
Equivalent input noise
voltage
nV/√Hz
f = 1 kHz
25°C
f = 0.1 Hz to 1 Hz
f = 0.1 Hz to 10 Hz
25°C
0.7
Peak-to-peak equivalent
input noise voltage
VN(PP)
In
µV
fA/√Hz
%
25°C
1.3
Equivalent input noise current
25°C
0.6
AV = 1
AV = 10
f = 50 kHz, RL = 50 kΩ(1), CL = 100 pF(1)
25°C
0.017
0.03
0.71
Total harmonic distortion plus VO = 0.5 V to 2.5 V, f = 20 kHz,
THD+N
noise
RL = 50 kΩ(1)
25°C
Gain-bandwidth product
25°C
MHz
kHz
Maximum output-swing
bandwidth
VO(PP) = 2 V, AV = 1, RL = 50 kΩ(1)
,
BOM
ts
25°C
185
CL = 100 pF(1)
To 0.1%
25°C
25°C
25°C
25°C
6.4
14.1
56
AV = –1, Step = 0.5 V to 2.5 V,
Settling time
µs
RL = 50 kΩ(1), CL = 100 pF(1)
To 0.01%
φm
Phase margin at unity gain
Gain margin
RL = 50 kΩ(1), CL = 100 pF(1)
RL = 50 kΩ(1), CL = 100 pF(1)
°
Gm
11
dB
(1) Referenced to 2.5 V
12
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TYPICAL CHARACTERISTICS
For all curves where VDD = 5 V, all loads are referenced to 2.5 V. For all curves where VDD = 3 V, all loads are
referenced to 1.5 V. Data at high and low temperatures are applicable only within the rated operating free-air
temperature ranges of the various devices.
Table of Graphs
FIGURE
Distribution
2–5
6, 7
VIO
Input offset voltage
vs Common–mode voltage
Distribution
αVIO
Input offset voltage temperature coefficient
Input bias and input offset currents
8–11
12
IIB/IIO
vs Free–air temperature
vs Supply voltage
13
VI
Input voltage
vs Free–air temperature
vs High-level output current
vs Low-level output current
vs Frequency
14
VOH
High-level output voltage
15, 18
16, 17, 19
20
VOL
Low-level output voltage
VO(PP)
Maximum peak-to-peak output voltage
vs Supply voltage
21
IOS
Short-circuit output current
vs Free-air temperature
vs Output voltage
22
VID
Differential input voltage
23, 24
25
AVD
Differential voltage amplification
vs Load resistance
vs Frequency
26, 27
28, 29
30, 31
32
AVD
zo
Large-signal differential voltage amplification
Output impedance
vs Free-air temperature
vs Frequency
vs Frequency
CMRR
Common-mode rejection ratio
vs Free-air temperature
vs Frequency
33
34, 35
36, 37
38, 39
40
kSVR
IDD
Supply-voltage rejection ratio
Supply current
vs Free-air temperature
vs Free-air temperature
vs Load capacitance
vs Free-air temperature
SR
Slew rate
41
VO
VO
VO
VO
Vn
Inverting large-signal pulse response
Voltage-follower large-signal pulse response
Inverting small-signal pulse response
Voltage-follower small-signal pulse response
Equivalent input noise voltage
42, 43
44, 45
46, 47
48, 49
50, 51
52
vs Frequency
Input noise voltage
Over a 10-second period
vs Frequency
Integrated noise voltage
53
THD+N
Total harmonic distortion plus noise
vs Frequency
54
vs Supply voltage
vs Free-air temperature
vs Frequency
55
Gain-bandwidth product
Phase margin
56
26, 27
57
φm
vs Load capacitance
vs Load capacitance
vs Load capacitance
vs Load capacitance
Gm
B1
Gain margin
58
Unity-gain bandwidth
Overestimation of phase margin
59
60
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DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2262
INPUT OFFSET VOLTAGE
15
12
9
15
12
9
841 Amplifiers From 2 Wafer Lots
841 Amplifiers From 2 Wafer Lots
V
DD
= ± 1.5 V
V = ± 2.5 V
±
DD
±
T
A
= 25°C
T = 25°C
A
6
3
0
6
3
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 2.
Figure 3.
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLV2264
INPUT OFFSET VOLTAGE
20
16
12
20
16
12
2272 Amplifiers From 2 Wafer Lots
= ±1.5 V
2272 Amplifiers From 2 Wafer Lots
= ±2.5 V
T = 25°C
A
V
DD
V
DD
±
±
T
= 25°C
A
8
4
0
8
4
0
−1.6
−0.8
0
0.8
1.6
−1.6
−0.8
0
0.8
1.6
V
IO
− Input Offset Voltage − mV
V
IO
− Input Offset Voltage − mV
Figure 4.
Figure 5.
14
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INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
1
1
0.5
0
V
R
T
= 3 V
= 50 Ω
= 25°C
V
R
T
= 5 V
= 50 Ω
= 25°C
DD
DD
S
S
A
A
0.5
0
−0.5
−0.5
−1
−1
−1 −0.5
−1
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
V
IC
− Common-Mode Input Voltage − V
V
IC
− Common-Mode Input Voltage − V
Figure 6.
Figure 7.
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2262 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
30
25
20
15
10
5
30
25
20
15
10
5
128 Amplifiers From 2 Wafer Lots
128 Amplifiers From 2 Wafer Lots
V
DD
= ±1.5 V
V = ±2.5 V
±
DD
±
P Package
= 25°C to 85°C
P Package
= 25°C to 85°C
T
T
A
A
0
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
α
− Temperature Coefficient − µV/°C
α
− Temperature Coefficient − µV/°C
VIO
VIO
Figure 8.
Figure 9.
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DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLV2264 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
35
30
35
30
128 Amplifiers From
2 Wafer Lots
128 Amplifiers From
2 Wafer Lots
V
DD
= ±1.5 V
±
V
DD
= ±2.5 V
±
N Package
= 25°C to 125°C
N Package
= 25°C to 125°C
T
A
T
A
25
20
15
10
25
20
15
10
5
0
5
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
−5 −4 −3 −2 −1
0
1
2
3
4
5
α
− Temperature Coefficient
α
VIO
− Temperature Coefficient
VIO
of Input Offset Voltage − µV/°C
of Input Offset Voltage − µV/°C
Figure 10.
Figure 11.
INPUT BIAS AND INPUT OFFSET CURRENTS
INPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
35
30
2.5
2
R
T
A
= 50 Ω
= 25°C
S
V
V
V
= ±2.5 V
= 0
= 0
= 50 Ω
±
DD
IC
O
1.5
1
R
S
25
I
IB
0.5
0
20
15
| V | ≤5 mV
IO
−0.5
−1
−1.5
−2
I
IO
10
5
0
−2.5
25
45
T
65
85
105
125
1
1.5
2
2.5
3
3.5
4
− Free-Air Temperature − °C
|V
DD
| − Supply Voltage − V
A
±
Figure 12.
Figure 13.
16
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INPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
4
3.5
3
5
4
3
2
1
V
DD
= 5 V
V
DD
= 3 V
T
A
= −55°C
2.5
2
T
A
= 125°C
| V | ≤5 mV
IO
T
A
= 25°C
= 85°C
1.5
1
T
A
T
A
= −40°C
0
0.5
0
−1
0
500
1000
1500
2000
−55 −35 −15
5
25
45
65 85 105 125
T
A
− Free-Air Temperature − °C
| I | − High-Level Output Current − µA
OH
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
1.4
1.2
1.2
1
V
T
= 3 V
= 25°C
DD
V
= 3 V
DD
= 1.5 V
V
IC
A
T
A
= 125°C
V
IC
= 0
1
0.8
0.6
0.4
0.2
0
T
= 85°C
A
0.8
0.6
V
IC
= 0.75 V
T
A
= 25°C
V
IC
= 1.5 V
T
= − 55°C
A
0.4
T
A
= − 40°C
0.2
0
0
1
2
3
4
5
0
1
2
3
4
5
I
− Low-Level Output Current − mA
OL
I
− Low-Level Output Current − mA
OL
Figure 16.
Figure 17.
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HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
6
5
4
3
2
1.4
1.2
V
V
= 5 V
= 2.5 V
DD
V
= 5 V
DD
IC
T
A
= −55°C
1
T
A
= 85°C
T
= −40°C
= 25°C
0.8
A
T
= 25°C
A
T
0.6
0.4
A
T
= 125°C
A
T
A
= 125°C
T
A
= −55°C
T
A
= 85°C
T
A
= −40°C
1
0
0.2
0
0
500
1000
1500
2000
2500
3000
0
1
2
3
4
5
6
| I | − High-Level Output Current − µA
OH
I
− Low-Level Output Current − mA
OL
Figure 18.
Figure 19.
SHORT-CIRCUIT OUTPUT CURRENT
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
FREQUENCY
5
12
10
V
T
A
= V /2
DD
= 25°C
IC
R = 10 kΩ
V
DD
= 5 V
I
V
ID
= −100 mV
T
= 25°C
A
4
3
8
6
V
DD
= 3 V
4
2
2
1
0
0
V
ID
= 100 mV
4
−2
3
4
5
6
2
3
5
6
7
8
10
10
10
10
V
DD
− Supply Voltage − V
f − Frequency − Hz
Figure 20.
Figure 21.
18
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SHORT-CIRCUIT OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
vs
vs
OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
12
10
1000
800
V
V
= 2.5 V
= 5 V
O
V
= 3 V
DD
DD
R = 50 kΩ
I
V
IC
= 1.5 V
= 25°C
600
V
ID
= −100 mV
T
A
8
6
4
2
0
400
200
0
−200
−400
−600
−800
V
ID
= 100 mV
−2
−4
−1000
0
0.5
1
1.5
2
2.5
3
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
V
O
− Output Voltage − V
Figure 22.
Figure 23.
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
vs
OUTPUT VOLTAGE
LOAD RESISTANCE
1000
100
10
1000
800
V
T
= 2 V
= 5 V
O(PP)
V
V
R
= 5 V
DD
= 25°C
A
= 2.5 V
= 50 kΩ
= 25°C
IC
L
600
T
A
V
DD
400
200
V
DD
= 3 V
0
−200
−400
−600
−800
1
10
−1000
3
4
5
6
10
10
10
0
1
2
3
4
5
R − Load Resistance − kΩ
L
V
O
− Output Voltage − V
Figure 24.
Figure 25.
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LARGE-SIGNAL DIFFERENTIAL VOLTAGE
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
AMPLIFICATION AND PHASE MARGIN
vs
vs
FREQUENCY
FREQUENCY
80
60
80
60
180°
135°
180°
135°
V
= 3 V
= 100 pF
= 25°C
V
= 5 V
DD
DD
C
T
C = 100 pF
T
A
L
L
= 25°C
A
40
20
0
40
90°
45°
90°
45°
Phase Margin
Phase Margin
20
0
Gain
Gain
0°
0°
−20
−45°
−90°
−20
−45°
−90°
−40
−40
10
3
4
5
6
7
10
10
10
10
10
3
4
5
6
7
10
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 26.
Figure 27.
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1000
100
10
10000
1000
V
= 5 V
= 2.5 V
= 1 V to 4 V
DD
V
IC
V
O
R = 1 MΩ
L
R = 1 MΩ
L
R = 50 kΩ
L
R = 50 kΩ
L
R = 10 kΩ
L
100
10
R = 10 kΩ
L
V
= 3 V
= 1.5 V
= 0.5 V to 2.5 V
DD
V
IC
V
O
−75 −50 −25
0
25
50
75 100
125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 28.
Figure 29.
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OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
1000
100
10
1000
100
10
V
T
= 3 V
= 25°C
V
T
= 5 V
= 25°C
DD
DD
A
A
A
= 100
V
A
= 100
= 10
V
A
= 10
= 1
V
A
V
A
V
A
= 1
V
1
1
0.1
0.1
2
3
4
5
2
3
4
5
10
10
10
10
10
10
10
10
f− Frequency − Hz
f− Frequency − Hz
Figure 30.
Figure 31.
COMMON-MODE REJECTION RATIO
COMMON-MODE REJECTION RATIO
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
100
80
90
88
86
84
82
80
78
76
74
72
70
V
V
= 5 V
= 2.5 V
T
A
= 25°C
DD
IC
V
V
= 5 V
= 1.5 V
DD
V
V
= 5 V
DD
IC
60
40
20
0
= 3 V
DD
4
5
6
1
2
3
10
10
10
10
10
10
− 75 − 50 − 25
0
25 50
75 100
125
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 32.
Figure 33.
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SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
100
80
100
80
V
T
A
= 3 V
= 25°C
V
= 5 V
DD
DD
T = 25°C
A
60
60
k
k
SVR+
SVR+
40
40
k
k
SVR−
SVR−
20
0
20
0
−20
−20
6
6
1
2
3
4
5
1
2
3
4
5
10
10
10
10
10
10
10
10
10
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 34.
Figure 35.
TLV2262
TLV2264
SUPPLY-VOLTAGE REJECTION RATIO
SUPPLY-VOLTAGE REJECTION RATIO
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
110
105
110
105
V
V
= 2.7 V to 8 V
V
= 2.7 V to 8 V
DD
= V = V /2
O DD
DD
= V = V /2
V
IC
IC
O
DD
100
95
100
95
90
90
−75 −50 −25
0
25
50
75 100
125
−75
−50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 36.
Figure 37.
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TLV2262
SUPPLY CURRENT
vs
TLV2264
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
600
500
1200
1000
V
V
= 5 V
= 2.5 V
DD
V
= 5 V
DD
= 2.5 V
O
V
O
400
300
800
600
V
V
= 3 V
= 1.5 V
DD
V
= 3 V
DD
= 1.5 V
O
V
O
200
400
−75 −50 −25
0
25
50
75
100 125
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
Figure 38.
T
A
− Free-Air Temperature − °C
Figure 39.
SLEW RATE
vs
SLEW RATE
vs
LOAD CAPACITANCE
FREE-AIR TEMPERATURE
1
0.8
0.6
1.2
1
SR−
SR−
0.8
0.6
0.4
0.2
0
SR+
SR+
0.4
V
= 5 V
DD
0.2
0
R = 50 kΩ
C
A
V
= 5 V
= −1
= 25°C
L
DD
= 100 pF
= 1
A
T
L
V
V
A
1
2
3
4
−75 −50 −25
0
25
50
75 100
125
10
10
10
10
T
A
− Free-Air Temperature − °C
C − Load Capacitance − pF
L
Figure 40.
Figure 41.
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INVERTING LARGE-SIGNAL PULSE
RESPONSE
INVERTING LARGE-SIGNAL PULSE
RESPONSE
3
2.5
2
5
4
V
= 5 V
V
= 3 V
DD
DD
R = 50 kΩ
R = 50 kΩ
L
L
C
A
T
= 100 pF
= −1
= 25°C
C
A
T
= 100 pF
= −1
= 25°C
L
V
L
V
A
A
3
2
1.5
1
1
0
0.5
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 42.
Figure 43.
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
5
4
3
2.5
2
V
= 5 V
DD
V
= 3 V
= 50 kΩ
= 100 pF
= −1
DD
R = 50 kΩ
C
A
L
R
C
A
L
L
V
= 100 pF
= −1
= 25°C
L
V
T
A
T
A
= 25°C
3
2
1.5
1
1
0
0.5
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 44.
Figure 45.
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INVERTING SMALL-SIGNAL
PULSE RESPONSE
INVERTING SMALL-SIGNAL
PULSE RESPONSE
0.95
0.9
2.65
2.6
V
= 3 V
DD
V
= 5 V
DD
R = 50 kΩ
C
A
L
R = 50 kΩ
C = 100 pF
L
= 100 pF
= − 1
= 25°C
L
V
L
A = −1
V
T
A
T
A
= 25°C
0.85
0.8
2.55
2.5
0.75
0.7
2.45
2.4
0.65
0.6
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 46.
Figure 47.
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
0.95
0.9
2.65
2.6
V
= 3 V
V
= 5 V
DD
DD
R = 50 kΩ
C = 100 pF
A
V
R = 50 kΩ
L
C = 100 pF
L
A
V
L
L
= 1
= 1
T
A
= 25°C
T
A
= 25°C
0.85
0.8
2.55
2.5
0.75
0.7
2.45
2.4
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t − Time − µs
t − Time − µs
Figure 48.
Figure 49.
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EQUIVALENT INPUT NOISE VOLTAGE
EQUIVALENT INPUT NOISE VOLTAGE
vs
vs
FREQUENCY
FREQUENCY
60
50
60
50
V
R
T
A
= 3 V
= 20 Ω
= 25°C
V
R
S
T
A
= 5 V
= 20 Ω
= 25°C
DD
DD
S
40
30
40
30
20
10
0
20
10
0
1
2
3
4
1
2
3
4
10
10
10
10
10
10
10
10
f − Frequency − Hz
f − Frequency − Hz
Figure 50.
Figure 51.
INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD
INTEGRATED NOISE VOLTAGE
vs
1000
750
FREQUENCY
100
CalculatedUsing Ideal Pass-Band Filter
Lower Frequency = 1 Hz
T
A
= 25°C
500
250
10
0
−250
−500
−750
−1000
1
V
= 5 V
DD
f = 0.1 Hz
to 10 Hz
T
A
= 25°C
0
2
4
6
8
10
0.1
1
2
3
4
5
t − Time − s
1
10
10
10
10
10
f − Frequency − Hz
Figure 52.
Figure 53.
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GAIN-BANDWIDTH PRODUCT
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
SUPPLY VOLTAGE
FREQUENCY
−1
10
900
860
820
A
= 100
V
−2
10
A
A
= 10
= 1
V
V
780
740
700
V
R
T
A
= 5 V
= 50 kΩ
= 25°C
DD
L
−3
10
1
2
3
4
4
10
10
10
10
10
0
1
2
3
4
5
6
7
8
V
DD
− Supply Voltage − V
f − Frequency − Hz
Figure 54.
Figure 55.
GAIN-BANDWIDTH PRODUCT
vs
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
1200
1000
800
75°
V
= 5 V
DD
T
A
= 25°C
f = 10 kHz
C = 100 pF
L
60°
45°
30°
R
= 100 Ω
null
R
= 50 Ω
null
R
= 20 Ω
= 10 Ω
null
R
null
50 kΩ
600
400
V
15°
0°
DD +
50 kΩ
R
null
V
−
+
I
C
L
R
null
= 0
V
/GND
DD −
2
3
4
−75 −50 −25
0
25
50
75
100
125
10
10
10
10
T
A
− Free-Air Temperature − °C
C − Load Capacitance − pF
L
Figure 56.
Figure 57.
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GAIN MARGIN
vs
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
1000
20
15
10
R
A
T
A
= 50 kΩ
= 1
= 25°C
L
V
T
A
= 25°C
R
= 100 Ω
null
800
600
400
200
R
null
= 50 Ω
R
= 20 Ω
null
5
0
R
null
= 10 Ω
R
3
= 0
null
2
3
4
10
10
10
10
2
4
10
10
10
10
C − Load Capacitance − pF
L
C − Load Capacitance − pF
L
Figure 58.
Figure 59.
OVERESTIMATION OF PHASE MARGIN
vs
LOAD CAPACITANCE
14°
12°
10°
T
A
= 25°C
R
null
= 100 Ω
8°
6°
4°
2°
0
R
= 50 Ω
null
R
null
= 10 Ω
R
null
= 20 Ω
2
3
4
10
10
10
10
C − Load Capacitance − pF
L
NOTE: See application information.
Figure 60.
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APPLICATION INFORMATION
Driving Large Capacitive Loads
The TLV226x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 51 and
Figure 52 illustrate its ability to drive loads greater than 400 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 61) improves the gain and phase margins
when driving large capacitive loads. Figure 51 and Figure 52 show the effects of adding series resistances of 10
Ω, 20 Ω, 50 Ω, and 100 Ω. The addition of this series resistor has two effects: the first is that it adds a zero to the
transfer function and the second is that it reduces the frequency of the pole associated with the output load in the
transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, Equation 1 can be used.
–1
ǒ2 × π × UGBW × R
LǓ
∆θ
+ tan
× C
m1
null
Where :
∆θ
+ improvement in phase margin
m1
UGBW + unity-gain bandwidth frequency
R
+ output series resistance
+ load capacitance
null
C
L
(1)
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 53). To use
Equation 1, UGBW must be approximated from Figure 53.
Using Equation 1 alone overestimates the improvement in phase margin as illustrated in Figure 60. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, providing
additional phase shift and reducing the overall improvement in phase margin. The pole associated with the load
is reduced by the factor calculated in Equation 2.
1
F +
1 ) g × R
m
null
Where :
F + factor reducing frequency of pole
–3
g
+ small-signal output transconductance (typically 4.83 × 10
+ output series resistance
mhos)
m
R
null
(2)
For the TLV226x, the pole associated with the load is typically 7 MHz with 100-pF load capacitance. This value
varies inversely with CL: at CL = 10 pF, use 70 MHz, at CL = 1000 pF, use 700 kHz, and so on.
Reducing the pole associated with the load introduces phase shift, thereby reducing phase margin. This results
in an error in the increase in phase margin expected by considering the zero alone (see Equation 1). Equation 3
approximates the reduction in phase margin due to the movement of the pole associated with the load. The
result of this equation can be subtracted from the result of the Equation 1 to better approximate the improvement
in phase margin.
–1ȱUGBW
ȳ
UGBW
–1
ǒ Ǔ
∆θ
+ tan
– tan
2 ȴ
ȧ
ȧ
Ǔ
m2
P
ǒF×P
2
Ȳ
Where :
∆θ
+ reduction in phase margin
m2
UGBW + unity-gain bandwidth frequency
F + factor from equation (2)
P
+ unadjusted pole (70 MHz @ 10 pF, 7 MHz @100 pF, etc.)
2
(3)
Using these equations with Figure 60 and Figure 61 enables the designer to choose the appropriate output
series resistance to optimize the design of circuits driving large capacitive loads.
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50 kΩ
V
DD+
50 kΩ
R
null
V
I
−
+
C
L
V
DD−
/GND
Figure 61. Series-Resistance Circuit
Macromodel Information
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™. The Boyle macromodel(1) and subcircuit in Figure 62 are generated using the TLV226x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
•
•
•
•
•
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
(1) G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
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99
DLN
3
EGND
+
−
V
CC+
92
9
FB
+
91
90
RSS
ISS
RO2
+
−
+
−
VB
DLP
RP
2
VLP
VLN
HLIM
−
+
−
10
+
−
VC
IN −
IN+
R2
C2
J1
J2
7
DP
6
53
+
−
1
VLIM
11
DC
12
RD2
GA
GCM
8
C1
RD1
60
RO1
+
−
DE
VAD
5
54
V
CC−
−
+
4
VE
OUT
.SUBCKT TLV226x 1 2 3 4 5
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
60
60
8
11
12
5
15.92E3
15.92E3
135
C1
11
6
12
7
5.5E−12
20.00E−12
DX
C2
DC
5
53
5
7
99
4
135
DE
54
90
92
4
DX
3
15.87E3
18.18E6
−.5
DLP
DLN
DP
91
90
3
DX
10
60
9
99
4
DX
DX
0
DC 0
EGND
FB
99
7
0
99
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
3
53
4
DC .615
DC .615
DC 0
54
7
+ VLN 0 8.84E6 −10E6 10E6 10E6 −10E6
VLIM
VLP
VLN
8
0
GA
6
0
6
11
10
12 62.83E−6
99 12.34E−9
91
0
DC 1
DC 5.1
GCM
ISS
HLIM
J1
0
92
3
10
0
DC 11.05E−6
VLIM 1K
10 JX
.MODEL DX D (IS=800.0E−18)
90
11
12
6
.MODEL JX PJF (IS=500.0E−15 BETA=325E−6
2
1
+ VTO=−.08)
.ENDS
J2
10 JX
R2
9
100.0E3
Figure 62. Boyle Macromodel and Subcircuit
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV2262AQDRQ1
OBSOLETE
ACTIVE
SOIC
D
8
8
TBD
Call TI
Call TI
TLV2262AQPWRQ1
TSSOP
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2262QDRQ1
TLV2264AQDRQ1
TLV2264AQPWRQ1
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
D
D
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
14
14
TSSOP
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TLV2264QDRQ1
OBSOLETE
SOIC
D
14
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2262-Q1, TLV2262A-Q1, TLV2264-Q1, TLV2264A-Q1 :
Catalog: TLV2262, TLV2262A, TLV2264, TLV2264A
Military: TLV2262M, TLV2262AM, TLV2264M, TLV2264AM
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
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相关型号：
TLV2264AIDR
QUAD OP-AMP, 1500uV OFFSET-MAX, 0.67MHz BAND WIDTH, PDSO14, GREEN, PLASTIC, SOIC-14
ROCHESTER
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