TLV2354IPWRG4 [TI]
Quad Low Voltage LinCMOS(TM) Differential Comparator 14-TSSOP -40 to 85;
| 型号： | TLV2354IPWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad Low Voltage LinCMOS(TM) Differential Comparator 14-TSSOP -40 to 85 放大器 光电二极管 |
| 文件： | 总19页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
Wide Range of Supply Voltages
2 V to 8 V
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
Fully Characterized at 3 V and 5 V
Extremely Low Input Bias Current
5 pA Typ
Very-Low Supply-Current Drain
240 µA Typ at 3 V
Output Compatible With TTL, MOS, and
CMOS
Common-Mode Input Voltage Range
Includes Ground
Built-In ESD Protection
12
High Input Impedance . . . 10 Ω Typ
description
symbol (each comparator)
The TLV2354 consists of four independent,
low-power comparators specifically designed for
single power-supply applications and operateS
with power-supply rails as low as 2 V. When
powered from a 3-V supply, the typical supply
current is only 240 µA.
IN+
OUT
IN–
The TLV2354 is designed using the Texas Instruments LinCMOS technology and, therefore, features an
12
extremely high input impedance (typically greater than 10 Ω), which allows direct interfacing with
high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup
resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic
wired-ANDrelationships. TheTLV2354Iisfullycharacterizedforoperationfrom–40°Cto85°C. TheTLV2354M
is fully characterized for operation from – 55°C to 125°C.
The TLV2354 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a
1000-V ESD rating using human body model testing. However, care should be exercised in handling this device
as exposure to ESD may result in degradation of the device parametric performance.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
V
max
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
CERAMIC
FLATPACK
(W)
IO
SMALL
T
A
FORM
(Y)
TSSOP
(PW)
at 25°C
OUTLINE
‡
†
(J)
(N)
(D)
–40°C to
85°C
5 mV
5 mV
TLV2354ID
—
—
—
TLV2354IN
—
TLV2354IPW
—
—
TLV2354Y
–55°C to
125°C
TLV2354MFK
TLV2354MJ
TLV2354MW
†
‡
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLV2352IDR).
The PW packages are only available left-ended taped and reeled (e.g., TLV2354IPW).
These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LINCMOS is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
TLV2354I
D OR N PACKAGE
(TOP VIEW)
TLV2354I
PW PACKAGE
(TOP VIEW)
1OUT
2OUT
1OUT
2OUT
3OUT
4OUT
3OUT
4OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
+
V
/GND
V
/GND
DD+
DD
DD–
DD–
2IN–
2IN+
1IN–
1IN+
2IN–
2IN+
1IN–
1IN+
4IN+
4IN–
3IN+
3IN–
4IN+
4IN–
3IN+
3IN–
8
8
TLV2354M
J OR W PACKAGE
(TOP VIEW)
TLV2354AM, TLV2354M
FK PACKAGE
(TOP VIEW)
1OUT
2OUT
3OUT
4OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
V
+
V
/GND
DD
DD–
3
2
1
20 19
18
V
/GND
V
4
5
6
7
8
DD–
DD+
NC
2IN–
2IN+
1IN–
1IN+
4IN+
4IN–
3IN+
3IN–
NC
17
16
15
14
4IN+
NC
2IN–
NC
8
4IN–
2IN+
9 10 11 12 13
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2254, TLV2254Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
•
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
TLV2354Y chip information
This chip, when properly assembled, displays characteristics similar to the TLV2354. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
V
DD
(3)
(7)
(6)
(13)
(12)
IN+
IN–
+
–
(10)
(9)
(11)
(1)
OUT
(5)
(4)
+
IN+
IN–
(2)
OUT
(14)
(1)
–
(9)
(8)
(8)
(7)
IN+
IN–
+
–
(14)
65
OUT
(11)
(10)
+
IN+
IN–
(13)
OUT
–
(12)
GND
(6)
(5)
(4)
(3)
(2)
CHIP THICKNESS: 15 MILS TYPICAL
90
BONDING PADS: 4 × 4 MILS MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8 V
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 8 V
ID
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Duration of output short-circuit current to GND (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TLV2354I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
TLV2354M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FK, J, or W package . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input terminal with respect to the inverting input terminal.
3. Short circuits from outputs to V
can cause excessive heating and eventual device destruction.
DD
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
T
= 85°C
T = 125°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
POWER RATING
D
FK
J
N
PW
W
950 mW
1375 mW
1375 mW
1150 mW
700 mW
700 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
5.6 mW/°C
5.5 mW/°C
494 mW
715 mW
715 mW
598 mW
364 mW
370 mW
—
275 mW
275 mW
—
—
150 mW
recommended operating conditions
MIN
MAX
8
UNIT
Supply voltage, V
DD
2
0
V
V
V
= 3 V
= 5 V
1.75
3.75
85
DD
Common-mode input voltage, V
V
IC
0
DD
TLV2354I
–40
–55
Operating free-air temperature, T
°C
A
TLV2354M
125
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
†
electrical characteristics at specified free-air temperature
TLV2354I
‡
PARAMETER
TEST CONDITIONS
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
UNIT
T
A
MIN
MAX MIN
MAX
25°C
Full range
25°C
1
1
5
5
7
1
1
5
5
7
V
Input offset voltage
Input offset current
Input bias current
V
IC
= V
min,
ICR
See Note 4
mV
IO
pA
nA
pA
nA
I
IO
85°C
1
1
2
25°C
I
IB
85°C
2
25°C
0 to 2
0 to 4
Common-mode input
voltage range
V
ICR
V
0 to
1.75
0 to
3.75
Full range
25°C
Full range
25°C
0.1
0.1
nA
High-level output
current
I
V
ID
= 1 V
OH
1
300
600
1
400
700
µA
115
150
Low-level output
voltage
V
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 2 mA
mA
mA
µA
OL
OL
Full range
Low-level output
current
I
I
V
= 1.5 V
25°C
6
16
6
16
OL
OL
25°C
240
500
700
290
600
800
Supply current
No load
DD
Full range
†
‡
All characteristics are measured with zero common-mode input voltage unless otherwise noted.
Full range is –40°C to 85°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with V
= 5 V, 2 V with V
DD
= 3 V, or
DD
below 400 mV with a 10-kΩ resistor between the output and V . They can be verified by applying the limit value to the input and
DD
checking for the appropriate output state.
switching characteristics, V
= 3 V, T = 25°C
A
DD
TLV2354I
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
§
= 15 pF ,
R
= 5.1 kΩ,
C
L
L
Response time
100-mV input step with 5-mV overdrive
640
ns
See Note 5
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or when the output crosses V = 1.4 with V
= 5 V.
DD
O
switching characteristics, V
= 5 V, T = 25°C
A
DD
TLV2354I
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
§
= 15 pF ,
100-mV input step with 5-mV overdrive
TTL-level input step
650
R
= 5.1 kΩ,
C
L
Response time
ns
See Note 5
200
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or when the output crosses V = 1.4 with V
= 5 V.
O
DD
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
†
electrical characteristics at specified free-air temperature
TLV2354M
‡
PARAMETER
TEST CONDITIONS
V
= 3 V
V
= 5 V
UNIT
T
A
DD
TYP
DD
TYP
MIN
MAX MIN
MAX
5
25°C
Full range
25°C
1
1
5
5
1
1
5
V
IO
Input offset voltage
Input offset current
Input bias current
V
IC
= V
min,
ICR
See Note 4
mV
10
10
pA
nA
pA
nA
I
IO
125°C
25°C
10
10
20
I
IB
125°C
25°C
20
0 to 2
0 to 4
Common-mode input
voltage range
V
ICR
V
0 to
1.75
0 to
3.75
Full range
25°C
Full range
25°C
0.1
0.1
nA
High-level output
current
I
V
ID
= 1 V
OH
1
300
600
1
400
700
µA
115
150
Low-level output
voltage
V
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 2 mA
mA
mA
µA
OL
OL
Full range
Low-level output
current
I
I
V
= 1.5 V
25°C
6
16
6
16
OL
OL
25°C
240
500
700
290
600
800
Supply current
No load
DD
Full range
†
‡
All characteristics are measured with zero common-mode input voltage unless otherwise noted.
Full range is –55°C to 125°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with V
= 5 V, 2 V with V
DD
= 3 V, or
DD
below 400 mV with a 10-kΩ resistor between the output and V . They can be verified by applying the limit value to the input and
DD
checking for the appropriate output state.
switching characteristics, V
= 3 V, T = 25°C
A
DD
TLV2354M
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
§
= 100 pF ,
R
= 5.1 kΩ,
C
L
L
Response time
100-mV input step with 5-mV overdrive
1400
ns
See Note 5
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or when the output crosses V = 1.4 with V
= 5 V.
DD
O
switching characteristics, V
= 5 V, T = 25°C
A
DD
TLV2354M
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
1300
900
§
= 100 pF ,
100-mV input step with 5-mV overdrive
TTL-level input step
R
= 5.1 kΩ,
C
L
Response time
ns
See Note 5
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or when the output crosses V = 1.4 with V
= 5 V.
O
DD
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
†
electrical characteristics at specified free-air temperature, T = 25°C
A
TLV2354Y
PARAMETER
TEST CONDITIONS
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
UNIT
MIN
MAX MIN
MAX
V
Input offset voltage
V
= V min, See Note 4
ICR
1
1
5
5
1
1
5
5
mV
pA
pA
V
IO
IC
I
I
Input offset current
IO
Input bias current
IB
V
ICR
Common-mode input voltage range
High-level output current
Low-level output voltage
Low-level output current
Supply current
0 to 2
0 to 4
I
V
ID
V
ID
V
ID
V
ID
= 1 V
0.1
115
16
0.1
150
16
nA
mV
mA
µA
OH
V
OL
= –1 V,
= –1 V,
= 1 V,
I
= 2 mA
300
6
400
600
OL
I
I
V
= 1.5 V
6
OL
OL
No load
240
500
290
DD
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with V
= 5 V, 2 V with V
DD
= 3 V, or
DD
below 400 mV with a 10-kΩ resistor between the output and V . They can be verified by applying the limit value to the input and
DD
checking for the appropriate output state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1100
990
880
770
660
550
440
330
380
360
340
320
300
280
260
V
T
= 3 V
= 25°C
No Load
DD
A
V
= 5 V
DD
V
DD
= 3 V
240
220
200
180
220
110
0
0
2
4
6
8
10
12
14
16
– 75 – 50 –25
0
25
50
75
100 125
I
– Low-Level Output Current – mA
T
A
– Free-Air Temperature – °C
OL
Figure 1
Figure 2
COMMON-MODE INPUT VOLTAGE RANGE
OUTPUT FALL TIME
vs
vs
FREE-AIR TEMPERATURE
CAPACITIVE LOAD
3
2.5
2
50
45
40
35
30
25
20
15
V
DD
= 3 V
V
= 3 V
DD
Overdrive = 10 mV
Positive Limit
R
T
A
= 5.1 kΩ (pullup to V
= 25°C
)
DD
L
1.5
1
0.5
0
Negative Limit
10
5
– 0.5
0
– 1
0
10 20 30 40 50 60 70 80 90 100
– 75 – 50 – 25
0
25
50
75 100 125
C
– Capacitive Load – pF
T
A
– Free-Air Temperature – °C
L
Figure 3
Figure 4
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
FOR VARIOUS CAPACITIVE LOADS
V
C
R
= 3 V
= 15 pF
= 5.1 kΩ (pullup to V
= 25°C
V
= 3 V
DD
L
L
DD
Overdrive = 10 mV
)
R = 5.1 kΩ (pullup to V
T = 25°C
A
)
DD
L
DD
T
A
3
0
3
0
C
= 100 pF
L
20 mV
5 mV
C = 15 pF
L
10 mV
C
= 50 pF
L
100
0
100
0
0
100 200 300 400 500 600 700 800 900 1000
– High-to-Low-Level Output
0
100 200 300 400 500 600 700 800 900 1000
– High-to-Low-Level Output
t
t
PHL
PHL
Propagation Delay Time – ns
Propagation Delay Time – ns
Figure 5
Figure 6
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS CAPACITIVE LOADS
FOR VARIOUS OVERDRIVE VOLTAGES
V
= 3 V
V
= 3 V
= 15 pF
= 5.1 kΩ (pullup to V
= 25°C
DD
DD
L
L
Overdrive = 10 mV
C
R
T
R
T
= 5.1 kΩ (pullup to V
= 25°C
)
DD
)
L
DD
C
= 50 pF
L
A
A
3
0
3
0
20 mV
C
= 15 pF
L
5 mV
10 mV
C
= 100 pF
L
100
0
100
0
0
100 200 300 400 500 600 700 800 900 1000
– Low-to-High-Level Output
0
100 200 300 400 500 600 700 800 900 1000
– Low-to-High-Level Output
t
t
PLH
PLH
Propagation Delay Time – ns
Propagation Delay Time – ns
Figure 7
Figure 8
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLV2354 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 9(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 9(b) for the V
accuracy.
test rather than changing the input voltages to provide greater
ICR
5 V
1 V
5.1 kΩ
5.1 kΩ
+
–
+
–
Applied V
Limit
Applied V
Limit
IO
IO
V
O
V
O
– 4 V
(a) V WITH V = 0
IO IC
(b) V WITH V = 4 V
IO IC
Figure 9. Method for Verifying That Input Offset Voltage Is Within Specified Limits
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes states.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
Figure 10 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage dividers R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
V
DD
C3
0.68 µF
R5
1.8 kΩ, 1%
U1b 1/4
TLV2354
C2
1 µF
U1c 1/4
Buffer
+
–
TLV2354
R6
5.1 kΩ
–
+
DUT
–
+
R7
1 MΩ
R4
47 kΩ
V
IO
(×100)
Integrator
R1
240 kΩ
R8
1.8 kΩ, 1%
U1a 1/4
TLV2354
C4
0.1 µF
–
+
C1
0.1 µF
Triangle
R9
10 kΩ, 1%
Generator
R10
100 Ω, 1%
R2
10 kΩ
R3
100 Ω
Figure 10. Circuit for Input Offset Voltage Measurement
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012C – MAY 1992 – REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
Propagationdelaytimeisdefinedastheintervalbetweentheapplicationofaninputstepfunctionandtheinstantwhen
the output crosses V = 1 V with V
= 3 V or when the output crosses V = 1.4 V with V
= 5 V. Propagation delay
O
DD
O
DD
time, low-to-high-level output, is measured from the leading edge of the input pulse, while propagation delay time,
high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation-delay-time measurement
at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced
by the adjustment at the inverting input (as shown in Figure 11) so that the circuit is just at the transition point. Then
a low signal, for example a 105-mV or 5-mV overdrive, causes the output to change state.
V
DD
Pulse
Generator
1 µF
5.1 kΩ
50 Ω
+
–
DUT
+ 1 V
Input Offset Voltage
Compensation
Adjustment
C
10 Ω
10 Turn
L
(see Note A)
1 kΩ
– 1 V
0.1 µF
TEST CIRCUIT
Overdrive
Overdrive
Input
100 mV
Input
100 mV
90%
90%
Low- to High-
Level Output
High- to Low-
Level Output
V
= 1 V With V
or
= 1.4 V With V
= 3 V
DD
O
V
O
= 5 V
DD
10%
10%
t
t
r
f
t
t
PHL
PLH
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 11. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9688201Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9688201Q2A
TLV2354
MFKB
5962-9688201QCA
5962-9688201QDA
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9688201QC
A
TLV2354MJB
W
5962-9688201QD
A
TLV2354MWB
TLV2354ID
TLV2354IDG4
TLV2354IDR
TLV2354IDRG4
TLV2354IN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
14
14
14
14
14
14
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TLV2354I
TLV2354I
TLV2354I
TLV2354I
TLV2354IN
TLV2354IN
TY2354
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
PDIP
N
Pb-Free
(RoHS)
TLV2354INE4
TLV2354IPW
TLV2354IPWG4
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
TSSOP
TSSOP
PW
PW
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
90
Green (RoHS
& no Sb/Br)
TY2354
TLV2354IPWLE
TLV2354IPWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TY2354
TY2354
TLV2354IPWRG4
TLV2354MFKB
ACTIVE
ACTIVE
TSSOP
LCCC
PW
FK
14
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
TBD
POST-PLATE
-55 to 125
5962-
9688201Q2A
TLV2354
MFKB
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TLV2354MJB
TLV2354MWB
ACTIVE
CDIP
CFP
J
14
14
1
TBD
A42
A42
N / A for Pkg Type
-55 to 125
5962-9688201QC
A
TLV2354MJB
ACTIVE
W
1
TBD
N / A for Pkg Type
-55 to 125
5962-9688201QD
A
TLV2354MWB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
OTHER QUALIFIED VERSIONS OF TLV2354, TLV2354M :
Catalog: TLV2354
•
Military: TLV2354M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV2354IDR
SOIC
D
14
14
2500
2000
330.0
330.0
16.4
12.4
6.5
6.9
9.0
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
TLV2354IPWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2354IDR
SOIC
D
14
14
2500
2000
367.0
367.0
367.0
367.0
38.0
35.0
TLV2354IPWR
TSSOP
PW
Pack Materials-Page 2
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