TLV2369 [TI]
适用于成本敏感型应用的双路、800nA、1.8V、RRIO 零交叉失真运算放大器;
| 型号： | TLV2369 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于成本敏感型应用的双路、800nA、1.8V、RRIO 零交叉失真运算放大器 放大器 运算放大器 |
| 文件： | 总28页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV369, TLV2369
ZHCSF19 –MAY 2016
TLVx369 具有零交叉失真的成本优化型
800nA、1.8V、轨到轨 I/O 运算放大器
1 特性
3 说明
1
•
成本优化型精密放大器，具有毫微功耗：800nA/通
道（典型值）
TLV369 系列单通道和双通道运算放大器是成本优化型
1.8V 毫微功耗放大器的典型代表。
•
•
•
•
•
•
•
低偏移电压：400μV（典型值）
轨到轨输入和输出
该系列放大器由 1.8V 至 5.5V 的单电源供电运行，并
且配有零交叉失真电路，可在整个共模输入范围内保持
较高线性度且无交叉失真，从而实现真正的轨到轨输
入。该系列还兼容符合行业标准的 3.0V、3.3V 和
5.0V 标称电压。
零交叉失真
低偏移漂移：0.5µV/°C（典型值）
增益带宽积：850MHz
电源电压：1.8V 至 5.5V
微型封装：SC70-5、VSSOP-8
TLV369（单通道版本）采用 5 引脚 SC70 封装。
TLV2369（双通道版本）采用 8 引脚超薄小外形尺寸
(VSSOP) 和小外形尺寸集成电路 (SOIC) 封装。
2 应用
•
•
•
•
血糖仪
器件信息(1)
测试设备
器件型号
TLV369
封装
SC70 (5)
封装尺寸（标称值）
低功耗传感器信号调节
便携式设备
2.00mm × 1.25mm
超薄小外形尺寸封装
(VSSOP) (8)
3.00mm × 3.00mm
4.90mm x 3.91mm
TLV2369
SOIC (8)
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
TLV369 系列消除了整个电源电压范围内的
交叉失真
100
80
60
40
20
0
–20
–40
–60
–80
–100
10 Typical Units Shown
VS = 5 V
Common-Mode Voltage (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS757
TLV369, TLV2369
ZHCSF19 –MAY 2016
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
8.3 System Examples .................................................. 14
Power Supply Recommendations...................... 15
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: TLV369 ................................... 5
6.5 Thermal Information: TLV2369 ................................. 5
6.6 Electrical Characteristics........................................... 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 器件和文档支持 ..................................................... 17
11.1 文档支持 ............................................................... 17
11.2 社区资源................................................................ 17
11.3 商标....................................................................... 17
11.4 静电放电警告......................................................... 17
11.5 Glossary................................................................ 17
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
日期
修订版本
注释
2016 年 5 月
*
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
TLV369, TLV2369
www.ti.com.cn
ZHCSF19 –MAY 2016
5 Pin Configuration and Functions
TLV369: DCK Package
5-Pin SC70
Top View
+IN
V-
1
2
3
5
4
V+
-IN
OUT
Pin Functions: TLV369
PIN
TLV369
I/O
DESCRIPTION
NAME
DCK (SC70)
–IN
+IN
3
1
4
2
5
I
Negative (inverting) input
I
Positive (noninverting) input
Output
OUT
V–
O
—
—
Negative (lowest) power supply or ground (for single-supply operation)
Positive (highest) power supply
V+
TLV2369: D Package
8-Pin SOIC
TLV2369: DGK Package
8-Pin VSSOP
Top View
Top View
OUT A
-IN A
+IN A
V-
V+
1
2
3
4
8
7
6
5
OUT A
-IN A
+IN A
V-
1
8
7
6
5
V+
OUT B
-IN B
+IN B
2
3
4
OUT B
-IN B
+IN B
Pin Functions: TLV2369
PIN
TLV2369
I/O
DESCRIPTION
NAME
DGK
(VSSOP)
D (SOIC)
–IN A
–IN B
+IN A
+IN B
OUT A
OUT B
V–
2
6
3
5
1
7
4
8
2
6
3
5
1
7
4
8
I
I
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Output, channel A
I
I
O
O
—
—
Output, channel B
Negative (lowest) power supply
Positive (highest) power supply
V+
Copyright © 2016, Texas Instruments Incorporated
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TLV369, TLV2369
ZHCSF19 –MAY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
+7
UNIT
V
Supply, VS = (V+) – (V–)
Signal input pin(2)
Signal input pin(2)
Output short-circuit(3)
Voltage
(V–) – 0.5
–10
(V+) + 0.5
10
V
mA
mA
°C
Current
Continuous
Operating, TA
–40
–65
125
150
150
Temperature
Junction, TJ
Storage, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to VS / 2, one amplifier per package.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted).
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
MIN
1.8
NOM
MAX
5.5
UNIT
VS
Supply voltage
V
Specified temperature
–40
85
°C
4
Copyright © 2016, Texas Instruments Incorporated
TLV369, TLV2369
www.ti.com.cn
ZHCSF19 –MAY 2016
6.4 Thermal Information: TLV369
TLV369
THERMAL METRIC(1)
DCK (SC70)
5 PINS
293.3
95.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
83.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.9
ψJB
82.4
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: TLV2369
TLV2369
THERMAL METRIC(1)
D (SOIC)
8 PINS
121.5
66.3
DGK (VSSOP)
8 PINS
168.5
58.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62.5
88.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.8
9.3
ψJB
61.9
87.6
RθJC(bot)
n/a
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF19 –MAY 2016
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6.6 Electrical Characteristics
VS (total supply voltage) = 1.8 V to 5.5 V; at TA = 25°C, and RL = 100 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
At TA= 25°C
0.4
0.85
0.5
2
VOS
Input offset voltage
mV
At TA = –40°C to +85°C
At TA = –40°C to +85°C
VS = 1.8 V to 5.5 V
dVOS/dT
PSRR
Drift
Power-supply rejection ratio
μV/°C
80
94
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
V–
80
V+
V
CMRR
(V–) ≤ VCM ≤ (V+)
110
dB
INPUT BIAS CURRENT
At TA= 25°C
10
See Figure 8
10
pA
pA
IB
Input bias current
Input offset current
At TA= –40°C to +85°C
IOS
INPUT IMPEDANCE
1013 || 3
1013 || 6
ZID
ZIC
NOISE
En
Differential
Ω || pF
Ω || pF
Common-mode
Input voltage noise
f = 0.1 Hz to 10 Hz
f = 1 kHz
4
300
1
μVPP
en
Input voltage noise density
Input current noise density
nV/√Hz
fA/√Hz
in
f = 1 kHz
OPEN-LOOP GAIN
At VS = 5.5 V, 100 mV ≤ VO ≤ (V+) – 100 mV,
RL = 100 kΩ
130
120
AOL
Open-loop voltage gain
dB
At VS = 5.5 V, 500 mV ≤ VO ≤ (V+) – 500 mV,
RL = 10 kΩ
80
OUTPUT
VO
Voltage output swing from rail
Short-circuit current
RL = 10 kΩ
25
mV
mA
ISC
10
CLOAD
Capacitive load drive
See Figure 10
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
12
0.005
250
kHz
V/µs
µs
Slew rate
G = 1
tOR
Overload recovery time
VIN × gain = VS
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current
1.8
5.5
V
IO = 0 mA, at VS = 5.5 V
800
1300
nA
TEMPERATURE
Specified range
Operating range
–40
–40
85
°C
°C
TA
125
6
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF19 –MAY 2016
6.7 Typical Characteristics
at TA = 25°C, VS = 5 V, and RL = 100 kΩ connected to VS / 2 (unless otherwise noted)
100
80
60
40
20
0
–20
–40
–60
–80
–100
Time (500 ms/div)
Common-Mode Voltage (V)
10 typical units shown, VS = 5 V
Figure 2. 0.1-Hz to 10-Hz Noise
Figure 1. Normalized Offset Voltage vs
Common-Mode Voltage
3
2.5
2
140
120
100
80
180
135
90
RL = 10 kΩ
RL = 100 kΩ
Gain
1.5
1
60
40
Phase
20
45
0.5
0
0
–20
0.001 0.01
0
10k 20k
0.1
1
10
100
1k
–75
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
VS = 5.5 V
Figure 3. Open-Loop Gain and Phase vs Frequency
Figure 4. Open-Loop Gain vs Temperature
120
25
20
RL = 10 kΩ
100
80
15
10
5
60
0
-5
40
-10
-15
-20
-25
RL = 10 kΩ
20
0
10
100
1k
10k 20k
–75
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
Figure 5. Common-Mode Rejection Ratio vs Frequency
Figure 6. Output Voltage Swing from Rail vs Temperature
Copyright © 2016, Texas Instruments Incorporated
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ZHCSF19 –MAY 2016
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Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, and RL = 100 kΩ connected to VS / 2 (unless otherwise noted)
3
2.5
2
10k
1k
100
10
1.5
1
1
0.5
0
0.1
0.01
100
1k
2k
–50
–25
0
25
50
75
100
125
Frequency (Hz)
Temperature (°C)
Figure 7. Maximum Output Voltage vs Frequency
Figure 8. Input Bias Current vs Temperature
20
18
16
14
12
10
8
10G
1G
100k
10k
1k
G = –1
G = 1
6
4
100
10
2
0
0
10
100
1k
10k
100k
1G
10
100
Frequency (Hz)
Capacitive Load (pF)
Figure 9. Open-Loop Output Impedance vs Frequency
Figure 10. Small-Signal Overshoot vs Capacitive Load
Time (100 μs/div)
Time (250 μs/div)
CL = 20 pF
Figure 11. Small-Signal Step Response
Figure 12. Large-Signal Step Response
8
Copyright © 2016, Texas Instruments Incorporated
TLV369, TLV2369
www.ti.com.cn
ZHCSF19 –MAY 2016
Typical Characteristics (continued)
at TA = 25°C, VS = 5 V, and RL = 100 kΩ connected to VS / 2 (unless otherwise noted)
Input
Output
Time (500 μs/div)
Figure 13. Overload Recovery
Copyright © 2016, Texas Instruments Incorporated
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TLV369, TLV2369
ZHCSF19 –MAY 2016
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLVx369 family of operational amplifiers minimizes power consumption and operates on supply voltages as
low as 1.8 V. The zero-crossover distortion circuitry enables high linearity over the full input common-mode
range, achieving true rail-to-rail input from a 1.8-V to 5.5-V single supply.
7.2 Functional Block Diagram
V+
Low-Noise
Charge Pump
Bias Circuitry
+IN
-IN
OUT
Input Stage Load
Bias Circuitry
V-
10
Copyright © 2016, Texas Instruments Incorporated
TLV369, TLV2369
www.ti.com.cn
ZHCSF19 –MAY 2016
7.3 Feature Description
7.3.1 Operating Voltage
The TLV369 series os op amps are fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters
that vary significantly with supply voltage are described in the Typical Characteristics section.
7.3.2 Input Common-Mode Voltage Range
The TLV369 family is designed to eliminate the input offset transition region typically present in most rail-to-rail,
complementary-stage operational amplifiers, allowing the TLV369 family of amplifiers to provide superior
common-mode performance over the entire input range.
The input common-mode voltage range of the TLV369 family typically extends to each supply rail. CMRR is
specified from the negative rail to the positive rail; see Figure 1, Normalized Offset Voltage vs Common-Mode
Voltage.
7.3.3 Protecting Inputs from Overvoltage
Input currents are typically 10 pA. However, large inputs (greater than 500 mV beyond the supply rails) can
cause excessive current to flow in or out of the input pins. Therefore, in addition to keeping the input voltage
between the supply rails, the input current must also be limited to less than 10 mA. This limiting is easily
accomplished with an input resistor, as shown in Figure 14.
A current-limiting resistor is required if the input voltage
exceeds the supply rails by ³ 0.5 V.
5 V
IOVERLOAD
10 mA, max
TLV369
VOUT
VIN
5 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Input Current Protection for Voltages That Exceed the Supply Voltage
7.4 Device Functional Modes
The TLV369 family has a single functional mode. These devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
Copyright © 2016, Texas Instruments Incorporated
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TLV369, TLV2369
ZHCSF19 –MAY 2016
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
When designing for ultra-low power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors can react with stray capacitance in the circuit and the input capacitance
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. Use of
a feedback capacitor assures stability and limits overshoot or gain peaking.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 15. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on
the output. In addition, amplification can be added by selecting the input resistor RI and the feedback resistor RF.
RF
VSUP+
RI
VOUT
+
VIN
VSUP-
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at
±2.5 V is sufficient to accommodate this application.
12
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ZHCSF19 –MAY 2016
Typical Application (continued)
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:
VOUT
AV
=
V
IN
(1)
(2)
1.8
AV
=
= -3.6
-0.5
When the desired gain is determined, choose a value for RI or RF. Choosing a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures that the device does not draw too much current. The trade-off is that very large
resistors (100s of kilohms) draw the smallest current but generate the highest noise. Very small resistors (100s of
ohms) generate low noise but draw high current. This example uses 10 kΩ for RI, meaning 36 kΩ is used for RF.
These values are determined by Equation 3:
RF
AV = -
RI
(3)
8.2.3 Application Curve
2
1.5
1
Input
Output
0.5
0
-0.5
-1
-1.5
-2
Time
Figure 16. Inverting Amplifier Input and Output
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8.3 System Examples
8.3.1 Battery Monitoring
The low operating voltage and quiescent current of the TLV369 series make the family an excellent choice for
battery-monitoring applications, as shown in Figure 17.
RF
R1
+IN
+
IBIAS
OUT
TLV369
VSTATUS
VBATT
-IN
VREF
RBIAS
R2
REF1112
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Battery Monitor
In this circuit, VSTATUS is high as long as the battery voltage remains above 2 V. A low-power reference is used to
set the trip point. Resistor values are selected as follows:
1. Selecting RF: Select RF such that the current through RF is approximately 1000 times larger than the
maximum bias current over temperature, as given by Equation 4:
VREF
RF =
1000 (IBMAX
)
1.2 V
1000 (50 pA)
=
= 24 MW » 20 MW
(4)
(5)
2. Choose the hysteresis voltage, VHYST. For battery-monitoring applications, 50 mV is adequate.
3. Calculate R1 as calculated by Equation 5:
V
HYST
50 mV
R = RF
= 20 MW
= 420 kW
1
V
2.4 V
BATT
4. Select a threshold voltage for VIN rising (VTHRS) = 2.0 V.
5. Calculate R2 as given by Equation 6:
1
R =
2
V
THRS
1
1
-
-
R1 R1
(V )
BATT
1
=
2 V
1
1
-
-
420 kW 20 MW
(
)
1.2 V ´ 420 kW
= 650 kW
(6)
6. Calculate RBIAS: The minimum supply voltage for this circuit is 1.8 V. The REF1112 has a current
requirement of 1.2 μA (max). Providing the REF1112 with 2 μA of supply current assures proper operation.
Therefore, RBIAS is as given by Equation 7.
V
BATTMIN
1.8 V
R
=
=
= 0.9 MW
BIAS
I
2 mA
BIAS
(7)
14
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ZHCSF19 –MAY 2016
System Examples (continued)
8.3.2 Window Comparator
Figure 18 shows the TLV2369 used as a window comparator. The threshold limits are set by VH and VL, with VH
greater than VL. When VIN is less than VH, the output of A1 is low. When VIN is greater than VL, the output of A2
is low. Therefore, both op amp outputs are at 0 V as long as VIN is between VH and VL. This architecture results
in no current flowing through either diode, Q1 is in cutoff, with the base voltage at 0 V, and VOUT forced high.
3 V
3 V
R1
VH
D1(2)
A1
1/2
3V
TLV2369
R2
R7
5.1 kW
VOUT
RIN
(1)
R5
2 kW
10 kW
Q1(3)
VIN
R6
5.1 kW
3 V
1/2
3 V
D2(2)
A2
R3
R4
TLV2369
VL
Copyright © 2016, Texas Instruments Incorporated
Figure 18. TLV2369 as a Window Comparator
If VIN falls below VL, the output of A2 is high, current flows through D2, and VOUT is low. Likewise, if VIN rises
above VH, the output of A1 is high, current flows through D1, and VOUT is low. The window comparator threshold
voltages are set as shown by Equation 8 and Equation 9:
R2
V =
H
R1 + R2
(8)
R4
V =
L
R3 + R4
(9)
9 Power Supply Recommendations
The TLV369 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout
Guidelines section.
Copyright © 2016, Texas Instruments Incorporated
15
TLV369, TLV2369
ZHCSF19 –MAY 2016
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI)
noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of
the ground current. For more detailed information, see Circuit Board Layout Techniques, SLOA089.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keep RF and RG close to the inverting
input in order to minimize parasitic capacitance, as shown in Figure 19.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
VS+
Run the input traces as
far away from the supply
lines as possible.
VIN
VSœ
+IN
V+
GND
Vœ
Use a low-ESR, ceramic
bypass capacitor.
Use a low-ESR,
ceramic bypass
capacitor.
RG
OUT
VOUT
œIN
GND
RF
Place components close to the device and
to each other to reduce parasitic errors.
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Operational Amplifier Board Layout for Noninverting Configuration
VIN
+
RG
VOUT
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Schematic Representation of Figure 19
16
版权 © 2016, Texas Instruments Incorporated
TLV369, TLV2369
www.ti.com.cn
ZHCSF19 –MAY 2016
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
使用 TLVx369 时，建议参考下列相关文档，文档下载地址为 www.ti.com.cn（除非另外注明）。
•
•
•
•
《REF1112 数据表》，SBOS283
《电路板布局布线技巧》，SLOA089
《运算放大器应用 手册》，SBOA092
《模拟工程师速查参考》，SLWY038
11.1.1.1 相关链接
表 1 列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访问。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
TLV369
TLV2369
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV2369IDGKR
TLV2369IDGKT
TLV2369IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
5
5
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
13JV
13JV
NIPDAUAG
NIPDAU
NIPDAU
NIPDAU
2500 RoHS & Green
3000 RoHS & Green
TL2369
12K
TLV369IDCKR
TLV369IDCKT
SC70
DCK
DCK
SC70
250
RoHS & Green
12K
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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