TLV2381IDBVTG4 [TI]
10-uA/Channel, 160kHz, RRIO Op Amp 5-SOT-23 -40 to 125;
| 型号： | TLV2381IDBVTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-uA/Channel, 160kHz, RRIO Op Amp 5-SOT-23 -40 to 125 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
FAMILY OF MICROPOWER RAIL-TO-RAIL INPUT AND OUTPUT
OPERATIONAL AMPLIFIERS
FEATURES
DESCRIPTION
BiMOS Rail-to-Rail Input/Output
The TLV238x single supply operational amplifiers
Input Bias Current . . . 1 pA
provide rail-to-rail input and output capability. The
TLV238x takes the minimum operating supply voltage
down to 2.7 V over the extended industrial temperature
range, while adding the rail-to-rail output swing feature.
The TLV238x also provides 160-kHz bandwidth from
only 7 µA. The maximum recommended supply voltage
is 16 V, which allows the devices to be operated from
( 8 V supplies down to 1.35 V) two rechargeable cells.
High Wide Bandwidth . . . 160 kHz
High Slew Rate . . . 0.1 V/µs
Supply Current . . . 7 µA (per channel)
Input Noise Voltage . . . 90 nV/√Hz
Supply Voltage Range . . . 2.7 V to 16 V
Specified Temperature Range
– –40°C to 125°C . . . Industrial Grade
Ultra-Small Packaging
– 5 Pin SOT-23 (TLV2381)
The combination of rail-to-rail inputs and outputs make
them good upgrades for the TLC27Lx family—offering
more bandwidth at a lower quiescent current. The offset
voltage is lower than the TLC27LxA variant.
APPLICATIONS
To maintain cost effectiveness the TLV2381/2 are only
available in the extended industrial temperature range.
This means that one device can be used in a wide range
of applications that include PDAs as well as automotive
sensor interface.
Portable Medical
Power Monitoring
Low Power Security Detection Systems
Smoke Detectors
All members are available in SOIC, with the singles in
the small SOT-23 package, duals in the MSOP.
SELECTION GUIDE
V
[V]
I
/ch
V
V
[mV]
I
IB
GBW
[MHz]
SLEW RATE
V , 1 kHz
n
S
Q
ICR
[V]
IO
DEVICE
[µA]
[pA]
[V/µs]
[nV/√Hz]
100
100
68
TLV238x
TLV27Lx
TLC27Lx
OPAx349
OPAx347
TLC225x
2.7 to 16
2.7 to 16
4 to 16
10
–0.2 to V + 0.2
4.5
60
0.16
0.16
0.06
0.06
0.03
0.02
0.01
0.02
S
11
–0.2 to V – 1.2
5
60
S
17
–0.2 to V – 1.5
10/5/2
10
60
0.085
0.070
0.35
S
1.8 to 5.5
2.3 to 5.5
2.7 to 16
2
–0.2 to V + 0.2
10
300
60
S
34
–0.2 to V + 0.2
6
10
S
62.5
0 to V – 1.5
1.5/0.85
60
0.200
19
S
NOTE: All dc specs are maximums while ac specs are typicals.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2001–2003 Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
CODE
PRODUCT
PACKAGE
SYMBOL
TEMPERATURE
RANGE
ORDER NUMBER TRANSPORT MEDIA
TLV2381ID
TLV2381IDR
TLV2381IDBVR
TLV2381IDBVT
TLV2382ID
Tube
TLV2381ID
TLV2381IDBV
TLV2382ID
SOIC-8
SOT-23
SOIC-8
D
2381I
VBKI
2382I
Tape and Reel
DBV
D
–40°C to 125°C
Tape and Reel
Tube
TLV2382IDR
Tape and Reel
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
S
Input voltage, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V + 0.2 V
I
S
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
O
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
ID
S
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Operating free-air temperature range, T : I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 125°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Relative to GND pin.
2. Maximum is 16.5 V or V +0.2 V whichever is the lesser value.
S
DISSIPATION RATING TABLE
≤ 25°C
PACKAGE
θ
θ
JA
T
A
T = 85°C
A
JC
(°C/W)
38.3
55
(°C/W)
POWER RATING POWER RATING
D (8)
176
710 mW
385 mW
425 mW
370 mW
201 mW
221 mW
DBV (5)
DBV (6)
324.1
294.3
55
2
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
recommended operating conditions
MIN
1.35
2.7
MAX
8
UNIT
Dual supply
Supply voltage, (V )
S
V
Single supply
16
Input common-mode voltage range
–0.2 V +0.2
V
S
Operating free air temperature, T
I-suffix
–40
125
°C
A
electrical characteristics at recommended operating conditions, V = 2.7 V, 5 V, and 15 V (unless
S
otherwise noted)
dc performance
†
PARAMETER
Input offset voltage
Offset voltage drift
TEST CONDITIONS
T
A
MIN
TYP
MAX
4.5
UNIT
mV
25°C
Full range
25°C
0.5
V
IO
V
R
= V /2,
S
= 100 kΩ
V
R
= V /2
= 50 Ω
S
IC
L
O S
6.5
α
VIO
1.1
69
µV/°C
25°C
54
53
71
70
58
57
72
70
65
64
72
70
80
77
80
77
77
74
V
R
= 0 V to V ,
S
IC
= 50 Ω
Full range
25°C
S
V
S
V
S
V
S
= 2.7 V
dB
dB
dB
86
74
V
R
= 0 V to V –1.3 V,
S
= 50 Ω
IC
Full range
25°C
S
V
R
= 0 V to V ,
= 50 Ω
S
IC
Full range
25°C
S
CMRR Common-mode rejection ratio
= 5 V
88
V
R
= 0 V to V –1.3 V,
= 50 Ω
S
Full range
25°C
S
80
V
R
= 0 V to V ,
= 50 Ω
S
Full range
25°C
S
= 15 V
90
V
R
= 0 V to V –1.3 V,
= 50 Ω
S
Full range
25°C
S
100
100
83
V
S
V
S
V
S
= 2.7 V
= 5 V
Full range
25°C
Large-signal differential voltage
amplification
V
R
=V /2,
S
= 100 kΩ
A
VD
dB
Full range
25°C
L
= 15 V
Full range
†
Full range is –40°C to 125°C.
input characteristics
PARAMETER
TEST CONDITIONS
T
MIN
TYP
MAX
60
UNIT
A
≤25°C
≤70°C
≤125°C
≤25°C
≤70°C
≤125°C
25°C
1
I
Input offset current
100
1000
60
pA
IO
IB
V
R
= V /2,
S
V
R
= V /2,
= 50 Ω
S
IC
L
O S
= 100 kΩ ,
1
I
Input bias current
200
1000
pA
r
Differential input resistance
1000
8
GΩ
i(d)
C
Common-mode input capacitance
f = 1 kHz
25°C
pF
IC
3
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
electrical characteristics at recommended operating conditions, V = 2.7 V, 5 V, and 15 V (unless
S
otherwise noted) (continued)
power supply
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP
MAX
10
UNIT
25°C
Full range
25°C
7
I
Supply current (per channel)
V
= V /2
µA
DD
S
O
15
74
70
82
V
V
= 2.7 V to 16V,
= V /2 V
No load,
S
IC
PSRR
Power supply rejection ratio (∆V /∆V
IO
)
dB
S
Full range
S
†
Full range is –40°C to 125°C for I suffix.
output characteristics
†
PARAMETER
TEST CONDITIONS
T
A
MIN
200
220
120
200
120
150
800
900
400
500
TYP
MAX
UNIT
25°C
Full range
25°C
160
V
V
V
V
= 2.7 V
= 5 V
S
S
S
S
85
50
V
I
= V /2,
S
IC
= 100 µA
mV
Full range
25°C
O
V
O
Output voltage swing from rail
= 15 V
= 5 V
Full range
25°C
420
200
400
Full range
25°C
V
I
= V /2,
IC S
= 500 µA
mV
O
V
V
= 15 V
= 2.7 V
S
Full range
25°C
I
O
Output current
V
O
= 0.5 V from rail
µA
S
†
Full range is –40°C to 125°C for I suffix.
dynamic performance
PARAMETER
Gain bandwidth product
TEST CONDITIONS
= 100 kΩ , = 10 pF, f = 1 kHz
T
MIN
TYP
160
0.06
0.05
0.08
62
MAX
UNIT
A
GBP
SR
R
C
25°C
25°C
kHz
L
L
V
C
= 2 V,
= 10 pF
R
= 100 kΩ,
L
O(pp)
Slew rate at unity gain
–40°C
125°C
25°C
V/µs
L
φ
M
Phase margin
Gain margin
°
R
= 100 kΩ,
C
= 50 pF
L
L
25°C
6.7
dB
Rise
Fall
31
V
C
= 1 V, A = –1,
V
(STEP)pp
= 10 pF,
t
s
Settling time (0.1%)
25°C
µs
R = 100 kΩ
61
L
L
noise/distortion performance
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP
MAX
UNIT
V
n
Equivalent input noise voltage
f = 1 kHz
25°C
90
nV/√Hz
4
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input offset voltage
vs Common-mode input voltage
1, 2, 3
4
IO
/I
I
Input bias and offset current
High-level output voltage
Low-level output voltage
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Supply voltage
IB IO
V
5, 7, 9
6, 8, 10
11
OH
OL
V
I
Q
Quiescent current
vs Free-air temperature
12
Supply voltage and supply current ramp up
Differential voltage gain and phase shift
Gain-bandwidth product
13
A
vs Frequency
14
VD
GBP
vs Free-air temperature
vs Load capacitance
vs Frequency
15
φ
m
Phase margin
16
CMRR Common-mode rejection ratio
17
PSRR
Power supply rejection ratio
Input referred noise voltage
Slew rate
vs Frequency
18
vs Frequency
19
SR
vs Free-air temperature
vs Frequency
20
V
Peak-to-peak output voltage
Inverting small-signal response
Inverting large-signal response
Crosstalk
21
O(PP)
22
23
vs Frequency
24
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
2000
2000
1500
1000
500
2000
1500
1000
500
0
V
T
= 2.7 V
= 25°C
V
T
= 5 V
= 25°C
S
A
S
A
V
= 15 V
1500
1000
S
T
A
= 25°C
500
0
0
–500
–1000
–1500
–2000
–500
–1000
–1500
–2000
–500
–1000
–1500
–2000
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
–0.2
7.5
15.2
V
– Common-Mode Input Voltage – V
V
– Common-Mode Input Voltage – V
IC
IC
V
– Common-Mode Input Voltage – V
IC
Figure 1
Figure 2
Figure 3
5
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
INPUT BIAS AND INPUT
OFFSET CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
15
14
13
12
11
10
9
15
100
V
= 15 V
S
V
= 15 V
S
V
V
V
= 2.5 V
DD
–40°C
90
125°C
70°C
25°C
0°C
= 0
12.5
10
IC
O
0°C
80
70
60
50
40
30
20
10
0
= 0
25°C
R
= 50 Ω
S
70°C
8
7
7.5
6
5
4
5
I
IB
125°C
3
2
1
0
I
IO
2.5
–40°C
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8 10 12 14 16 18 20 22 24
25
45
65
85
105
125
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
T
A
– Free-Air Temperature – °C
OH
Figure 4
Figure 5
Figure 6
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5
5
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
V
= 5 V
V
= 5 V
S
V = 2.7 V
S
S
4.5
4.5
4
125°C
70°C
–40°C
–40°C
4
0°C
0°C
3.5
3
3.5
25°C
25°C
70°C
25°C
0°C
3
70°C
2.5
2.5
2
1.5
1
2
1.5
1
125°C
125°C
–40°C
0.5
0.3
0
0.5
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5 5.5
6
0.4
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.2
0.6
0.8
1
1.2 1.4
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
OH
Figure 7
Figure 8
Figure 9
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
8
7
6
5
4
3
2
1
0
8
7
6
2.7
2.4
2.1
1.8
1.5
1.2
16 V
V
= 2.7 V
125°C
70°C
S
5 V
125°C
70°C
5
4
3
2
2.7 V
25°C
0°C
–40°C
25°C
0°C
0.9
0.6
0.3
0
–40°C
1
0
–40 –25–10
5 20 35 50 65 80
95 110
125
0
0.2
0.4
0.6
0.8
1
1.2 1.4
0
2
4
6
8
10
12 14 16
T
A
– Free-Air Temperature – °C
I
– Low-Level Output Current – mA
V
– Supply Voltage – V
OL
S
Figure 12
Figure 10
Figure 11
6
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN
AND PHASE SHIFT
vs
SUPPLY VOLTAGE AND
FREQUENCY
SUPPLY CURRENT RAMP UP
40
120
100
80
15
V
= 5 V
S
V
S
R
C
T
= 100 kΩ
= 10 pF
= 25°C
L
L
A
10
5
0°
V
O
30°
0
V
R
C
= 0 to 15 V,
= 100 Ω,
= 10 pF,
= 25°C
S
L
L
60
60°
90°
40
T
A
15
10
I
Q
20
0
120°
150°
180°
5
0
–20
0
5
10
15
20
25
30
0.1
1
10
100
1 k 10 k 100 k 1 M
t – Time – ms
f – Frequency – Hz
Figure 13
Figure 14
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
PHASE MARGIN
vs
LOAD CAPACITANCE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
80
170
160
120
V
= 5 V
S
110
100
90
80
70
60
50
40
30
20
10
0
V
T
= 5 V
= 25°C
S
A
70
60
50
40
30
20
10
0
R
T
A
= 100 kΩ
= 25°C
L
V
= 2.7 V
S
150
140
130
V
= 5 V
S
V
= 15 V
S
120
110
100
–40 –25 –10 5 20 35 50 65 80 95 110 125
10
100
1000
10
100
1 k
10 k
100 k
1 M
T
A
– Free-Air Temperature – °C
C
– Load Capacitance – pF
L
f – Frequency – Hz
Figure 15
Figure 16
Figure 17
SLEW RATE
vs
FREE-AIR TEMPERATURE
INPUT REFERRED NOISE VOLTAGE
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
0.09
100
250
200
150
100
V
= 5 V,
S
V
T
A
= 2.5 V
S
= 25°C
90
80
70
0.08
0.07
0.06
0.05
SR+
G = 2,
= 100 kΩ
R
F
SR–
60
50
40
30
20
0.04
0.03
0.02
V = 5 V
S
Gain = 1
V
= 1
50
0
O
R
C
= 100 kΩ
= 50 pF
L
L
0.01
0
10
0
1
10
100
1 k
10 k
100 k
10
100
1 k
10 k
100 k
1 M
–40 –25 –10 5 20 35 50 65 80 95 110 125
T
A
– Free-air Temperature – °C
f – Frequency – Hz
f – Frequency – Hz
Figure 19
Figure 20
Figure 18
7
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
TYPICAL CHARACTERISTICS
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
INVERTING SMALL-SIGNAL
RESPONSE
FREQUENCY
16
2
V = 3 V
I
PP
V
= 15 V
1.5
S
14
12
10
1
Gain = –1,
R
C
= 100 kΩ,
= 10 pF,
= 5 V,
L
L
0.5
R
C
= 100 kΩ,
= 10 pF,
L
L
V
V
S
O
0
–0.5
–1
THD+N <= 5%
8
6
4
= 3 V
,
PP
f = 1 kHz
V
= 5 V
S
V
–1.5
–2
2
0
= 2.7 V
S
V
= 3 V
PP
O
10
100
1000
1 k
10 k
–100
0
100 200 300 400 500 600 700
t – Time – µs
f – Frequency – Hz
Figure 22
Figure 21
CROSSTALK
vs
FREQUENCY
INVERTING LARGE-SIGNAL
RESPONSE
0
0.06
0.04
0.02
V
= 5 V
S
R
C
= 2 kΩ
= 10 pF
= 25°C
L
L
–20
V = 100 mV
I
PP
T
A
Gain = –1,
–40
–60
Channel 1 to 2
R
C
= 100 kΩ,
= 10 pF,
L
L
V
V
= 5 V,
= 100 mV
S
O
0
,
PP
–80
f = 1 kHz
–0.02
–0.04
–0.06
–100
–120
–140
V
= 100 mV
PP
O
10
100
1 k
10 k
100 k
–100
0
100 200 300 400 500 600 700
f – Frequency – Hz
t – Time – µs
Figure 23
Figure 24
8
www.ti.com
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
APPLICATION INFORMATION
offset voltage
The output offset voltage (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times the
OO
IO
IB
corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
R
F
I
IB–
R
G
+
–
+
R
R
R
R
F
F
V
I
V
V
1
I
R
1
I
R
V
O
OO
IO
IB
S
IB–
F
G
G
R
S
I
IB+
Figure 25. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The
simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 26).
R
R
F
G
V
R
R
O
F
1
1
V
1
sR1C1
I
G
V
DD
/2
–
1
V
O
f
+
–3dB
V
I
2 R1C1
R1
C1
Figure 26. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task.
For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure
to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
–3dB
2 RC
C2
R
F
1
R
=
G
R
F
2 –
)
(
R
Q
G
V
DD
/2
Figure 27. 2-Pole Low-Pass Sallen-Key Filter
9
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TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV238x, follow proper printed-circuit board design techniques. A
general set of guidelines is given in the following.
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets—Socketscanbeusedbutarenotrecommended. Theadditionalleadinductanceinthesocketpins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
10
www.ti.com
TLV2381
TLV2382
SLOS377A – SEPTEMBER 2001– REVISED JULY 2003
APPLICATION INFORMATION
general power dissipation considerations
For a given θ , the maximum power dissipation is shown in Figure 28 and is calculated by the following formula:
JA
T
–T
MAX
A
P
D
JA
Where:
P
= Maximum power dissipation of TLV238x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
1.5
1.25
1
θ
= 104°C/W
JA
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
–55–40 –25 –10
5
20 35 50 65 80 95 110 125
T
A
– Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 28. Maximum Power Dissipation vs Free-Air Temperature
TLV2381
D PACKAGE
(TOP VIEW)
TLV2382
D PACKAGE
(TOP VIEW)
TLV2381
DBV PACKAGE
(TOP VIEW)
NC
IN–
NC
1OUT
1IN–
1IN+
GND
V
DD
1
2
3
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
5
4
V
DD
OUT
GND
V
2OUT
2IN–
2IN+
DD
IN+
OUT
NC
GND
IN–
IN+
NC – No internal connection
11
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
TLV2381ID
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
D
8
5
5
5
5
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2381I
VBKI
VBKI
VBKI
VBKI
2381I
2381I
TLV2381IDBVR
TLV2381IDBVRG4
TLV2381IDBVT
TLV2381IDBVTG4
TLV2381IDG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
D
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
75
Green (RoHS
& no Sb/Br)
TLV2381IDR
SOIC
D
2500
Green (RoHS
& no Sb/Br)
TLV2381IP
TLV2382ID
PREVIEW
ACTIVE
PDIP
SOIC
P
D
8
8
TBD
Call TI
Call TI
-40 to 125
-40 to 125
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2382I
2382I
2382I
2382I
TLV2382IDG4
TLV2382IDR
TLV2382IDRG4
TLV2382IP
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
D
D
P
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2500
2500
Green (RoHS
& no Sb/Br)
ACTIVE
Green (RoHS
& no Sb/Br)
OBSOLETE
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLV2381IDBVR
TLV2381IDBVT
TLV2381IDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
8
3000
250
180.0
180.0
330.0
330.0
9.0
9.0
3.15
3.15
6.4
3.2
3.2
5.2
5.2
1.4
1.4
2.1
2.1
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
2500
2500
12.4
12.4
12.0
12.0
TLV2382IDR
SOIC
D
6.4
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV2381IDBVR
TLV2381IDBVT
TLV2381IDR
SOT-23
SOT-23
SOIC
DBV
DBV
D
5
5
8
8
3000
250
182.0
182.0
340.5
340.5
182.0
182.0
338.1
338.1
20.0
20.0
20.6
20.6
2500
2500
TLV2382IDR
SOIC
D
Pack Materials-Page 2
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相关型号：
TLV2382IDGK
DUAL OP-AMP, 6500uV OFFSET-MAX, 0.16MHz BAND WIDTH, PDSO8, ULTRA SMALL, PLASTIC, MSOP-8
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